--------------------------------------

-- OR gate
--
--------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------

entity OR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end OR_ent;

---------------------------------------

architecture OR_arch of OR_ent is
begin

process(x, y)
begin
-- truth table
if ((x='0') and (y='0')) then
F <= '0';
else
F <= '1';
end if;
end process;

end OR_arch;





















---------------------------------------
-- AND gate
-- --------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------------------

entity AND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end AND_ent;

--------------------------------------------------

architecture behav1 of AND_ent is
begin

process(x, y)
begin
-- compare to truth table
if ((x='1') and (y='1')) then
F <= '1';
else
F <= '0';
end if;
end process;

end behav1;


















-----------------------------------------
-- NOR gate --
-----------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-----------------------------------------

entity NOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end NOR_ent;

------------------------------------------

architecture behv1 of NOR_ent is
begin

process(x, y)
begin
-- compare to truth table
if (x='0' and y='0') then
F <= '1';
else
F <= '0';
end if;
end process;

end behv1;






















-----------------------------------------
-- NAND gate --
-- -----------------------------------------

library ieee;
use ieee.std_logic_1164.all;

------------------------------------------

entity NAND_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end NAND_ent;

------------------------------------------

architecture behv1 of NAND_ent is
begin

process(x, y)
begin
-- compare to truth table
if (x='1' and y='1') then
F <= '0';
else
F <= '1';
end if;
end process;

end behv1;



















--------------------------------------
-- XOR gate
--
-- --------------------------------------

library ieee;
use ieee.std_logic_1164.all;

--------------------------------------

entity XNOR_ent is
port( x: in std_logic;
y: in std_logic;
F: out std_logic
);
end XNOR_ent;

---------------------------------------

architecture behv1 of XNOR_ent is
begin

process(x, y)
begin
-- compare to truth table
if (x/=y) then
F <= '0';
else
F <= '1';
end if;
end process;

end behv1;






















-------------------------------------------------
-- VHDL code for 4:1 multiplexor
-- --
--
-- Multiplexor is a device to select different
-- inputs to outputs. we use 3 bits vector to
-- describe its I/O ports
-------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------

entity Mux is
port( I3: in std_logic_vector(2 downto 0);
I2: in std_logic_vector(2 downto 0);
I1: in std_logic_vector(2 downto 0);
I0: in std_logic_vector(2 downto 0);
S: in std_logic_vector(1 downto 0);
O: out std_logic_vector(2 downto 0)
);
end Mux;

-------------------------------------------------

architecture behv1 of Mux is
begin
process(I3,I2,I1,I0,S)
begin

-- use case statement
case S is
when "00" => O <= I0;
when "01" => O <= I1;
when "10" => O <= I2;
when "11" => O <= I3;
when others => O <= "ZZZ";
end case;

end process;
end behv1;











-- 2:4 Decoder -- --
-- decoder is a kind of inverse process
-- of multiplexor
-------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

-------------------------------------------------

entity DECODER is
port( I: in std_logic_vector(1 downto 0);
O: out std_logic_vector(3 downto 0)
);
end DECODER;

-------------------------------------------------

architecture behv of DECODER is
begin

-- process statement

process (I)
begin

-- use case statement

case I is
when "00" => O <= "0001";
when "01" => O <= "0010";
when "10" => O <= "0100";
when "11" => O <= "1000";
when others => O <= "XXXX";
end case;

end process;

end behv;















Half adder- dataflow

library ieee;
use ieee.std_logic_1164.all;
entity ha is
port(x,y:in std_logic;
s,c:out std_logic);
end ha;
architecture dataflow of ha is
begin
s<=x xor y;
c<=x and y;
end dataflow;


Full adder structural



library ieee;
use ieee.std_logic_1164.all;
entity xor1 is
port(x,y:in std_logic;d:out std_logic);
end xor1;

architecture behav1 of xor1 is
begin
d<=x xor y;
end behav1;

library ieee;
use ieee.std_logic_1164.all;
entity and1 is
port(a,b:in std_logic;c:out std_logic);
end and1;

architecture behav2 of and1 is
begin
c<=a and b;
end behav2;



library ieee;
use ieee.std_logic_1164.all;
entity or1 is
port(l,m:in std_logic;n:out std_logic);
end or1;

architecture behav3 of or1 is
begin
n<=l or m;
end behav3;

library ieee;
use ieee.std_logic_1164.all;
entity fa1 is
port(x,y,z:in std_logic;s,c:out std_logic);
end fa1;

architecture struct of fa1 is
component xor1
port(x,y:in std_logic;d:out std_logic);
end component;

component and1
port(a,b:in std_logic;c:out std_logic);
end component;

component or1
port(l,m:in std_logic;n:out std_logic);
end component;

signal tmp,tmp1,tmp2,tmp3,tmp4:std_logic;
begin
h0:xor1 port map(x,y,tmp);
h1:xor1 port map(tmp,z,s);
h2:and1 port map(x,y,tmp1);
h3:and1 port map(x,z,tmp2);
h4:and1 port map(y,z,tmp3);
h5:or1 port map(tmp1,tmp2,tmp4);
h6:or1 port map(tmp3,tmp4,c);
end struct;








Full adder data flow

library ieee;
use ieee.std_logic_1164.all;
entity fa is
port(x,y,z:in std_logic;s,c:out std_logic);
end fa;

architecture dataflow of fa is
begin
s<=(x xor y) xor z;
c<=(x and y) or (x and z) or ( y and z);
end dataflow;


full adder behavioural


library ieee;
use ieee.std_logic_1164.all;

entity fa2 is
port(x,y,z:in std_logic; s,c:out std_logic);
end fa2;

architecture behav of fa2 is
begin
process(x,y)
begin
s<=(x xor y) xor z;
c<=(x and y) or (x and z) or (y and z);
end process;
end behav;











D Flip-Flop


library ieee ;
use ieee.std_logic_1164.all;
---------------------------------------------
entity dff1 is
port( data_in: in std_logic;
clock: in std_logic;
data_out: out std_logic
);
end dff1;
----------------------------------------------
architecture behv of dff1 is
begin
process(data_in, clock)
begin
-- clock rising edge
if (rising_edge(clock)) then
data_out <= data_in;
end if;
end process;
end behv;
























3-bit Shift-Register/Shifter

library ieee ;
use ieee.std_logic_1164.all;
---------------------------------------------------
entity shift_reg is
port( I: in std_logic;
clock: in std_logic;
shift: in std_logic;
Q: out std_logic_vector(2 downto 0)
);
end shift_reg;
---------------------------------------------------
architecture behv of shift_reg is
-- initialize the declared signal
signal S: std_logic_vector(2 downto 0):="111";
begin
process(I, clock, shift, S)
begin
-- everything happens upon the clock changing
if (clock'event and clock='1') then
if (shift = '1') then
S <= I & S(2 downto 1);
end if;
end if;
end process;
-- concurrent assignment
Q <= S;
end behv;

















n-bit counter

library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
----------------------------------------------------
entity counter is
generic(n: natural :=2);
port( clock: in std_logic;
clear: in std_logic;
count: in std_logic;
Q: out std_logic_vector(n-1 downto 0)
);
end counter;
----------------------------------------------------
architecture behv of counter is
signal Pre_Q: std_logic_vector(n-1 downto 0);
begin
-- behavior describe the counter
process(clock, count, clear)
begin
if (clear = '1') then
Pre_Q <= Pre_Q - Pre_Q;
elsif (clock='1' and clock'event) then
if (count = '1') then
Pre_Q <= Pre_Q + 1;
end if;
end if;
end process;
-- concurrent assignment statement
Q <= Pre_Q;
end behv;