11/2/2014 David A.C.

http://www.eng.uwaterloo.ca/~dacananz/PMOS%20Switch.html 1/1
PMOS Switch
A common problem in discrete circuit design is create some kind of switch to turn the voltage supply rail "ON"
(conducting, SC) to "OFF" (non-conducting, OC). We know that a transistor is a switch. You here that
everywhere; any mundane reference to a transistor is followed by, "an electronic switch", in order inform any
marketing folks (or even softies) who didn't get the memo.
But there's more to FET than a switch. It has three modes of operation!
Inversion (aka cut-off, aka subthreshold) -- FET does not conduct
Triode (aka linear, aka Ohmic) -- FET acts like a resistor (or a triode, but if you know what that is, I'd be
looking at your website)
Saturation -- Fet acts like a voltage controlled current source
So that's a FET, what is a switch? It is either an open-circuit or short-circuit, if its "ON" or "OFF" respectivelly. But
when it's "ON" there will be some resistance, due to the contact and the conductor properties themsevles, unless
it's a super-conductor switch (but they are out of stock at digikey.com). This means that the triode region makes
a lot of sense. If we can switch a FET from tiode to inversion and vice-versa, you got a swtich!
OK! But most people think wait, for a FET you enter saturation when the gate voltage is much higher than the
drain to source voltage. I'm trying to turn-off 24 volts, and my control circuitry can only output 5 V or 3.3 V tops!
True, an NMOS enters triode under that condition, for a PMOS the reverse is true!
With this simple circuit, you can see than when V.in is low the collector of Q.1 will float, causing it to rise to
V.supply due to the pull-up (which is large to limit current). The gate of M1 willbe high, and the circuit will be non-
conducting. Well, there will be some leakage current. If V.in rises, Q.1 will conduct. If Q.1 is driven into the
saturation region the collector voltage will drop to V.ce. This maeans that the gate voltage of Q.2 will also fall,
and the FET will turn into resistor will low imepdance. Plus, Q.1 is not needed if you already plan to drive Q.2 will
an open-collector device, like a comparator!
If we had used an NMOS circuit, driving the gate high will cause the FET to enter saturation. This means that the
voltage seen at the output would could not exceed the gate voltage. Plus, the device would be a current source.
True, the current is voltage controlled and can be switched "ON" and "OFF", but for a switch you want to the load
to determine the current draw.
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