PRACTICAL: 3

TITLE: 3-BIT SYNCHRONOUS BINARY COUNTER

Learning Outcomes:
At the end of this practical, student are able to:
i. Design schematic circuit for Synchronous JK -counter .
ii. Simulate digital output for Synchronous JK -counter .

Laboratory Equipment:
i.
ii.

Computer
Software Altera Max+Plus II Baseline 10.2 software

Theory:
Counter can be developed by cascading the flip-flop. It has been categorized into two,
asynchronous and synchronous counter. We can define the asynchronous counter as a counter
where the flip-flop is triggered from external clock and the subsequent flip-flop clock is triggered
by the output Q from previous flip-flop. This counter is also known as a ripple counter. Figure 1
below is an example of logic schematic for asynchronous counter.

Figure 1: 2-bit asynchronous forward counter

Table 1 below summarized the flip-flop schematic connection for forward or backward counter.
Table 1
Connection
between
Q

CLK

CLK

Count down
Count up

Count up
Count down

In asynchronous counter, the more the flip-flop been used in the circuit, it will add more
propagation delay to the output. A synchronous circuit can be use to solve this problem where all
the flip-flop in the schematic receives the clock pulses at the same time. Besides counting
forward and backward, this counter can be designed to count randomly.

Figure 2: 2-bit synchronous forward counter

PROCEDURE :
PART 1
A.

Designing Using The Graphic Editor

1. Start MAXPLUS software. Choose File, New in the new window select Graphic Editor
(*.gdf file)
2. From the File menu, click Save as, and save the file in a new folder (eg., ..
file.gdf) and click OK. If the new folder was not created, just type the complete
path in the File Name box.
3. In the File menu, select Project, then Set Project to Current File.
4. Then select Assign, Device. In the Device Family, select the MAX7000S device
family. Uncheck Show Only Fastest Speed Grades. Under Devices, select
EPM7128SLC84-7 and click OK.
5. If a dialog box open up and recommends to turning on the Maintain Current
Synthesi.. click No.

B.

Creating The Schematic Diagram

Figure 1: A 3-bit synchrounous binary counter schematic

1. Right click in the centre of the worksheet, and then choose Enter Symbol. In the
Symbol Libraries box, double click on the..library.
2. Scroll down in the Symbol Files box and double click on jkff, and2. The symbol
should appear in the centre of the Graphic Editor.
3. Assign also output and Input pin and connecting the symbol by referring Figure 1
C.

Assign PIN Numbers

1. Right click on the CLK symbol and select AssignPin/Location/Chip.
2. In Chip Resource, select Anywhere on this Chip.
3. Click OK in the Pin/Location/Chip box and repeat the previous step for all
Output pin (Q0, Q1, Q2)
4. Do not forget to save your file.

D.

Compiling Project
1. Select File Project Save and Compile.

Figure 2: Compiling

2. A similar window should appear.

3. The project should compile with 0 errors. If any errors appear verify if you have
performed the entire steps correctly.

Figure 3: Compiler result

A.

Simulating project
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.

Select File NewWaveform Editor File and click OK.

From the toolbar, select NodeEnter Nodes from SNF (Simulator Netlist File).
Click on List.
Select (highlight) CLK, Q0, Q1, and Q2 in Available Nodes & Groups.
Click on => to have CLK, Q0, Q1, and Q2 in the Selected Node & Groups.
Click OK.
You can drag the Node to have an appropriate order.
By referring Figure 4, route CLK input.
Go to File menu and select Save.
Save option would automatically select filename to be the same as the project name,
Click OK.
Go to MAX+PLUS II menu and select Simulator.
Click Start when the simulator dialog box appears.
Once simulation is done, the finish dialog box would appear. Click OK.
Click Open SCF to see the simulation result.
Record your Q0, Q1, and Q2 results.

Figure 4: Timing Diagram

16. Then, fill up the Table 1 below based on result Q0, Q1 and Q2 :

Table 1: The state sequence for a 3 bit binary counter

CLOCK PULSE

Q2

Q1

Q0

INITIALLY
1
2
3
4
5
6
7
8 (RECYCLES)

QUESTION

1. Explain the operation of 3-bit binary counter. [2 marks]

2. Explain 3 applications of counter. [3 marks]

DISCUSSION & CONCLUSION :

Your discussion should be related to your practical and theoretical understanding on the related
topic. (not less than one page of explanation)

END OF PRACTICAL 3

Jabatan Kejuruteraan Elektrik

(JKE)

PRACTICAL ANSWER
SHEET

COURSE

EC303 COMPUTER ARCHITECTURE AND ORGANIZATION

PRACTICAL NO.

PRACTICAL TITLE

_________________________________________________________

LECTURER NAME : _________________________________________________CLASS : ____________

NO

REG. NO.

STUDENT NAME

1
2
3

Pre Lab & Project Setup

Creating Schematic Design
SKILL ACQUIRED (60%)
Simulating Project
Measuring & Recording Data
Result
REPORT (25%) Question
Discussion & Conclusion
Attendance
TEAMWORK (15%) Submitted on Time
Cleanliness of Workspace
Submission Date

TOTAL

PRACTICAL 3

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/20%
/15%
/ 5%
/ 5%
/ 5%
/ 5%
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/100%

1.0

Pre Lab & Design

Show all your theory finding and schematic design here.

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PRACTICAL 3
2.0

Result
Show the waveform, truth table and all the finding from practical.
2.1 Waveform

2.2 Truth Table

CLOCK PULSE

Q2

Q1

Q0

INITIALLY
1
2
3
4
5
6
7
8 (RECYCLES)

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PRACTICAL 3

3.0

Question
Answer all the question below
1. Explain the operation of 3-bit binary counter. [2 marks]
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2. Explain 3 applications of counter. [3 marks]

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PRACTICAL 3
4.0

Discussion
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5.0

Conclusion
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