M. Jagadesh Kumar and Ali. A.

Orouji , "Investigation of a New Modified Source/Drain for

Diminished Self-heating Effects in Nanoscale MOSFETs using Computer Simulation,"
Physica E: Low-dimensional Systems and Nanostructures, Vol. 33, Issue.1, pp.134-
MS# tkc05181 138, June 2006.

Investigation of a New Modified Source/Drain for

Diminished Self-heating Effects in Nanoscale MOSFETs
using Computer Simulation

M. Jagadesh Kumar1 and Ali A. Orouji2

1
Department of Electrical Engineering, Indian Institute of Technology, New Delhi, India
2
Department of Electrical Engineering, Semnan University, Semnan, Iran

Abstract- In this paper, we demonstrate that by introducing a buried oxide in a bulk

MOSFET only under the source and drain regions i.e. using an oxygen implanted

Source/Drain (OISD) structure, the drain capacitance of a nanoscale MOSFET can be made

close to that of an SOI MOSFET while the self heating effects are highly diminished and are

similar to that of a bulk MOSFET. Two-dimensional simulation is used to optimize the

length and thickness of the OISD regions.

Index Terms- Self-heating, silicon-on-insulator (SOI), MOSFET, capacitance, temperature

distribution, two-dimensional (2-D) simulation.

1. INTRODUCTION

Silicon-On-Insulator (SOI) MOSFETs have many advantages for high-performance and low-

voltage applications in the sub-half-micron regime since they offer a steeper subthreshold

swing, reduced parasitic capacitance and elimination of latch up [1]. However, self-heating is

a major problem in SOI-MOSFETs as compared to the bulk MOSFETs due to the decreased

heat flow across the buried oxide. The temperature rise causes a decrease in the drain current

and leads to more serious reliability problems such as increased electromigraton and
enhanced impact ionization. In the past, several attempts have been made to reduce the

temperature rise stemming from this self-heating [2], [3].

In this paper, we examine an alternative measure to reduce the self-heating effects by

introducing a buried oxide in a bulk MOSFET only under the source and drain regions which

can be easily created with implantation of oxygen molecules under source/drain regions.

Using two-dimensional simulation [4], we demonstrate that introducing optimized oxygen

implanted source and drain (OISD) regions in a bulk MOSFET, we can achieve low junction

capacitances comparable to that of an SOI MOSFET while the self heating effects are

significantly reduced.

II. SIMULATION METHOD AND DEVICE PARAMETERS

There is a lattice temperature advanced application module (LT-AAM) in MEDICI

simulator [4]. Therefore, it is possible to couple the electrical and thermal characteristics of

devices for their accurate modeling. In this case, a new state variable “the temperature of the

lattice” is introduced into MEDICI in order to describe the self-heating of devices. Poisson’s

equation, the current continuity equation, and the heat equation are solved in a completely

coupled manner to obtain the temperature of the lattice.

A schematic cross-sectional view of the OISD-MOSFET implemented using the 2-D

device simulator MEDICI is shown in Fig.1 where tOISD and LOISD are the thickness of OISD

region and the distance between the two OISD regions, respectively. The simulation

parameters of the structure are given in Table I. We have compared this OISD structure with

that SOI and Bulk MOSFETs with equivalent parameters.

III. RESULTS AND DISCUSSIONS

 Fig. 2 shows a typical MEDICI simulated 3-D temperature distribution in the OISD,

SOI and bulk MOSFETs for VGS = 1 V and VDS = 1.5 V. The temperature in the substrate is

fixed at 300 K. As can be seen from Fig. 2(a), the maximum temperature in the OISD

structure (≈ 320 K) is very close to that of the peak temperature in the bulk MOSFET (≈ 310

K) as shown in Fig. 2(b) and is significantly smaller than the peak temperature (≈ 510 K)

shown in Fig. 2(c) for the SOI MOSFET. The reduced self-heating effect is also clearly

reflected in the output characteristics shown in Fig. 3 in which the drain current of the OISD

structure is close to that of the bulk MOSFET.

For optimizing the length and thickness of the OISD regions, we have carried out a

comparison in terms of zero-bias drain capacitance and maximum device temperature as

shown in Fig. 4. It can be observed clearly that when the distance between OISD regions

(LOISD) decreases, the maximum temperature of the device will increase. However, the zero-

bias drain capacitance of the device is very weakly dependent on the distance between the

OISD regions up to 90 nm and exhibits only about 5 percent variation. Therefore, in the

OISD MOSFETs, by keeping the distance between the OISD regions (LOISD) almost equal to

that of the channel length, the temperature of the device can be kept close to that of the bulk

MOSFET while the drain capacitance is close to that of the SOI MOSFET. However, if the

distance between the OISD regions (LOISD) is below the channel length (100 nm), the zero-

bias drain capacitance abruptly increases. This can be understood from Fig. 5. Our simulation

shows that when LOISD is less than the channel length, the zero bias depletion region is as

shown schematically in Fig. 5(a). However, if LOISD exceeds the channel length, the zero-bias

depletion region forms over an extended length as shown schematically in Fig. 5(b)

increasing the zero-bias drain capacitance. Fig. 6 shows the dependence of the maximum

temperature and zero drain-bias capacitance on the thickness (tOISD) of the OISD regions. The
distance between OISD regions is set equal to the channel length at 100 nm. We can observe

that the maximum device temperature is weakly dependent on the thickness of the OISD

regions because heat removal takes place through the gap between the OISD regions. The

drain capacitance is also weakly dependent on the thickness of the OISD regions if the

thickness is more than 50 nm. However, if the thickness of the OISD regions (tOISD) is

smaller than 50 nm, the zero-bias drain capacitance increases abruptly. This can be

understood from Fig. 7 in which, based on our simulation results, the formation of the

depletion for two different tOISD cases are schematically shown. If the thickness of the OISD-

regions (tOSID) is less than the zero-bias source/drain depletion region thickness (Fig. 7(a)),

the length over which the depletion region forms is more than the case when the thickness of

the OISD-regions (tOSID) is greater than the zero-bias source/drain depletion region thickness

(Fig. 7(b)). This clearly shows the reason why the drain capacitance increases when tOISD is

smaller than 50 nm.

The importance of the standby current or leakage current as a factor to be included in

the performance figure of merit for deep submicron CMOS has recently been proposed and

analyzed for bulk CMOS technology [5], [6]. Therefore, the transfer characteristic of OISD

structure is shown in Fig. 8. It can be seen from the figure that the leakage current of OISD

device reduces when compared to the bulk MOSFET due to the junction area reduction.

Also, the subthreshold slope of the device improves. Fig. 9 shows the threshold voltage of

OISD, SOI, and bulk MOSFET structures versus the channel length up to 50 nm. It is clear

that the variation of threshold voltage for the OISD structure is similar or slightly better when

compared to the bulk MOSFET.

 IV. CONCLUSIONS

In this paper, using two dimensional simulation, we have demonstrated that by

introducing an oxide region just under the source and drain of a MOSFET, one can realize

self heating effects close to that of a bulk MOSFET while the drain capacitance is similar to

that an SOI MOSFET. We have also shown that even if there are variations in the distance

between the OISD regions or their thickness, it will not critically affect the projected

benefits. In conclusion, we can design the OISD structure for best performance by choosing

the distance between the OISD regions about the channel length, and the thickness of OISD

regions greater than the difference between width of depletion region under the gate and the

thickness of n+ source/drain regions.

 REFERENCES

1. A. Chaudhry and M. J. Kumar, "Controlling Short-channel Effects in Deep

Submicron SOI MOSFETs for Improved Reliability: A Review", IEEE Trans.
on Device and Materials Reliability, Vol.4, pp.99-109, March 2004.
2. M. Zhu, P. Chen, R. K. Y. Fu, Z. An, C. Lin, and P. K. Chu, “Numerical
Study of Self-Heating Effects of MOSFETs Fabricated on SOAN Substrate,”
IEEE Trans. on Electron Devices, vol. 51, pp. 901-906, June 2004.
3. B. Cole and S. Parke, “A Method to Overcome Self-Heating Effects in SOI
MOSFETs,” IEEE University/Government/Industry Microelectronics
Symposium, Proceeding of the 15th Biennial, pp. 295-297, 2003.
4. MEDICI 4.0, Technology Modeling Associates, Palo Alto, CA, 1997.
5. R. A. Chapman, T. C. Holloway, V. M. McNeil, A. Chatterjee, and G. E.
Stacey, “A standby current limited performance figure of merit for deep
submicron CMOS,” IEEE Trans. Electron Devices, vol. 4, pp. 1888-1895,
Nov. 1997.
6. K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand, “Leakage current
mechanisms and leakage reduction techniques in deep-submicrometer CMOS
circuits,” Proc. IEEE, vol. 91, pp. 305-327, Feb. 2003.
Table I Parameters for OISD structure used in MEDICI simulation

Parameter Value
+
n source/drain 1019 cm-3
p-type silicon film doping 1016 cm-3
Thickness of the n+ source/drain layer (tn+) 50 nm
Thickness of the OISD region (tOISD) 300 nm
Distance of the OISD regions (LOISD) 100 nm
Channel length 100 nm
Gate oxide thickness 5 nm
Gate work function 4.8 eV

Figure Captions

Figure 1 Cross-sectional view of an N-channel OISD-MOSFET.

Figure 2 3-D temperature distribution of (a) OISD, (b) bulk and (c) SOI MOSFETs.
Figure 3 Output characteristics of OISD, SOI and bulk MOSFETs.
Figure 4 Maximum temperature and zero drain capacitance versus distance between
OISD-regions.
Figure 5 Depletion region formation when the distance between OISD-regions (LOSID) is
(a) less than the channel length and (b) greater than the channel length.
Figure 6 Maximum temperature and zero drain capacitance versus thickness of OISD
regions.
Figure 7 Depletion region formation when the thickness of the OISD-regions (tOSID) is
(a) less than the zero-bias source/drain depletion region thickness and (b)
greater than the zero-bias source/drain depletion region thickness.
Figure 8 Transfer characteristics of OISD, SOI, and bulk MOSFETs.
Figure 9 Threshold voltage of OISD structure versus channel length up to 50 nm.
 Source Gate Drain

tn+ n+ n+

tOISD LOISD

y P substrate

SiO2 Metal Silicon

Fig. 1.
 Drain

Gate
Source

tOISD LOISD

Fig. 2. (a)
 Drain

Gate
Source

Fig. 2. (b)
 Drain

Gate
Source

Burried L
Oxide

Fig. 2. (c)
 0.6

VGS = 1 V
0.5 tOISD = 300 nm
LOISD = 100 nm
0.4
Drain Current (mA)

0.3

0.2

OISD-MOSFET
0.1 SOI-MOSFET
BULK-MOSFET
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
Drain Voltage (Volts)

Fig. 3
 0 20 40 60 80 100
5.00E-016 550

tOISD = 300 nm

4.50E-016 500

Maximum Temperature (Kelvin)

Drain Capacitance (F/μm)

4.00E-016 450

3.50E-016 400

3.00E-016 350

2.50E-016 300
0 20 40 60 80 100 120 140
Distance between OISD regions (nm)

Fig. 4
 Source Gate Drain

tn+ n+ n+

tOISD LOISD (a)

y P substrate

Source Gate Drain

tn+ n+ n+

tOISD LOISD (b)

y P substrate

SiO2 Metal Silicon

Fig. 5
 0 50 100 150 200 250 300
5.00E-016 550

LOISD = 100 nm

4.50E-016 500
Drain Capacitance (F/μm)

Maximum Temperature (Kelvin)

4.00E-016 450

3.50E-016 400

3.00E-016 350

2.50E-016 300
0 50 100 150 200 250 300
Thickness of OISD regions (nm)

Fig. 6
 Source Gate Drain

tn+ n+ n+
LOISD

tOISD (a)

y P substrate

Source Gate Drain

tn+ n+ n+

tOISD LOISD (b)

y P substrate

SiO2 Metal Silicon

Fig. 7
 1E-4
VDS = 50 mV
tOISD = 300 nm
1E-5 LOISD = 100 nm
Drain Current (Amp)

1E-6

1E-7

1E-8

OISD-MOSFET
1E-9
SOI-MOSFET
BULK-MOSFET
1E-10
-0.5 0.0 0.5 1.0 1.5
Gate Voltage (Volts)

Fig. 8
 0.6

0.5
Threshold Voltage (Volts)

0.4

0.3

0.2

VDS = 50 mV
OISD-MOSFET
0.1 tOISD = 300 nm
SOI-MOSFET
LOISD = 100 nm BULK-MOSFET
0.0
50 100 150 200 250 300
Channel Length (nm)

Fig. 9