T-Flip Flop

RTL:

TTL:

Waveform:

=========================================================================
*

Final Report

=========================================================================
Final Results
RTL Top Level Output File Name
Top Level Output File Name
Output Format

: t_ff

: NGC

Optimization Goal

: Speed

Keep Hierarchy

: NO

Design Statistics
# IOs

:5

Cell Usage :
# BELS

:2

:2

INV

# FlipFlops/Latches

:2

FDRE

:1

FDSE

:1

# Clock Buffers

: t_ff.ngr

:1

BUFGP

:1

# IO Buffers

:4

IBUF

OBUF

:2
:2

=========================================================================

Device utilization summary:

---------------------------

Selected Device : 3s400tq144-4

Number of Slices:

1 out of 3584

0%

Number of Slice Flip Flops:

2 out of 7168

0%

Number of 4 input LUTs:

2 out of 7168

0%

Number of IOs:
Number of bonded IOBs:
Number of GCLKs:

5
5 out of
1 out of

97

5%

8 12%

--------------------------Partition Resource Summary:

---------------------------

No Partitions were found in this design.

---------------------------

=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.

FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
----------------------------------------------------+------------------------+-------+
Clock Signal

| Clock buffer(FF name) | Load |

-----------------------------------+------------------------+-------+
clk

| BUFGP

|2

-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:

---------------------------------------No asynchronous control signals found in this design

Timing Summary:
--------------Speed Grade: -4

Minimum period: 3.152ns (Maximum Frequency: 317.259MHz)

Minimum input arrival time before clock: 2.724ns
Maximum output required time after clock: 7.241ns
Maximum combinational path delay: No path found

Timing Detail:
-------------All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 3.152ns (frequency: 317.259MHz)
Total number of paths / destination ports: 2 / 2
------------------------------------------------------------------------Delay:
Source:

3.152ns (Levels of Logic = 1)

q (FF)

Destination:

q (FF)

Source Clock:

clk rising

Destination Clock: clk rising

Data Path: q to q
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDRE:C->Q
INV:I->O
FDRE:D

2 0.720 0.877 q (q_OBUF)

1 0.551 0.801 q_not00011_INV_0 (q_not0001)
0.203

---------------------------------------Total

3.152ns (1.474ns logic, 1.678ns route)

(46.8% logic, 53.2% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 4 / 4
------------------------------------------------------------------------Offset:
Source:

2.724ns (Levels of Logic = 1)

rst (PAD)

Destination:

q (FF)

Destination Clock: clk rising

Data Path: rst to q

Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------IBUF:I->O

2 0.821 0.877 rst_IBUF (rst_IBUF)

FDRE:R

1.026

---------------------------------------Total

2.724ns (1.847ns logic, 0.877ns route)

(67.8% logic, 32.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 2 / 2
------------------------------------------------------------------------Offset:
Source:

7.241ns (Levels of Logic = 1)

q (FF)

Destination:

q (PAD)

Source Clock:

clk rising

Data Path: q to q
Gate
Cell:in->out

Net

fanout Delay Delay Logical Name (Net Name)

---------------------------------------- -----------FDRE:C->Q
OBUF:I->O

2 0.720 0.877 q (q_OBUF)

5.644

----------------------------------------

q_OBUF (q)

Total

7.241ns (6.364ns logic, 0.877ns route)

(87.9% logic, 12.1% route)

=========================================================================

Total REAL time to Xst completion: 13.00 secs

Total CPU time to Xst completion: 13.60 secs

-->

Total memory usage is 131564 kilobytes

Number of errors : 0 ( 0 filtered)

Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

ower summary

| I(mA) | P(mW) |

---------------------------------------------------------------Total estimated power consumption |

Number of error messages: 0
Number of warning messages: 3
Number of info messages: 1

15 |

19 |

Total Vccaux 2.50V |

15 |

38 |

Total Vcco25 2.50V |

0 |

0 |

--Clocks |

0 |

0 |

Inputs |

0 |

0 |

Logic |

0 |

0 |

Outputs |
Vcco25 |
Signals |

0 |

0 |

0 |

0 |

Quiescent Vccint 1.20V |

15 |

---

Quiescent Vccaux 2.50V |

15 |

19 |
38 |