MANCHEstER

1824
The Thumb instruction set
The University
of Manchester

❏ Outline:

❍ the Thumb programmers’ model

❍ Thumb instructions
❍ Thumb implementation
❍ Thumb applications

☞ hands-on: writing Thumb assembly programs

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 1

 MANCHEstER
1824
The Thumb instruction set
The University
of Manchester

❏ Outline:

➜ the Thumb programmers’ model

❍ Thumb instructions
❍ Thumb implementation
❍ Thumb applications

☞ hands-on: writing Thumb assembly programs

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 2

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What is Thumb?
The University
of Manchester

❏ Thumb is:

❍ a compressed, 16-bit representation of a subset of the ARM

instruction set
– primarily to increase code density
– also increases performance in some cases

❏ It is not a complete architecture

❍ all ‘Thumb-aware’ cores also support the ARM instruction set

– therefore the Thumb architecture need only support common
functions

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 3

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The Thumb bit
The University
of Manchester

31 30 29 28 27 7 6 5 4 0
NZCV unused I F T mode

❏ The ‘T’ bit in the CPSR controls the interpretation of

the instruction stream
❍ switch from ARM to Thumb (and back) by executing BX
instruction
❍ exceptions also cause switch to ARM code
– return symmetrically to ARM or Thumb code
❍ Note: do not change the T bit with MSR!

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 4

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The Thumb programmers’ model
The University
of Manchester

r0 shaded registers have

r1 restricted access
r2
r3 Lo registers
r4
r5
r6
r7
r8
r9
r10
r11
Hi registers
r12
SP (r13)
LR (r14)
PC (r15)
CPSR

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 5

 MANCHEstER
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The Thumb programmers’ model
The University
of Manchester

❏ Thumb register use:

❍ r0 - r7 are general purpose registers

❍ r13 is used implicitly as a stack pointer
– in ARM code this is a software convention
❍ r14 is used as the link register
– implicitly, as in the ARM instruction set
❍ a few instructions can access r8 - r15
❍ the CPSR flags are set by data processing instructions &
control conditional branches

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 6

 MANCHEstER
1824
The Thumb programmers’ model
The University
of Manchester

❏ Thumb-ARM similarities:

❍ load-store architecture
– with data processing, data transfer and control flow instructions
❍ support for 8-bit byte, 16-bit half-word and 32-bit data types
– half-words are aligned on 2-byte boundaries
– words are aligned on 4-byte boundaries
❍ 32-bit unsegmented memory

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 7

 MANCHEstER
1824
The Thumb programmers’ model
The University
of Manchester

❏ Thumb-ARM differences:

❍ most Thumb instructions are unconditional

– all ARM instructions are conditional
❍ most Thumb instructions use a 2-address format
– most ARM instructions use a 3-address format
❍ Thumb instruction formats are less regular
– a result of the denser encoding
❍ Thumb has explicit shift opcodes
– ARM implements shifts as operand modifiers

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 8

 MANCHEstER
1824
The Thumb instruction set
The University
of Manchester

❏ Outline:

❍ the Thumb programmers’ model

➜ Thumb instructions
❍ Thumb implementation
❍ Thumb applications

☞ hands-on: writing Thumb assembly programs

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 9

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Thumb branch instructions
The University
of Manchester

15 12 11 8 7 0
1 1 0 1 cond 8-bit offset (1) B<cond> <label>

15 12 11 0
11100 11-bit offset (2) B <label>

15 12 11 10 0
1 1 1 1H 11-bit offset (3) BL <label>

15 12 11 7 6 5 3 2 0
0 1 0 0 0 1 1 1 0H 000 (4) BX Rm

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 10

 MANCHEstER
1824
Thumb branch instructions
The University
of Manchester

❏ These are similar to ARM instructions except:

❍ offsets are scaled to half-word, not word

❍ range is reduced to fit into 16 bits
❍ BL works in two stages:
H=0: LR := PC + signextend(offset << 12)
H=1: PC := LR + (offset << 1)
LR := oldPC + 3
❍ the assembler generates both halves
❍ LR bit[0] is set to facilitate return via BX

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 11

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Thumb branch instructions
The University
of Manchester

❏ Branch and eXchange (BX)

❍ to return to ARM or Thumb caller:

BX lr ; replaces MOV pc, lr

❏ Subroutine calls

❍ later ARMs support BLX instruction

❍ to synthesize BLX or earlier ARM:
ADR r0, subr + 1 ; “+ 1” to enter Thumb mode
ADR lr, return ; save return address
BX r0 ; calls subr
return ... ;

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 12

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Thumb software interrupts
The University
of Manchester

15 8 7 0
1 1 0 1 1 1 1 1 8-bit immediate

❏ The Thumb SWI operates exactly like the ARM SWI

❍ the (interpreted) immediate is just 8 bits

– Thumb Angel SWI uses value 0xAB
r0 call value is exactly as in ARM code
❍ the SWI handler is entered in ARM code
– the return automatically selects ARM or Thumb

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 13

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Thumb data processing instructions
The University
of Manchester

15 10 9 8 6 5 3 2 0
0 0 0 1 1 0 A Rm Rn Rd (1) ADD|SUB Rd,Rn,Rm

15 10 9 8 6 5 3 2 0
0 0 0 1 1 1 A imm3 Rn Rd (2) ADD|SUB Rd,Rn,#imm3

15 12 11 10 8 7 0
0 0 1 op Rd/Rn imm8 (3) MOV|CMP|ADD|SUB Rd/Rn,#imm8

15 13 12 11 10 6 5 3 2 0
0 0 0 op #sh (4) LSL|LSR|ASR Rd,Rn,#shift

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 14

 MANCHEstER
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Thumb data processing instructions
The University
of Manchester

15 10 9 6 5 3 2 0
0 1 0 0 0 0 op Rm/Rs Rd/Rn (5) <Op> Rd/Rn,Rm/Rs

15 10 9 8 7 6 5 3 2 0
0 1 0 0 0 1 op D M Rm Rd/Rn (6) ADD|CMP|MOV Rd/Rn,Rm

15 12 11 10 8 7 0
1 0 1 0 R Rd imm8 (7) ADD Rd,SP|PC,#imm8

15 8 7 6 0
10110000A imm7 (8) ADD|SUB SP,SP,#imm7

❍ In case (6):
– MOV does not affect the flags
(it can be distinguished using the mnemonic CPY after v6)
© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 15
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Thumb data processing instructions
The University
of Manchester

❏ Notes:

❍ in Thumb code shift operations are separate from general

ALU functions
– in ARM code a shift can be combined with an
❍ ALU function in a single instruction
❍ all data processing operations on the ‘Lo’ registers set the
condition codes
– those on the ‘Hi’ registers do not, apart from CMP which only
changes the condition codes

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 16

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Thumb single register data transfers
The University
of Manchester

15 13 12 11 10 6 5 3 2 0
011BL off5 Rn Rd (1) LDR|STR{B} Rd,[Rn,#off5]

15 13 12 11 10 6 5 3 2 0
1000L off5 Rn Rd (2) LDRH|STRH Rd,[Rn,#off5]

15 12 11 9 8 6 5 3 2 0
0 1 0 1 op Rm Rn Rd (3) LDR|STR{S}{H|B} Rd,[Rn,Rm]

15 11 10 8 7 0
0 1 0 0 1 Rd off8 (4) LDR Rd,[PC,#off8]

15 12 11 10 8 7 0
1 0 0 1 L Rd off8 (5) LDR|STR Rd,[SP,#off8]

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 17

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Thumb multiple register
The University
of Manchester

data transfers
15 12 11 10 8 7 0
1 1 0 0 L Rn reg. list (1) LDMIA|STMIA Rn!,

15 10 9 8 7 0
1 0 1 1 1 1 LR reg. list (2) POP|PUSH {<reg list>{,R}}

❍ These map directly onto the ARM forms:

PUSH: STMFD SP!, {<regs>{, lr}}
POP: LDMFD SP!, {<regs>{, pc}}
– note restrictions on available addressing modes compared with
ARM code

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 18

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Unique Thumb mnemonics
The University
of Manchester

❏ Most significant differences from ARM:

PUSH ; STMFD sp!,{&}

POP ; LDMFD sp!,{&}
NEG ; RSB Rd, Rs, #0
LSR ; MOV Rd, Rd, LSR <Rs | #5>
ASR ; MOV Rd, Rd, ASR <Rs | #5>
LSL ; MOV Rd, Rd, LSL <Rs | #5>
ROR ; MOV Rd, Rd, ROR Rs

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 19

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Newer Thumb instructions (from v5)
The University
of Manchester

❏ BLX works in two stages; (first is same as BL)

15 12 11 10 1 0
11101 10-bit offset 0 (1) BLX <label>

H=0: LR := PC + signextend(offset << 12)

H=1: PC := (LR + (offset << 2)) AND FFFFFFFC
LR := oldPC + 3
T flag := 0

❍ There is also a register-based BLX

15 7 6 3 2 0
0 1 0 0 0 1 1 1 1 Rm 0 0 0 (2) BLX Rm

❏ BKPT (Breakpoint)
© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 20
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Newer Thumb instructions (from v6)
The University
of Manchester

❍ CPY
– Mnemonic allowing register moves without affecting flags
❍ SXTB/SXTH/UXTB/UXTH
– Sign extension (no shifts)
❍ REV/REV16/REVSH
– Byte swaps
❍ SETEND
❍ CPSIE/CPSID
– Interrupt enable/disables (no mode changes)

More about these in later ARM session.

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 21

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ARM/Thumb interworking
The University
of Manchester

❏ BX (Branch eXchange) moves to the mode specified by

the address LSB (in register)
❏ BLX (Branch with Link and eXchange) moves to the
other mode (common case)
❍ the LSB of LR retains the ‘parent’ mode
❍ BLX Rm can move to either mode (like BX)

❏ The ‘correct’ subroutine return is:

BX LR
❍ the routine can then be called from both ARM and Thumb
code
© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 22
 MANCHEstER
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ARM/Thumb interworking
The University
of Manchester

❏ Calling procedures in other instruction set

❍ ARM v5 or later
BLX procedure ; ARM or Thumb
❍ ARM v4T
– from ARM
ADR lr, return_addr ;
ADR r0, procedure + 1 ; + 1 sets ‘T’
BX r0 ;
return_addr ...
– from Thumb
LDR r0, =procedure ;
MOV lr, pc ; ‘here’ + 4
BX r0 ;
...
© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 23
 MANCHEstER
1824
The Thumb instruction set
The University
of Manchester

❏ Outline:

❍ the Thumb programmers’ model

❍ Thumb instructions
➜ Thumb implementation
❍ Thumb applications

☞ hands-on: writing Thumb assembly programs

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 24

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Thumb decoding
The University
of Manchester

❏ The original Thumb implementation translated the

opcodes into ARM opcodes.
❍ This means the effect of Thumb and ARM instructions are the
same
– Thumb is more restricted (e.g. smaller offsets/immediates)
– One or two new functions (e.g. BL details)

❏ Later implementations decode Thumb directly

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 25

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Thumb - ARM
The University
of Manchester

instruction mapping
15 12 11 10 8 7 0
0 0 1 op Rd/Rn imm8 ADD Rd, #imm8
‘always’
condition

ma jor opcode,
minor opcode destination
format 3: MOV/ zero immediate
denoting ADD and source
CMP/ADD/SUB shift value
& set CC register
with immediate

31 28 27 26 25 24 21 20 19 16 15 12 11 8 7 0
1 1 1 0 0 0 1 0 1 0 0 1 0 Rd 0 Rd 0 0 0 0 imm8

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 26

 MANCHEstER
1824
The Thumb instruction set
The University
of Manchester

❏ Outline:

❍ the Thumb programmer’s model

❍ Thumb instructions
❍ Thumb implementation
➜ Thumb applications

☞ hands-on: writing Thumb assembly programs

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 27

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Thumb applications
The University
of Manchester

❏ Thumb code properties:

❍ 70% of the size of ARM code

– 30% less external memory power
– 40% more instructions
❍ With 32-bit memory:
– ARM code is 40% faster than Thumb code
❍ With 16-bit memory:
– Thumb code is 45% faster than ARM code

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 28

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Thumb applications
The University
of Manchester

❏ For the best performance:

❍ use 32-bit memory and ARM code

❏ For best cost and power-efficiency:

❍ use 16-bit memory and Thumb code

❏ In a typical embedded system:

❍ use ARM code in 32-bit on-chip memory for small speed-

critical routines
❍ use Thumb code in 16-bit off-chip memory for large non-
critical control routines

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 29

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Hands-on: writing Thumb
The University
of Manchester

assembly programs
❏ Explore further the ARM software development tools

❍ Write Thumb assembly programs

❍ Check that they work as expected

☞ Follow the ‘Hands-on’ instructions

© 2005 PEVEIT Unit – ARM System Design Thumb instruction set – v5 – 30