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4.0 Using IGBT Modules 4.1 Structure and Operation A brief comparison between the
of IGBT Module structures of the IGBT, MOSFET
Mitsubishi IGBT modules are and npn Bipolar Junction
designed to be rugged, low loss The IGBT, Insulated Gate Bipolar Transistor (BJT) is depicted in
and easy to use. Use of advanced Transistor, is a switching transistor Figure 4.1. The npn BJT is a three
processing technologies gives low that is controlled by voltage junction device that requires a
on-state saturation voltages while applied to the gate terminal. continuous current flowing into the
maintaining the high switching Device operation and structure are base region to supply enough
speed needed for 20kHz operation. similar to those of an Insulated charges to allow the junctions to
The information presented in this Gate Field Effect Transistor, more conduct current. Because the
section is intended to help users of commonly known as a MOSFET. MOSFET and the IGBT are
Mitsubishi IGBT modules apply the The principal difference between voltage controlled devices, they
devices effectively and reliably. the two device types is that the only require voltage on the gate to
IGBT uses conductivity modulation maintain conduction through the
to reduce on-state conduction device. The IGBT has one junction
losses. more than the MOSFET, and this
SiO2 SiO2
n+
n+ n+
p
p p
n– n– n–
n+
n+ n+ p+
C D C
E S E
G G
B
C D C
Low on-state drop conductivity modulation High on-state drop for majority carrier Medium on-state drop for conductivity
condition modulation
Current control device, large drive power
Voltage control drive, small drive power Voltage control drive, small drive power
Medium fast switching
Very fast switching Fast switching
Advantage Disadvantage
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
junction allows higher blocking collector bulk region (n+ buffer lifetime control techniques are used
voltage and conductivity layer and collector “n” region). The to reduce the gain of the “pnp” bi-
modulation, as described below, charges reduce the collector bulk polar element and minimize lateral
during conduction. This additional region resistance and thus RBE values, thus precluding latch-
junction in the IGBT does limit collector to emitter voltage drop is up. Therefore, the equivalent circuit
switching frequency however. reduced (relative to VDS(on) of model of a H-Series IGBT
MOSFET). is reduced to the schematic in Fig-
4.1.1 Silicon Structure ure 4.3B.
When a positive gate voltage is first
The IGBT silicon structure is as applied, a gate current flows until 4.1.3 Wafer Processing
shown in Figure 4.2. A positive volt- the gate capacitance is charged
age on the gate attracts and the gate voltage rises to the IGBT wafer processing is similar to
electrons from the “p” gate region “on” level. When the gate voltage is FET processing. The silicon
towards the silicon surface under removed, the charges injected into material is a dual epitaxial
the gate. These electrons invert the collector bulk region must be structure, and gate and emitter
the “p” directly under the gate to removed before high voltage can regions are diffused and/or ion
form an “n” region, thus creating a be blocked. implanted into the emitter side.
path for charge flow between the Selective doping, electronic
“n” collector region and the “n” The IGBT surface emitter pattern is irradiation, and other processing
emitter region. A zero or negative striped geometrically, in contrast to techniques are used during
voltage (depends on the device) the FET cell-based geometry. The emitter-side processing.
on the gate maintains the off-bias. IGBT uses the same small feature
size advantages of the MOSFET, Many of the same processing
4.1.2 Device Operation but the striped geometry offers techniques used to fabricate FET
more ruggedness and immunity devices are employed in IGBT
When the device is on, the from latch-up of the parasitic thyris- manufacture. The high di/dt and
collector is at a higher voltage than tor shown in Figure 4.3A. dv/dt capabilities of the FETs
the emitter, and therefore minority result from the control of minority
carriers are injected from the A circuit model of a typical IGBT is carriers near the gate “p” region
collector p+ region into the illustrated in Figure 4.3A. H-Series and collector “n” region interface.
IGBTs use optimized buffer layer, The same techniques plus addi-
Figure 4.2 IGBT Cross Section p± well doping and alignments, tional steps to control carrier life-
and Silicon Structure gate structure, and surface pattern time near the collector N+ buffer
designs. Minority carrier region help to generate immunity
E
from latch-up and to enhance the
LG
n–
n+
p+ G RBE G RBE
C C
E E
C
HOLES VCE(sat) = VBE + IMOS • RMOD + IMOS • rDS(ON)
e ELECTRONS
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Figure 4.4 Structure of Mitsubishi IGBT Module and Module Base Plate Construction
(A) EMITTER COLLECTOR (B)
COMMON (C2E1) (E2) (C1)
GATE AND IGBT, FWD CHIP
CASE EMITTER COPPER NEW
(EPOXY RESIN) (G1, E1, G2, E2) INSULATING
PLATE
BASE H-SERIES
INSULATION MATERIAL
IGBT MODULE
COPPER SEMICONDUCTOR CHIP
TERMINAL COLLECTOR PLATE
EPOXY
RESIN ALUMINUM BASEPLATE CONVENTIONAL
WIRE BASE INSULATION PLATE POWER MODULE
SILICONE NEW INSULATING BASE
GEL SILICON CHIP (ALN ISOLATOR)
Figure 4.5 Cross Section of U-Series Module Package 4.1.5 Features of U-Series IGBT
MAIN TERMINAL ELECTRODE COVER Packages
SILICONE GEL INSERT MOLDED CASE
A new IGBT module package
called “U-Series” was developed by
Mitsubishi Electric in 1996. The
new package technology achieves
a significant reduction in internal in-
ductance and improved reliability
over older designs. The time re-
quired to assemble the new mod-
ule was substantially reduced by
AL BOND WIRES CU BASE PLATE POWER CHIPS AIN SUBSTRATE
using a special case that has the
switching ruggedness of H-Series minimizing thermal impedance. power electrodes molded into its
IGBTs. Ultra clean facilities and Mitsubishi IGBT modules use sides rather than inserted after the
in-line wafer testing promote materials with similar thermal case is molded. Figure 4.5 is a
consistent processing, thus coefficients of expansion so that cross section drawing of the new
ensuring chips of the highest thermal stress is limited. Thus IGBT module package. The main
quality and reliability. these IGBT modules can be electrodes are connected directly
expected to provide improved to the power chips using large di-
4.1.4 Module Packaging thermal cycle life over existing ameter aluminum bonding wires. In
Construction and Layout power transistor modules. order to help simplify power circuit
and snubber designs or possibly
IGBT modules consist of multiple Free-wheeling diodes are also eliminate the need for snubbers al-
IGBT chips mounted on an mounted in the module for ease together an effort was made to
isolated substrate, which is itself of system assembly and to allow minimize the inductance of the new
mounted on a heatsinking copper minimum lead inductance, both U-Series package. A variety of
base plate (Figure 4.4A). inside and outside the module. techniques were used to reduce
Interconnection inside the modules each component of the package in-
Mitsubishi IGBT modules use an is accomplished with rigid bussing ductance. One of the most signifi-
isolating ceramic substrate with to ease assembly. Rigid bussing cant improvements was made pos-
copper patterns metallurgicly also offers symmetric layout of sible by the new insert molded
bonded to the top and bottom internal components so the case design. Wide electrodes are
surfaces. (Figure 4.4B). This parasitic inductance is reduced molded into the side of the case to
mounting method allows highly and module ruggedness is form parallel plate structures that
automated module assembly while enhanced. have considerably less inductance
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Static
ICES Collector-Emitter Leakage Current IC at VCE = VCES, VGE = 0, gate-emitter shorted, Tj = 25°C
IGES Gate-Emitter Leakage Current IG at VGE = VGES, VCE = 0, collector-emitter shorted, Tj = 25°C
VGE(th) Gate-Emitter Threshold Voltage VGE at IC = specified mA, VCE = 10V
VCE(sat) Collector-Emitter Saturation Voltage VCE at IC = rated IC and VGE = 15V
QG Total Gate Charge Charge on gate at VCC - 0.5~0.6VCES, rated, IC = rated IC, VGE = 15V
VEC Emitter-collector voltage Diode voltage at IE = -rated IC, VGE = 0V
Dynamic
Cies Input Capacitance Gate-emitter capacitance with VCE = 10V
Coes Output Capacitance Collector-emitter capacitance with the gate shorted to the emitter
Cres Reverse Transfer Capacitance Gate-collector capacitance with the emitter connected to the guard terminal of
the impedance analyzer
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Dynamic (Continued)
td(on) Turn-on Delay Time Time from VGE = 0V to IC = 10% of final value
tr Rise Time Time from IC = 10% of final value to IC = 90% of final value
td(off) Turn-off Delay Time Time from VGE = 90% of initial value to IC = 90% of initial value
tf Fall Time Time from IC = 90% of initial value to IC = 10% of initial value
trr Diode Reverse Recovery Time Time from IC = 0A to projection of zero IC from Irr and 0.5 Irr points with
IE = -rated IC and at specified di/dt (Refer to Figure 4.6)
Qrr Diode Reverse Recovery Charge Area under Irr curve from IC = 0A to projection of zero IC from Irr and
0.5x Irr points with IE = rated IC and at specified di/dt (Refer to Figure 4.6)
Figure 4.6 Reverse Recovery Measurement Circuit and Waveform Figure 4.7 VCE (sat) Test
C
trr
CURRENT
MONITOR RG
IE VGE V IC
D.U.T.
L Irr E
VGE 0.5 Irr
Qrr = 1/2 Irr trr
IE
VCC Figure 4.8 VCE Test
IE
t C
+VGE1 Irr
IC
V IC
-VGE2
t
E
4.2.4 Test Circuits and and VEC must be performed Figure 4.9 Resistive Load
Conditions as low duty factor pulsed tests. Switching Test Circuit
(See Figures 4.7 and 4.8) lC
-VGE2
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Figure 4.10 Switching Time Figure 4.11 Half-Bridge Switching Test Circuit
Waveform
VGE
90%
0 t
SHORT
lE VCC
lC
90%
+VGE1 RG
10% lC
0 -VGE2
t
td(off)
td(on) tr tf
4.3 Safe Operation Area MOSFET channel window gets the Mitsubishi IGBTs by careful
blocked and injection of electrons optimization of the device
Protecting IGBTs against cease. Removal of the stored geometry.
disturbance caused by over minority carriers (holes) in the
currents or over voltage is an “n” base region starts, and during The Switching SOA curve is the
important design topic in most this interval, the parasitic wide locus of points defining the
switching applications. In the case base pnp transistor operated by vir- maximum allowable simultaneous
of all hard switching applications, tue of its current gain occurrence of collector current and
such as inverter or chopper circuits characteristics causing the collector to emitter voltage during
for motor controls and transformer collector current to continue turn-off. Figure 4.14 shows that
loads, the turn-off switching SOA flowing. Thus, the later part of the H-Series IGBTs offer square
and short circuit capability are the IGBT turn-off fall current, is mainly switching SOA for 600V and
two most important ratings of due to the hole current. Some of 1200V devices at 2X rated current.
IGBTs today. the holes in the “n” base region
continues to cross through the The curves show that independent
4.3.1 The Turn-off Switching C-B junction of the parasitic npn of VCE, the device current must
SOA of IGBT transistor and travel horizontally be kept below 200% rated
below the “n” emitter layer. current. This limit is due to the
The turn-off switching SOA is simi- (Figure 4.13) designed current density of the
lar to RB SOA (Reverse Bias SOA) chips and internal connections in
of Darlington transistors. This flow of holes causes a the module.
The switching operation for a potential drop across the “p” body
typical inverter bridge circuit resistance, RD, and tends to
(Figure 4.11) will generate the activate the npn transistor. A
current and voltage waveform turn on of the npn transistor,
illustrated in Figure 4.12. In while the pnp transistor is still
turning off an inductive load active, can lead to pnp thyristor
current, the voltage rise precedes latch-up, which means loss of
the current fall. As the gate gate control and, eventually,
voltage reduces below its destruction of the device. This
threshold value, the intrastructural problem has been eliminated in
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Figure 4.12 Switching Waveforms (Half-Bridge Mode) 4.3.2 Short Circuit SOA
RG=3.9 ohm
Most power conversion
TURN-ON TURN-OFF
50A/div 50A/div
applications require that the
100V/div
50ns/div
100V/div applied switch should survive
T 50ns/div
a short circuit on the system
VCE T IC output without any damage.
When considering short circuit
T
withstand capability of IGBT
modules, two distinguishing
IC T VCE
O cases are generally reviewed:
Case-1 – Switching on of an
IGBT into a short circuit,
Figure 4.14 Turn-off Switching SOA
Case-2 – Load or groundfault
LIMIT FOR
250V
LIMIT FOR
600V
LIMIT FOR
1200V
LIMIT FOR
1400V
short-circuit across a
LIMIT FOR
CLASS
(-5F)
CLASS
(-12H)
CLASS
(-24H)
CLASS
(-28H)
1700V switched on IGBT.
CLASS
(-34H)
COLLECTOR CURRENT, IC, (NORMALIZED TO MODULE RATING)
2X
Figure 4.15 shows the circuitry
and waveforms for each case.
CONDITIONS:
Tj = 25∼125°C
VGE = ±15V In Case-1, as the IGBT turns
RG = SEE TABLE 4.2
RECOMMENDED RANGE on, initial rate of rise of IC is
VCC ≤ 150V (5F)
1X 400V (12H) determined by the wiring
800V (24H)
1000V(28H)
inductance, L. Also, the voltage,
1100V (34H) VCE, drops to some value below
VCC as the L discharges. Soon
after this, VCE switches back to
almost full VCC level. The dv/dt at
0
0 200 400 600 800 1000 1200 1400 1600
this switch back is coupled to the
COLLECTOR-EMITTER VOLTAGE (VOLTS) gate through the reverse transfer
capacitance thus causing a
Figure 4.13 High Injection On-state Electron and Hole Currents momentary rise of gate
within an IGBT Structure voltage.This extra gate voltage
mobilizes more electron and hole
EMITTER GATE
plasma within the IGBT module
structure. The effect of this
translates to a higher peak
collector current within a couple of
microseconds. The circuit design
N° (e.g. layout, bias condition,
P RB selection of RG, maximum supply
voltage, etc.) is important to
HOLE limit the short circuit current
N° e
magnitude in this high injection
N°
state. Due to high current density
P°
COLLECTOR
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
within the silicon, the internal SCSOA. (See Figures 4.16, 4.17, In Figures 4.16, 4.17, 4.18, 4.19,
temperature rises and it causes the 4.18, 4.19, and 4.20) and 4.20 the short circuit self limita-
high short circuit peak current to re- tion in Case-1 is shown as
duce to a lower value which corre- In Case-2 short circuit an external the dark area. Careful precautions
sponds to what is called a satura- short circuit occurs while the IGBT must be considered in Case-2 to
tion current. To protect the device is already in the on state. (See prevent the short circuit current
from destruction, the Figure 4.15B) The increasing short magnitude going beyond a magni-
current has to be cut off within a circuit forces the IGBT chip to tude of ten times the rated current
specified period, which is normally desaturate causing the collector- as an absolute limit (shaded area
specified by the input gate pulse emitter voltage to rise from in Figures 4.16, 4.17, 4.18, 4.19,
width, tw. At turn off, a sharp fall of VCE(sat) to almost full VCC. The and 4.20).
collector current in the presence of dv/dt during IGBT desaturation
the wiring inductance, L1, causes may be higher compared to Cautions:
VCE to shoot up by an amount Case-1 and is coupled back 1. SCSOA is valid for gate pulse
equivalent to: through the reverse transfer width, tW, ≤ 10µs
capacitance, which is now higher at 2. SCSOA is a non-repetitive
∆VCE ≈ L1 X diC/dt. the low on-state voltage, and may capability. H-Series IGBT
result in a higher momentary rise of modules can survive up to 100
The instantaneous value of gate voltage. As a result the magni- short circuit events on a
collector-emitter voltage, VCE, tude of the short circuit in Case-2 non-repetitive basis over the
including this surge peak value can reach significantly higher val- life of the equipment.
must not be allowed to go beyond ues than in Case-1.
the specified voltage limit given by
(A) (B)
LI lC
CASE-1 CASE-2
Q1 (on) C
SHORT-CIRCUIT lC (OFF) SHORT-CIRCUIT
G
C
RG VCC
G
VCE VCC
VGE E
L12
(OFF)
Q4 (on)
SHORT
VCE
∆VCE
dv/dt VCE
IC VCE(pk)
VCE(pk)
ICP
IC
VGE
VCC VCC
IC(off)
ICP dv/dt
IC(off)
t tw
Q1 ON
tw STATE LOAD SHORTED
IGBT TURN-ON
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Figure 4.16 Short-Circuit SOA Figure 4.17 Short-Circuit SOA 4.4 Performance Curves
for Modules 600V for Modules 1200V
Class Class The characteristic curves show
600V CLASS 1200V CLASS typical electrical characteristics and
10X
maximum transient thermal imped-
10X
ance characteristics of the IGBT
9X 9X and FWDi.
8X 8X
4.4.1 Output Characteristics
COLLECTOR CURRENT, IC, (NORMALIZED)
COLLECTOR CURRENT, IC, (NORMALIZED)
CONDITIONS: CONDITIONS:
7X VCC ≤ 400V 7X VCC ≤ 800V
Tj = 25∼125°C Tj = 25∼125°C The output characteristics
VGE = ±15V VGE = ±15V
6X 6X tw = 10µs (Figure 4.21) define the value of
tw = 10µs
RG = SEE TABLE 4.2 5X RG = SEE TABLE 4.2 VCE that the IGBT will have when
5X
RECOMMENDED RECOMMENDED conducting a given IC for a given
RANGE RANGE
4X 4X value of VGE. The IGBT is
intended for switching operation
3X
3X only and the range for practical
2X
use is limited to the range of VCE
2X
within the saturation area.
1X 1X
4.4.2 Collector-Emitter
0 0
0 100 200 300 400 500 600 0 200 400 600 800 1000 1200 Saturation Voltage
COLLECTOR-EMITTER VOLTAGE, VCE, (VOLTS) COLLECTOR-EMITTER VOLTAGE, VCE, (VOLTS)
9X 9X 9X
8X 8X 8X
X 100 (%)
X 100 (%)
X 100(%)
6X 6X 6X
tw ≤ 10µs tw ≤ 10µs tw = 10µs
RG = SEE TABLE 4.2 RG = RECOMMENDED RECOMMENDED
RG = R
COLLECTOR CURRENT I
COLLECTOR CURRENT
COLLECTOR CURRENT I
4X 4X 4X
3X 3X 3X
2X 2X 2X
1X 1X 1X
0 0 0
0 200 400 600 800 1000 1200 0 500 1000 1500 0 50 100 150 200 250
COLLECTOR-EMITTER VOLTAGE, VCE, (VOLTS) COLLECTOR-EMITTER VOLTAGE, VCE, (VOLTS) COLLECTOR-EMITTER VOLTAGE, VCE, (VOLTS)
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
12
160 VGE = 20V
15 perature coefficient becomes posi-
8
tive. Table 4.1
120 Cies = CGE + CGC (in parallel)
Figures 4.22 and 4.23 show (measured C-E shorted)
7
80 typical collector-emitter saturation Coes = CCE + CGC
voltage characteristics, VCE(sat) (measured G-E shorted)
6
40 versus IC, and VCE(sat) versus Cres = CGC
5 VGE respectively.
0
0 2 4 6 8 10
4.4.4 Gate Charge
COLLECTOR-EMITTER VOLTAGE, VCE, (VOLTS) 4.4.3 Device Capacitance
Since input capacitance varies
As the IGBT is a MOS gate with VCE voltage, another
Figure 4.22 device, it has three characteristic parameter is used to better specify
capacitances Cies, Coes, and the energy required to turn on and
COLLECTOR-EMITTER
SATURATION VOLTAGE CHARACTERISTICS Cres. These capacitances are off the IGBT, the gate charge, QG
(TYPICAL)
5
specified in the data sheet characteristic. The “QG vs. VGE”
because they are the most readily curve shows the charge necessary
VGE = 15V
SATURATION VOLTAGE, VCE(sat), (VOLTS)
4
Tj = 25°C measured. They can be used to switch the IGBT. The first slope
Tj = 125°C
to determine the IGBT junction corresponds to the charging of the
COLLECTOR-EMITTER
3
and diffusion physical input capacitance while VCE
capacitance, CGE, CGC, and equals VCC. When the VGE(th) is
2
CCE, by the formula given in achieved, the collector current, IC,
Table 4.1 All three specified causes the VCE to decrease to-
1
capacitances are small during wards VCE(sat). During the VCE
device off state, but the large fall the CGC capacitance increases
0
diffusion capacitance portion of rapidly and prevents the increase
0 160 320 480 640 800 the gate-collector capacitance of VGE as it draws more charge.
COLLECTOR-CURRENT, IC, (AMPERES)
Figure 4.23 Figure 4.24 IGBT Device Figure 4.25 Typical IGBT
Capacitances Capacitances
COLLECTOR-EMITTER
SATURATION VOLTAGE CHARACTERISTICS E
(TYPICAL) CAPACITANCE VS. VCE
LG (TYPICAL)
10 105
Tj = 25°C Cies
SATURATION VOLTAGE, VCE(sat), (VOLTS)
G
CAPACITANCE, Cies, Coes, Cres, (pF)
8
e e Coes
COLLECTOR-EMITTER
n+ n+
p+ p p p+ 104
6 IC = 800A
RB
4
IC = 400A
103 Cres
n–
2 IC =160A n+
p+
0 102
0 4 8 12 16 20 10-1 100 101 102
GATE-EMITTER VOLTAGE, VGE, (VOLTS)
COLLECTOR-EMITTER VOLTAGE, VCE, (VOLTS)
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Figure 4.26 Typical Gate When VCE stabilizes, the input ca- load. (See Figure 4.28) This
Charge pacitance also stabilizes and the reflects the fact that inductive
GATE CHARGE, VGE
additional charge increases the loads are the most prevalent
20 VGE voltage up to the full on level. application for IGBTs. The
IC = 400A At turn off the same charge quan- switching times are defined in
GATE-EMITTER VOLTAGE, VGE, (VOLTS)
lE
VCC
Figure 4.29 shows the voltage drop
102 tr between anode and cathode when
a forward current is supplied to the
+VGE1 RG VCC = 600V FWDi.
VGE = ±15V
RG = 1.6Ω
lC Tj = 125°C
-VGE2
101
101 102 103
COLLECTOR CURRENT, IC, (AMPERES)
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Typical reverse recovery temperature per unit of power 4.4.8 Switching Energy Charac-
characteristics of the FWDi are applied for a given time period. teristics
shown in Figure 4.30. These (See Figures 4.31 and 4.32) The
measurements are made using a value of Zth(j-c) is obtained by Switching energy curves are pro-
circuit which operates as a multiplying the value of Rth(j-c) by vided in order to simplify estimation
half-bridge with inductive load. the normalized factor taken from of switching losses.
(Figure 4.28A) The low values of the curve at the time of interest. Use of these curves is described
trr and Irr and their relative The steady state thermal in more detail in Section 3.4.1 of
independence of forward current resistance, Rth(j-c) is the this application data. Figures 4.33
are a unique feature of the FWDi saturated value of Zth(j-c). If this through 4.41 show turn-on and
used in H-Series IGBT modules. value is smaller, the maximum turn-off switching energy as a func-
allowable power loss, PC, of a tion of collector current for
4.4.7 Transient Thermal device becomes larger: Mitsubishi 250V, 600V, 1200V,
Impedance 1700V H-Series and U-Series
Tj(max) – TC IGBT modules. Figures 4.42 and
The transient thermal impedance, PC = 4.43 show switching loss versus
Zth(j-c) gives the rise of junction Rth(j-c)
series gate resistance for U-Series
temperature over case IGBT modules.
Tj = 25°C
operation. The first criterion is that
Irr
the peak collector current during
102 101 operation including any required
102 t rr overload current must be within the
SWSOA (this means < 2 x Irated or
2 x nameplate current). The
suggested IGBT selections in
101 100 Sections 2.3, 2.4, and 2.5 are
101 101 102 103 based on a 200% overload
0.8 1.2 1.6 2.0 2.4 2.8 EMITTER CURRENT, IE, (AMPERES)
EMITTER-COLLECTOR VOLTAGE, VEC, (VOLTS) requirement and allow 20% for
ripple current factors in
Figure 4.31 Figure 4.32 determining the peak IGBT current
TRANSIENT THERMAL TRANSIENT THERMAL requirement for the inverter. The
IMPEDANCE CHARACTERISTICS IMPEDANCE CHARACTERISTICS
(IGBT) (FWDi) second criterion is that the IGBT
10-3 10-2 10-1 100 101 10-3 10-2 10-1 100 101 operating junction temperature
NORMALIZED TRANSIENT THERMAL IMPEDANCE, Z th(j-c)
NORMALIZED TRANSIENT THERMAL IMPEDANCE, Z th(j-c)
101 101
Single Pulse Single Pulse must always be kept below Tj(max)
TC = 25°C TC = 25°C
Per Unit Base = R th(j-c) = 0.08°C/W Per Unit Base = R th(j-c) = 0.18°C/W (150°C) in all normal operation in-
Zth = Rth • (NORMALIZED VALUE)
Zth = Rth • (NORMALIZED VALUE)
100 100
cluding expected motor overload.
Power dissipation and thermal de-
10-1 10-1 10-1 10-1 sign considerations are discussed
in detail in Section 3.4. Modules
selected for listing in
10-2 10-2 10-2 10-2
Sections 2.3, 2.4, and 2.5 will
meet these requirements with
10-3 10-3 10-3 10-3 normal environmental and
10-5 10-4 10-3 10-5 10-4 10-3
TIME, (s) TIME, (s)
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
TURN-ON
CM-600**-12H
TURN-ON
101 102 100 101
CM-400**-12H
CM-300**-12H
CM30TF*-12H
CM-200**-12H
CM20TF*-12H
TURN-OFF SWITCHING, ESW (mJ/PULSE)
TURN-ON SWITCHING, ESW (mJ/PULSE)
CM15TF*-12H
CM-75**-12H
CM15/20/30TF*-12H
CM50-600**-12H TURN-OFF IC = Ir/10~Ir FOR TURN-OFF
IC = Ir/10~Ir FOR
10-1 EACH MODULE
100 10-2
EACH MODULE
10-1
CONDITIONS: CONDITIONS:
HALF-BRIDGE SWITCHING MODE HALF-BRIDGE SWITCHING MODE
Tj = 125°C Tj = 125°C
VCC = 300V VCC = 300V
VGE = ±15V VGE = ±15V
RG = 625/Ir RG = 625/Ir
TURN-ON
TURN-ON
CM400**-24H
CM300**-24H
CM30TF-24H
CM200**-24H
CM20TF-24H
CM150**-24H
CM15TF-24H
102
TURN-OFF SWITCHING, ESW (mJ/PULSE)
CM100**-24H
101
TURN-ON SWITCHING, ESW (mJ/PULSE)
100 101
CM75**-24H
CM600**-24H
CM50**-24H
CM400**-24H
CM300**-24H
CM30TF-24H
CM200**-24H
CM20TF-24H
TURN-OFF
CM150**-24H
CM100**-24H
CM75**-24H
CM50**-24H
TURN-OFF
10-2 CONDITIONS:
10-1 10-1 100
CONDITIONS:
HALF-BRIDGE SWITCHING MODE Tj = 125°C
Tj = 125°C VCC = 600V
VCC = 600V VGE = ±15V
VGE = ±15V RG = 313/Ir
RG = 313/Ir CM600HA-24H : RG = 2.1Ω
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
CM600HA-5F
101 TURN-ON 102
CM450HA-5F
TURN-OFF
CM350DU-5F
102 102
CM1000HA-24H TURN-OFF
100 101
CM600HA-5F
CM450HA-5F
CM350DU-5F
10-1 CONDITIONS:
100
CONDITIONS: Tj = 125°C
Tj = 125°C VCC = 100V
VCC = 600V VGE = ±10V
VGE = ±15V RG = 2500/Ir
RG = 3.3Ω
Figure 4.39
SWITCHING ENERGY
1400V CLASS H-SERIES IGBT MODULE
CONDITIONS:
Tj = 125°C
VCC = 800V
VGE = ±15V
RG = 312/Ir
CM600HA-28H: RG = 2.1Ω
CM1000HA-28H: RG = 3.3Ω
TURN-OFF SWITCHING, ESW (mJ/PULSE)
TURN-ON SWITCHING, ESW (mJ/PULSE)
CM1000HA-28H
102 102
CM600HA-28H
CM400HA-28H
CM300DY-28H
TURN-OFF
CM200DY-28H
CM50~1000-28H
(IC = Ir /10~Ir)
CM100TF-28H
101 101
TURN-ON
CM75**-28H
CM50**-28H
100 100
100 101 102 103
COLLECTOR CURRENT, I C (AMPERES)
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
CM300DU-24H
CM600HU-24H
TURN-OFF
CM400DU-12H
CM200DU-24H
101 101
CM150DU-24H
CM400HU-24H
CM300DU-12H
101 101
CM100TU-24H
CM200TU-12H
CM75TU-24H
CM150TU-12H
CM100TU/BU-12H
CM50TU-24H
CM75TU/BU-12H
TURN-ON TURN-ON
CM600HU-12H
100 100
CM300DU-24H
CM400DU-12H
CM200DU-24H
CM150DU-24H
100 100
CM300DU-12H
CM100TU-24H
CM200TU-12H
CM75TU-24H
CM50TU-24H
CM150TU-12H
CM100TU/BU-12H
10-1 10-1
101 102 101 102
COLLECTOR CURRENT, IC (AMPERES) COLLECTOR CURRENT, IC (AMPERES)
Tj = 125°C
VCC = 300V VCC = 600V
VGE = ±15V TURN-ON VGE = ±15V
CM-100*U-12H
IC = Ir IC = Ir CM600HU-24H
CM-75*U-12H
TURN-ON
CM600HU-12H
103
TURN-ON SWITCHING, ESW (mJ/PULSE)
TURN-ON SWITCHING, ESW (mJ/PULSE)
CM600HU-12H CM100*U-24H
101 102
CM400DU-12H CM600HU-24H
CM75*U-24H
CM300DU-12H CM400HU-24H
CM200*U-12H
100 101 CM300DU-24H CM50*U-24H
CM200DU-24H
CM150*U-12H
CM150DU-24H
CM100*U-24H
CM100*U-12H
CM75*U-24H
CM75*U-12H 100 101
TURN-OFF CM50*U-24H
TURN-OFF
10-1 100
100 101 100 101
GATE-RESISTANCE, RG (Ω) GATE RESISTANCE, RG (Ω)
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
heatsink considerations. It may its off state when dv/dt noise is Figure 4.44 Typical IGBT Gate
be possible (or required) to use a present in the collector-emitter Drive Circuit
lower (higher) current rated if voltage an off bias must be used. +VGE
more (or less) efficient cooling Use of reverse bias also decreases
is employed. turn off losses. The relationship Q1
between reverse bias voltage and
RG
4.6 IGBT Module Gate Drive switching losses is shown in
Figure 4.45. For H-Series IGBTs VG
18V
IGBTs require gate voltage to an off bias of -5 to -15V is recom- Q2
circuit include device off biasing should only appear on the IGBT’s RG: See Table 4.2 or data sheet
for suggested value
requirements, gate charge gate during rapid switching
requirements, ruggedness transitions. Figure 4.45 Switching Energy
requirements and power supply as a Function of
availability. 4.6.2 RG - Series Gate Reverse-Bias
Resistance Voltage
A recommended drive circuit
103
includes substantial on biasing Selecting the proper series gate re- CONDITIONS:
and off biasing. Such a circuit is sistor for IGBT gate drive is very HALF-BRIDGE INDUCTIVE LOAD
MOSFET the IGBT turn-off bias resistor will charge/discharge the Esw(on)
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
tor is the standard resistor that is Table 4.2 was generated frequency, chopper, and resonant
used for determining all data sheet considering hard switched mode applications for which values
parameters and characteristics. inductive load applications which of series gate resistance outside of
The maximum value given allows represent the majority of IGBT the limits in the table may be used.
for flexibility in slowing down the applications. There are some low Consult the factory for specific
switching speed and avoiding po- recommendations in these cases.
tential oscillation problems without Table 4.2 Values of Gate Resistance
risking linear operation. It also pro-
vides for slower switching in lower Recommended Series Gate Resistance, RG, (ohms)
frequency applications where
Voltage Turn-on
switching losses are not as critical (Volts) Type Number Min. Max
and reduced transient voltages and
gate drive current CM15**-12H 42 420
requirements may be a factor. CM20**-12H 31 310
CM30**-12H 21 210
CM50**-12H 13 130
Figure 4.46 Typical
Dependence of CM75**-12H 8.3 83
Switching Time on 600 CM100**-12H 6.3 63
Gate Resistance CM150**-12H 4.2 42
104 CM200**-12H 3.1 31
CONDITIONS:
HALF-BRIDGE INDUCTIVE LOAD CM300**-12H 2.1 21
SWITCHING OPERATION
Tj = 125oC CM400**-12H 1.6 16
VCC = 300V
td(on), tr, td(off), tf, (ns)
tf CM30**-24H 10 100
tr CM50**-24H 6.3 63
CM75**-24H 4.2 42
102
100 101 102 1200 CM100**-24H 3.1 31
GATE RESISTANCE, RG, (Ω)
CM150**-24H 2.1 21
CM200**-24H 1.6 16
Figure 4.47 Typical CM300**-24H 1.0 10
Dependence of
CM400**-24H 0.78 8
Switching Loss on
Gate Resistance CM600**-24H 2.1 22
CM1000**-24H 3.3 33
103
CONDITIONS: CM50**-28H 6.3 63
HALF-BRIDGE INDUCTIVE LOAD
CM75**-28H 4.2 42
SWITCHINTG LOSS, ESW (mJ/PULSE)
SWITCHING OPERATION
Tj = 125oC
VCC = 300V CM100**-28H 3.1 31
VGE = ±15V
CM200DY-28H 1.6 16
102
Esw(on)
1400 CM300DY-28H 1.0 10
CM400HA-28H 0.78 8
Esw(off) CM600HA-28H 2.1 22
101
CM1000HA-28H 3.3 33
100 101 102
1700 CM400HA-34H 10 50
GATE RESISTANCE, RG, (Ω)
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
4.6.3 Gate Drive Power 2. Care must be taken to avoid Appropriate measures to
Requirements coupling of noise between the reduce these parasitic
power circuit and the control capacitances have to be
IGBT switching consumes power circuit. This can be implemented.
from the gate drive power supply accomplished by proper
as a function of the transition from placement of the gate drive 8. If optocouplers are used for
negative to positive bias, ∆GE, the board and/or shielding the isolation of the high side gate
total gate charge, QG, and the gate drive circuit. drive signals they should have
frequency of operation, f. The a minimum common mode
minimum peak current capability, 3. It is recommended to use the transient immunity of
IG(pk) of the supply is: auxiliary emitter terminal for 10,000 V/µs.
connecting the gate drive.
∆VGE
IG(pk) = ± 4. If direct connection of the
RG Figure 4.48 Total Gate Charge
drive PCB to the IGBT control in IGBT Switching
terminals is not possible, the
The average power, PAVG,
use of twisted pair (3 turns per VGE (V)
required of the supply is:
inch of minimum length) or
QG
stripline is recommended.
PAVG = ∆VGE * QG * f
(+VGE)
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
4.7 Protecting IGBT Modules Figure 4.50 One-Phase Circuit of an Inverter Bridge
(Inductive Load)
4.7.1 dv/dt Protection
D1
In half-bridge and inductive mode
operation the IGBT that is in the Q1 VQ1
VQ1 = IL
off state is subjected to sharp rise RG
VCC
of positive voltage due to recovery LOAD
Irr
of its anti-parallel diode. (See
VQ2 = –IL
Figures 4.50 and 4.51) This static Q2
D2 VQ2
dv/dt can be higher than the rate RG
of rise of VCE at turn off of the
IGBT. This dv/dt generates a
current in the collector gate
capacitance that flows into the gate
Figure 4.51 Relevant Current and Voltage Waveforms of
drive circuit. (See Figure 4.52) Al-
Phase Elements
though the gate is reverse
biased in the off-state, this current Irr
IQ2 VQ2(pk)
causes an increase of VGE VQ2 trrb
towards VGE(th) due to the gate cir- Irr
cuit impedance. In the worst case,
dIQ1/dt dVQ1/dt
the threshold voltage is reached at
the IGBT chip and turn on of the
IGBT is initiated resulting in an arm VQ1(pk)
shoot through. The ID1
dVQ1/dt VQ1
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
4.7.2 Short Circuit Protection reduced as the IGBT turns off. short circuit, tw. However, this
The spike voltage is also will increase the magnitude of
If a short circuit occurs the stress reduced. the current at turn off (See Fig-
on the IGBT must remain within ure 4.56) and di/dt will be in-
the SCSOA. (See Section 4.3.2) 2. VGE Clamping: creased. This undesirable ef-
Common methods of short circuit As described in Section 4.3.2 fect may be overcome by using
protection are current sensing (See the peak of the short circuit the techniques in Steps 1 and
Figure 4.53) and desaturation current depends on VGE which 2 above.
detection (See Figure 4.54). is augmented by the feedback
of dv/dt through the gate-col- Caution:
Once a short circuit is detected, lector capacitance. The effect The above techniques reduce the
several techniques can be can be overcome by clamping stress at short circuit turn-off.
employed to protect the IGBT from the VGE safely below 18 Volts. However, they do not release the
destruction. The most elementary An effective clamping circuit is designer from considering worst
technique is to simply turn off the shown in Figure 4.55. The case turn off in snubber design.
IGBT within 10ms. But, in this clamping diode, DCL, and
case, the snubber or clamp must clamping capacitor, CCL, 4.7.3 Handling Precautions
be designed for the short circuit should be connected directly to
condition. However, it is the control signal terminals of Since IGBT gates are insulated
recommended to use turn-off the IGBT module. A fast for- from any other conducting region,
techniques that control the VGE in ward recovery is required for care should be taken to prevent
order to reduce the stress on the DCL. For low current IGBTs a static build up which could possible
IGBT. These techniques are: zener clamp between gate and damage gate oxides. All H-Series
emitter may also be effective. IGBT modules are shipped from
1. Controlled Shutdown: the factory with conductive foam
The gate voltage is reduced 3. Reducing tw: contacting the gate and emitter
either in steps or by a ramp For reducing the thermal stress control terminals. Never touch the
so the short circuit current is in short circuit operation it is gate terminals during assembly
reduced and its di/dt is also beneficial to reduce the time in and keep the conducting foam in
DRIVER
BUS
CURRENT
SENSE
M
CURRENT
COMPARATOR
SENSOR +
R Q
–
<F.F.> UNDER PROTECTION PWM SIGNALS
S <PWM SIGNAL GENERATOR>
LATCH DISABLE <SIGNAL GATE>
CLEAR PROTECTION
CLEAR 6
UNDER PROTECTION PWM SIGNALS
<PWM SIGNAL GENERATOR>
CLEAR PROTECTION
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
place until permanent connections 2. Use a 100V resistor in series 4.8 Parallel Operation
are made to the gate and emitter with the gate when performing
control terminals. Always ground curve tracer tests. Mitsubishi IGBT modules can be
parts touching gate terminals dur- connected in parallel for applica-
ing installation. In general, stan- 3. Never install devices into tions requiring very high currents.
dard ESD precautions applicable to systems with power connected In such applications parallel opera-
MOSFETs should to the system. tion should only be considered
be followed. when the highest current module
4. Use soldering irons with available is not large enough. Use
Other handling precautions that grounded tips when soldering of a single large module rather
should be observed are: to gate terminals. than smaller parallel modules is
recommended because it elimi-
1. Use grounded work station nates concerns about static and
with grounded floors and dynamic current balance among
grounded wrist straps when the paralleled devices.
handling devices. With proper attention to circuit de-
sign and device selection several
modules can be reliably operated
in parallel. The following
Figure 4.54 Out of Saturation Short-Circuit Protection
sub-sections outline the basic re-
quirements and considerations for
ONLY FOR ARM SHORT CIRCUIT parallel operation of single IGBT
OUT OF SATURATION SHORT CIRCUIT DIAGRAM
modules with ratings of 200A or
more.
COMPARATOR
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
ance as a function of saturation rated 200A or more. Saturation When modules of the same satura-
voltage at Tj = 25°C is shown in voltage ranking is not normally tion voltage rank are paralleled the
Figure 4.57. Experimental analysis available for dual or six pack types. static current imbalance will be
has demonstrated that the current Modules of different saturation volt- minimized so
balance becomes considerably bet- age ranks may be used in the that the following recommended
ter at elevated junction tempera- same inverter provided that de- deratings can be applied:
tures. For example, in the case of vices connected in parallel are of
1200V H-series the worst case im- the same rank.
balance drops from 15%
at 25°C to about 5% at 125°C. Fig-
ure 4.58 shows how the imbalance Table 4.4 IGBT Module Parallel Operation, Current Sharing
shown in Figure 4.57 is defined. To
Factors related to current sharing and their effect.
facilitate the matching of devices
for parallel operation Mitsubishi Categories of Current Sharing
provides IGBT modules marked IGBT Switching Steady State
with a saturation voltage rank letter. Factors Effecting Current Sharing Turn-on Turn-off di/dt = 0 di/dt ≠ 0
All devices to be operated in paral- Device ∆VCE(SAT) X X ● X
lel should have the same saturation Characterization ∆ Temperature ● ● ● X
voltage rank. Devices can also be Main ∆L (Supply to ● ∂ X X
supplied in matched sets for paral- Circuit Device)
lel applications. Contact the factory Wiring ∆L (Total Loop X X X ●
Inductance Including Load)
for ordering information. Table 4.5
shows the standard saturation volt- Driver to Device ● ● X X
age letter rankings for Mitsubishi Driver Wiring Length Diff.
Wiring Output Impedance ● ● X X
IGBT modules. Column 1 of this
of Driver
table is applicable to all voltage
classes of U-Series and H-Series ● - Relation Exists X - No Relation ∂ - Relation Ambiguous or Weak
modules and column 2 applies to
250V trench gate IGBT modules.
Note that all ranks do not exist for a Table 4.5 Saturation Voltage Ranks For Parallel Applications
given voltage class. For example,
600V H-Series modules have a Saturation Voltage Ranks for H-Series Saturation Voltage Ranks for 250V
maximum data sheet saturation and U-Series IGBT Modules Trench Gate IGBT Modules
voltage of 2.8V and therefore ranks Saturation Voltage VCE(sat) (V) Saturation Voltage VCE(sat) (V)
H through M do not exist for these Rank IC = Rated Current Rank IC = Rated Current
devices. Saturation voltage ranks VGE = 15V VGE = 15V
Tj = 25C Tj = 25C
are intended for matching sets of
C 1.70 ~ 1.95 Q 1.15 ~ 1.30
devices for parallel applications.
D 1.90 ~ 2.15 R 1.25 ~ 1.40
Orders specifying a specific rank
E 2.10 ~ 2.35 S 1.35 ~ 1.50
will not normally be accepted. The
F 2.30 ~ 2.55
saturation voltage rank will be ei-
G 2.50 ~ 2.80
ther marked with white ink on the
top of the module or indicated on H 2.75 ~ 3.05
the label. Saturation voltage rank- J 3.00 ~ 3.30
ing is available for single modules K 3.25 ~ 3.55
L 3.50 ~ 3.80
M 3.75 ~ 4.05
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Figure 4.57 Maximum Current Figure 4.58 Circuit Showing the 4.8.2 Dynamic Current Balance
Imbalance vs. Definition of
DVCE(sat) Current Imbalance Matching VCE(sat) is effective for
maintaining good static steady
30
IC - ∆IC IC + ∆IC
state current balance. This match-
ing also helps some with turn off
current balance because of the fun-
20
damental inverse relationship of fall
time and saturation voltage. How-
∆IC/IC x 100%
[( )
(n – 1) (1 – x) + 1 the result of an asymmetric con-
1–
___________
(1 + x)
______________
n
] X 100
nection of the load as shown
in Figure 4.59. A typical current im-
balance waveform resulting from
Where: an asymmetric load connection is
shown in Figure 4.60. Experimental
x = 0.1 for 250V devices analysis has shown that this type of
x = 0.1 for 600V devices imbalance can also be caused by
x = 0.15 for 1200V/ the orientation of the main circuit
1400V devices bus bars. For example, if the load
x = 0.20 for 1700V devices connection causes the load current
n = number parallel to run in parallel with the current in
one of the paralleled modules mu-
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
tual inductance effects can cause vices should be connected with a eral, the best practice is to mini-
the inductance of that short, low impedance symmetric mize the inductance in the gate
path to be effectively reduced or in- connection in order to prevent drive wiring. Use of a printed circuit
creased even though the mechani- ground loop currents from disrupt- board mounted directly to the mod-
cal connection point is symmetric. ing the gate drive. In some power ule or short tightly twisted wires of
circuit layouts it may become nec- equal length is recommended.
The second case that must be con- essary to put some part of the RG Care should be exercised to avoid
sidered is current imbalance that impedance in the ground path to inductive coupling to the gate drive
occurs at the moment of turn-on or impede the flow of ground loop cur- by keeping the wiring from running
turn-off switching. Table 4.4 indi- rents. However, in this case im- parallel to the main circuit current.
cates that the most important fac- provements in the power circuit lay- Figure 4.62 shows a typical turn-off
tors influencing current balance are out should be investigated first. In current waveform with imbalance
the gate circuit design and module order to maintain uniform switching caused by an improper gate drive.
temperature. The recommended it is recommended to use relatively In addition to the influences of tem-
gate drive configuration for paral- small values of series gate resis- perature and gate drive the current
leled modules is shown in Figure tance. Series gate resistors should balance at turn-on is influenced by
4.61. The recommended approach never be larger than ten times the the symmetry of the inductance in
is to use a single drive stage with a value recommended on the data the power circuit between the main
separate RG for each paralleled sheet of the module being used. supply capacitors and devices.
module. The small kelvin emitter Care must be exercised to make Figure 4.63 is a circuit showing
connections on the paralleled de- the gate wiring symmetric. In gen- symmetric versus asymmetric main
Figure 4.59 Circuit Diagram Showing Symmetric and Asymmetric Figure 4.60 Typical Current
Load Connections Imbalance Caused
by Assymetric
Load Connection
IC1 IC2
lC
ASYMMETRIC
LOAD
CONNECTION lC1
lC2
SYMMETRIC
LOAD
CONNECTION
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Figure 4.61 Gate Drive Configuration for Paralleled Modules Figure 4.62 Typical Current
Waveform Showing
Imbalance at Turn-
off Due to Improper
USE SAME RG
Gate Drive
RG
RG
GATE AND EMITTER TWIST
CONNECTIONS LOW
INDUCTANCE AND
SYMMETRIC
Sep.1998
MITSUBISHI SEMICONDUCTORS POWER MODULES MOS
Figure 4.63 Symmetric and Asymmetric Main Circuit Connections Figure 4.64 Typical Turn-on
Waveform with
Current Imbalance
ASYMMETRIC
Caused by
MAIN BUS Asymmetric Main
CONNECTION SYMMETRIC
MAIN BUS Circuit Inductance
CONNECTION
IC1 IC2
lC
lC1
lC2
Sep.1998