Physics Matters: Statistical Aging Prediction under

Trapping/Detrapping
Jyothi Bhaskarr Velamala
1
, Ketul Sutaria
1
, Takashi Sato
2
, Yu Cao
1

1
School of Electrical, Computer and Energy Engineering, Arizona State University, Tempe, AZ 85287
2
School of Informatics, Kyoto University, Kyoto, Japan
{jvelamal, kbsutari, ycao}@asu.edu, {takashi}@i.kyoto-u.ac.jp

ABSTRACT
Randomness in Negative Bias Temperature Instability (NBTI) pro-
cess poses a dramatic challenge on reliability prediction of digital
circuits. Accurate statistical aging prediction is essential in order to
develop robust guard banding and protection strategies during the
design stage. Variations in device level and supply voltage due to
Dynamic Voltage Scaling (DVS) need to be considered in aging
analysis. The statistical device data collected from 65nm test chip
shows that degradation behavior derived from trapping/detrapping
mechanism is accurate under statistical variations compared to
conventional Reaction Diffusion (RD) theory. The unique features
of this work include (1) Aging model development as a function of
technology parameters based on trapping/detrapping theory (2)
Reliability prediction under device variations and DVS with solid
validation with using 65nm statistical silicon data (3) Asymmetric
aged timing analysis under NBTI and comprehensive evaluation of
our framework in ISCAS89 sequential circuits. Further, we show
that RD based NBTI model significantly overestimates the degra-
dation and TD model correctly captures aging variability. These
results provide design insights under statistical NBTI aging and
enhance the prediction efficiency.
Categories and Subject Descriptors
B.7.2 [Integrated Circuits]: Design Aids performance analysis
and design aids; B.8.2 [Performance and Reliability]: Perfor-
mance Analysis and Design Aids.
General Terms
Design, Experimentation, Performance, Reliability
Keywords: Negative Bias Temperature Instability, Hole Trap-
ping, Dynamic Voltage Scaling, Timing Violations
1. INTRODUCTION
Negative Bias Temperature Instability (NBTI) is a serious reliabil-
ity concern in todays digital circuits and becomes predominant
with CMOS technology scaling [1][4]. NBTI manifests itself as an
increase in the threshold voltage (V
th
) of PMOS devices, resulting
in gate and circuit delay shift [3]. Accurate prediction of the aging
rate during the design stage is crucial to the decision of guard band-
ing. However, statistical prediction is not trivial since NBTI has
strong dependence on device physical parameters and operation
conditions. The situation is more complex in todays digital circuits
as they operate under multiple V
DD
in Dynamic Voltage Scaling
(DVS), leading to supply voltage variations. Hence, it is critical to
understand, simulate and mitigate the NBTI effect in early design
stages to ensure reliable circuit operation for desired lifetime [5].
NBTI mechanism has been explained by the classical Reaction
Diffusion (RD) model. According to RD model, V
th
follows pow-
er law relation with stress time, where the time exponent (n) should
be independent of process and operation parameters. However,
Figure 1a illustrates that even from the same process and the same
stress condition, the values of n from three different devices do not
match with each other, similar to that observed at circuit level [6].
V
th
prediction from RD model is very sensitive to the time expo-
nent. Hence, even a small change in n leads to dramatic difference
in long term prediction of circuit lifetime [7]. On the other hand,
recent works show the role of charge trapping/detrapping (TD) in
NBTI degradation, where PMOS V
th
increases if a trap captures the
channel carrier. TD based BTI model follows logarithmic relation
with time and is less sensitive to variation in model parameters.
Further, this work incorporates V
th
dependence on technology
parameters in TD model and correctly predicts statistical aging.
Threshold voltage and gate delay shifts can be determined using
TD model based on the circuit operation conditions. Todays circuit
operation involves multiple V
DD
under Dynamic Voltage Scaling
(DVS). Figure 1b presents the operation pattern in a 65nm dual
core Intel processor and threshold voltage shift under such an oper-
ation. When the supply voltage is changed from a higher V
DD
to
lower V
DD
, the degradation undergoes recovery. TD model correct-
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Figure 1. (a) Variation of time exponent extracted from
three 65nm devices (b) DVS operation pattern in a Intel
65nm processor and predicted V
th
.

VDD
Device 1 Device 2 Device 3
0.0
5.0x10
4
1.0x10
5
0.25
0.50
0.75
1.00
A
V
t
h
(
a
.
u
.
)
Time(s)
(b)


V
th
shift
(simulated)
65nm Intel
processor
V
DD
=0.9
V
DD
=1.3
V
DD
=1.1
10
3
10
4
10
5
0.1
1
n~0.13,
0.21,0.33
Device 1
Device 2
Device 3
A
V
t
h

(
a
.
u
.
)
Symbols: 65nm data
Lines: RD model
Time (s)
(a)


139
ly predicts the recovery under DVS, whereas RD model predicts a
very low degradation when operated under lower V
DD
, resulting in
aging overestimation. Further, the gate delay and circuit delay
shifts may turn certain paths into critical paths, resulting in timing
violations. Therefore, it is essential to include NBTI in the aged
timing analysis to guarantee circuit lifetime. TD model based aging
analysis realizes realistic failure rate in digital circuits avoiding
overly pessimistic prediction from RD model.
This work leverages trapping/detrapping based compact mod-
els for transistor degradation into the VLSI simulation flow at
the system level, under device to device and supply voltage var-
iations. The main contributions of this work include:
1. Modeling of NBTI degradation based on trapping/detrapping
mechanism and incorporating the technology dependence into
the model.
2. Aging prediction under variations at device level and supply
voltage using TD model; recovery present in DVS operation
is correctly captured avoiding the pessimistic aging prediction.
3. Comprehensive validation with 65nm statistical device data
under long term NBTI stress (200ks) and multiple supply
voltages in DVS operation.
4. Aging aware timing analysis to capture path delay shifts and
timing violations in sequential circuits; RD model significant-
ly overestimates aging rate compared to TD model.
Section 2 presents the trapping/detrapping based V
th
shift models
with dependence on technology and statistical parameters. Section
3 illustrates the statistical aging analysis and timing violations in
VLSI circuits. The aging analysis is further demonstrated in
ISCAS89 benchmark circuits using 45nm Nangate standard cell
library. Section 4 concludes this paper.
2. AGING MODELS
The fundamental step in circuit aging prediction is to estimate V
th

shift in PMOS device under NBTI. In this section, measurement
setup to collect statistical aging data and trapping/detrapping based
NBTI model is presented. Further, aging dependence on technology
parameters such as V
DD
and t
ox
is incorporated into the modeling
framework. The TD model accuracy under device level and supply
voltage variations are demonstrated in this section.
2.1 Measurement Setup
To analyze the variability and develop an efficient aging prediction,
the first step is to collect statistical device data. The measurement
time plays a crucial role in NBTI test since even a small measure-
ment time leads to large recovery, resulting in inaccurate aging data.
Hence, obtaining degradation data by removing stress from all
devices leads to a large measurement error. One solution is to
place multiple DUTs on a chip so that stress periods and threshold
voltage measurements can be conducted in parallel. This approach
is very expensive and needs a larger area. Contrary to parallel
measurement method, a parallelize stress period in a pipeline man-
ner is implemented and V
th
measurements for the DUTs are con-
ducted in this work [8]. Figure 2 shows the microphotograph of test
chip implemented in 65nm and 11 metal layer CMOS process.
Total area of the test chip is 489x332um
2
and 128 PMOS devices
of four different aspect ratios are implemented as DUTs. Aging
measurements are conducted when all the devices are stressed at a
voltage of 1.8V and a temperature of 125
o
C for 200ks. These
measurements are required in order to analyze device to device
statistical aging behavior in long term. Further, measurements are
conducted when all the devices are stressed under multiple V
DD
to
realize the aging in DVS operation. Figure 3 presents the test struc-
ture and measurement principle implemented in our work. Except
for the device in measurement, all other devices are stressed and V
th

is measured using constant current method with a resolution of
0.2mV.
2.2 Trapping/Detrapping based BTI Model
Several works show the role of charge trapping/detrapping mech-
anism in NBTI degradation as opposed to classical RD theory [9].
Clear steps showing single trapping or detrapping events have
been reported through discrete V
th
shifts [10]. Figure 4 presents
our measurement in a device under pure recovery. Discrete V
th

shifts due to trapping/detrapping are observed, confirming the
necessity of TD based NBTI models for reliable aging prediction.
According to the trapping theory, threshold voltage of a device
increases when a trap captures a charge carrier, resulting in reduc-
tion of drain current. If the device is not under stress, only local-
ized traps with energy close to Fermi level can change their states,
originating into low frequency noise. If NBTI stress leads to a
high electric field, the trap energy is modulated and might capture
charge carriers. The occupation probability of the trap to be cap-
tured is independent of stress time [10]. The probability of trap-
ping depends on capture time constant and that of detrapping
depends on emission time constant. The gradual change in num-
ber of traps occupied results in the time evolution of V
th
shift.
The primary assumptions in the modeling framework are (1) the
number of traps are Poisson distributed, (2) time constants are uni-
formly distributed on log scale and (3) trap energy distribution is
assumed to be U shaped (key to include V
DD
, t
ox
dependence) [11].
The average number of traps that capture charge carriers during the
stress phase is given by:
Figure 2. Microphotograph of a 65nm test chip
(489x332um
2
) with a 11 metal layer CMOS; 128 PMOS
transistors of 4 different aspect ratios.

Figure 3. Measurement setup: (a) All devices are under
stress except the device under measurement (b) Vth meas-
urement using constant current method

(a)

(b)

l
o
g
(
I
d
s
)
Vth
Icc
Vgs
|Vth|
VSS
VSS
VSTR
VDD
VCC
140

( ) . ( , , )
c e
n t N p t t t =
(1)
where N is the Poisson parameter for the trap distribution and p is
the capture probability, which is a function of time constants and
stress time. Integrating the number of occupied traps over a period
of time gives the V
th
shift:

( ) log 1
th
V A Ct | A = + + (

(2)
where is proportional to the number of available traps per device.
The variation in V
th
shift is mainly due to and parameters, A and
C are relatively constant. The V
th
shift from TD model follows
logarithmic relation with time, different from power law time de-
pendence in RD model.
To validate trapping theory, RD and TD model parameters are ex-
tracted from stress data<20ks. The parameter in TD model has
/ of 26% and A, C exhibit /<1%, indicating that is the main
variation parameter from device to device. Figure 5 shows the dis-
tribution of V
th
prediction using extracted parameters from 20ks
and measured V
th
after stress time of 200ks. The logarithmic mod-
el from TD theory correctly estimates mean and variance of V
th

shift, since the degradation is less sensitive to model parameter
variation compared to RD model. Hence, trapping/detrapping based
BTI model accurately predicts variability in aging due to random-
ness in number of traps per device.
2.3 Technology Dependence
As the CMOS technology scales down and gate oxide thickness
becomes lesser than 4nm, NBTI is the dominant aging mechanism
which limits the device and circuit lifetime [5]. Therefore, it is
essential to incorporate technology parameters in aging models
besides time evolution. In this subsection, we derive a closed form
solution for V
th
dependence on V
DD
and t
ox
, facilitating the design-
ers to estimate aging for various technology nodes.
The threshold voltage shift as a function of trap and Fermi energy
levels is given by [11]:

( )
( )/
( )
' log 1
1 e
T F
Ec
T T
th E E kT
Ev
f E dE
V N A Ct

| |
A = + + (
|

+
\ .
}
(3)
where f(E
T
) is trap energy distribution, E
T
and E
F
are trap and Fer-
mi energy levels respectively. The trap energy changes as function
of electric field (E
ox
) and the difference E
T
-E
F
decreases under high
E
ox
, resulting in a larger V
th
shift. Trap energy is assumed to follow
bucket shape (close to U shape) i.e., energy of traps is 0 from E
F
to
kT, and linearly increases beyond kT. Since V
gs
~-V
DD
in digital
circuits, performing integration of Eq. (3) leads to:
( )
0
1
~ .exp exp log 1
.
dd
th
ox
E BV
V K A Ct
kT kT t
| | | |
A + + (
| |
\ .
\ .
(4)
The compact model in Eq. (4) predicts the dependence of device
degradation as a function of V
DD
, t
ox
and temperature (T). Figure 6
presents the validation of our TD model in a 65nm PMOS device
stressed under different voltages, showing that our model well
matches with experimental data [12]. Further, Eq. (4) is essential to
predict aging under multiple V
DD
in DVS operation.
2.4 Dynamic Voltage Scaling
Todays digital circuit operation is compounded with Dynamic
Voltage Scaling (DVS) as shown in Figure 1b. Since the aging rate
is a strong function of V
DD
, it is important to predict the degrada-
tion under sequence of V
DD
s present in DVS operation. The TD
based BTI model is capable of correctly predicting the degradation
under multiple supply voltages. Our model is evaluated with 65nm
device measurement under DVS in this subsection.
Figure 7 illustrates two cases where a PMOS device is stressed
under different voltages sequentially. When a digital circuit is op-
erated at V
DD
of 1.5V and followed by a higher V
DD
of 1.8V, the
number of occupied traps increases and V
th
shift increases exponen-
tially as shown in Figure 7a. This behavior is captured by both TD
and RD models. When V
DD
is changed back to 1.5V from 1.8V, the
degradation undergoes recovery due to traps emitting the charge
carriers (Figure 7a). This recovery behavior is captured by TD
model and RD model predicts a very low degradation at a lower
V
DD
using the boundary condition [3]. The recovery is significant
when operated under a much lower V
DD
of 1.2V as presented in
Figure 7b, which results in a large prediction error in the long term.
Figure 4. V
th
shift under pure recovery; discrete V
th
shifts
observed due to trapping/detrapping events [8].

Figure 5. TD model well predicts the long term aging
variability compared to RD model.

0.0 0.5 1.0 1.5 2.0
0
20
40
60

65nm data for 200k seconds
TD model prediction
from data<20k seconds
RD model prediction
from data<20k seconds
C
o
u
n
t
s
AV
th
(a.u.)


Figure 6: Prediction of V
th
shift using TD model in 65nm
PMOS device under different supply voltages [12].

10
3
10
4
10
5
0.1
1
Model
V
gs
=-1.8V
V
gs
=-1.7V
V
gs
=-1.6V
A
V
t
h
(
a
.
u
.
)
Time(s)
65nm PMOS
T=105
o
C


141
The recovery behavior is also governed by the log(t) function simi-
lar to the stress phase. Further, it is important to determine if the
device undergoes stress or recovery when V
DD
is changed. Given
the values of V
th0
, stress time (t) experienced by the device and
the supply voltage to be operated (V
DD
), we can predict if the deg-
radation increases or recovers. Based on our BTI model, we can
predict the V
th
shift assuming that the device is stressed under V
DD

from time t=0 to t=t. Using Eq. (4), the degradation increases fur-
ther if:

( )
0
0 1
'
.exp exp log 1 '
.
dd
th
ox
E BV
V K A Ct
kT kT t
| | | |
A < + + (
| |
\ .
\ .
(5)
else, the degradation recovers until it reaches equilibrium. This
condition at the boundary of supply voltage change allows the ac-
curate aging prediction under DVS operation.
3. STATISTICAL AGING ANALYSIS IN
VLSI CIRCUITS
The V
th
model based on trapping/detrapping proposed in previous
section is crucial in statistical aging analysis at the circuit level. In
this section, an experimental setup for failure analysis and timing
violations in sequential circuits due to NBTI is demonstrated. Fur-
ther, failure rate in digital circuits is comprehensively estimated
under device to device and supply voltage variations.
3.1 Experimental Setup
Figure 8 presents the experimental setup and static timing analysis
framework implemented in this work. NBTI aging aware library is
used to calculate the delay shift in digital gates. Our framework
uses delay information under different V
DD
in standard library and
predicts the delay shift due to change in V
th
using a simple gate
delay model, capable of handling the inherent stack effect present
in NOR gates.
For a given digital circuit, we begin with the standard Static Timing
Analysis (STA) which generates fresh timing report with timing
information of all the paths in the circuit, without considering the
NBTI effect. Logic analysis is performed on the circuit to obtain
switching activities () in case of AC stress and node voltages in
case of static stress. Based on the stress conditions, PMOS V
th
shift
and gate delay shifts are computed using delay information from
standard cell library under different slew rates and load capacitanc-
es. Aged timing report is then obtained by updating gate and path
delay shifts in fresh timing report, thus identifying the paths violat-
ing timing requirements. Our framework is general and can be ex-
tended to other aging mechanisms such as Positive Bias Tempera-
ture Instability (PBTI). The library used in the entire aging analysis
is 45nm Nangate standard cell library.
3.2 Long Term Prediction
Device level aging due to trapping/detrapping exhibits large varia-
tions due to randomness in number of available traps. The variabil-
ity at (t>0) is also a function of transistor sizing similar to process
induced variations (t=0) [13]. Aging variability increases with
downsizing the devices and hence, it becomes significant with
CMOS technology scaling. Further, it is important to understand
and estimate the translation of device aging to circuit level degrada-
tion. Figure 9 presents the long term prediction of PMOS V
th
shift
and ring oscillator frequency shift under device level variations.
Though, the device level prediction has a large variation, circuit
aging exhibits moderate variation due to the average effect of mul-
tiple transistors in the circuit. Standard deviation () of V
th
shift is
Figure 7. Threshold voltage shift under different V
DD
; RD
model overestimates compared to TD model.

0
1x10
4
2x10
4
0.00
0.25
0.50
0.75
1.00
0
1x10
4
2x10
4
0.00
0.25
0.50
0.75
1.00
65nm data
TD model
RD model
A
V
t
h
(
a
.
u
.
)
Time(s)


V
DD
=1.5, 1.8, 1.5V
(b)

65nm data
TD model
RD model
Time(s)
(a)
V
DD
=1.8, 1.2, 1.5V


Figure 8. NBTI based statistical timing analysis framework.

C
i
r
c
u
i
t

N
e
t
l
i
s
t
STA Fresh Timing
Logic
Analysis
Aging Model of
Vth (RD or TD)

Gate Delay
Shift
Standard cell
library
Aged Timing
& Failure
Analysis
Figure 9. Long term prediction under device level variations
of PMOS V
th
shift and delay change in an 11 stage RO.

0.05
0.1
10
5
10
6
10
7
40
80

A
V
t
h
(
V
)
o/=22%
Longterm prediction under TD model
parameter variations


A
D
e
l
a
y
(
p
s
)
Time(s)
o/=5%
Delay shift in 11 stage RO


Figure 10. Distribution of read noise margin in a 6T SRAM
cell under RD and TD models.

0.14 0.15 0.16 0.17
0
20
40
60
80
100
C
o
u
n
t
s
RNM (V)
RD Model


TD Model
45nm 6T SRAM cell
142

22% of mean () from our measurement data. When these V
th
shifts
are induced randomly into an 11 stage Ring Oscillator (RO),
/~5% is observed. Figure 10 presents the distribution of Read
Noise Margin (RNM) in a 6T SRAM cell predicted with extrapola-
tion using the model coefficients from the short term data. Lower
bound from RD model is much less compared to TD, model indi-
cating the accurate prediction from the trapping theory.
3.3 Timing Violations in Sequential Circuits
NBTI induced gate and circuit delay shifts imply that many circuit
paths that are not critical in the design stage may turn critical over
time, causing timing violations during the operation [14]. Figure 11
demonstrates a timing violation in an inverter chain between two
sequential elements. The output of the inverter chain passes
through FF2 at the rising edge of clock signal. The path delay of
the inverter chain should be less than required data arrival time.
NBTI results in increase of path delay along the inverter chain,
causing a setup violation and subsequent logic failure. A setup
violation in this circuit is illustrated in Table I. When operated at a
clock period of 340ps, the required data arrival time of this circuit
is 285ps. The accumulated path delay is 280.6ps, resulting in a
setup slack of +4.4ps. Positive setup slack indicates that the data
reaches earlier than the required data arrival time and a setup viola-
tion do not occur. For a stress time of 2x10
6
s, gate and path delays
shift due to NBTI. Since NBTI only shifts low to high delay of a
signal, only the rising edges are shifted resulting in asymmetric
aging. This is considered in our analysis as only delays of Inv1,
Inv3 and Inv5 (rising transitions) are shifted, as highlighted in Ta-
ble I. Power law time dependence in RD model overestimates aging
compared to log(t) dependence in TD model. Path delay for the
circuit increases to 286.7ps and 284.5ps under RD and TD models
respectively. When RD model is used, the accumulated delay along
the logic path is higher than the required data arrival time, causing
a setup violation with negative slack of -1.7ps. TD model predicts a
positive slack of 0.5ps and the circuit does not encounter any tim-
ing violation. Similar to shift in the logic path delay, NBTI induces
delay in the clock buffer. If the clock travels slowly between two
sequential elements and data is allowed to penetrate through both
the registers in the same clock tick, a hold violation occurs. Since
modern circuits are well designed to handle clock skew, only NBTI
induced setup violations are estimated in this work. Our framework
can be further extended to evaluate violations due to aging in se-
quential benchmark circuits.
The proposed trapping/detrapping based BTI models and asymmet-
ric aging analysis are implemented in ISCAS89 benchmark circuits
and PrimeTime, a commercial STA tool is used in our work. A
45nm Nangate open cell library characterized by Predictive Tech-
nology Model (PTM) is used in our analysis. V
th
is predicted us-
ing both TD and RD models based on the stress conditions. Gate
delay shifts are computed by aging aware library and aged timing
report is generated. Figure 12a shows the distribution in shift in
path delays when the proposed framework is implemented in s5378
circuit with 179 paths. TD based aging model exhibits a narrow
distribution with of 19ps and of 18.9 ps. RD model predicts a
wider distribution of delay shifts and overestimates aging by 50%
as illustrated in Figure 12a. The observed behavior is due to fast
changing degradation with time in RD model compared to gradual
change in TD model due to logarithmic time dependence.
The variations present at the device level are also significant to
determine the failure rate due to aging. The predicted V
th
varia-
tions using the extracted model parameters (Figure 5) are used to
calculate the variations in gate delay shifts. Aged timing under
variations is obtained and number of violations can be predicted
under both models. Figure 12b presents the distribution of the
number of setup violations in s5378 circuit due to model parameter
variations in both TD and RD models. When the circuit is under
static operation for 2x10
6
s, RD model has a wider distribution and
predicts approximately 5X more number of violations compared to
TD model. The main variation parameter in RD model is the time
exponent (n) and a small change in n value leads to huge difference
in aging prediction. Hence, the exponential sensitivity of predicted
V
th
to time exponent leads to a wide failure distribution. On the
other hand, the main variation parameter in the TD model is and
Figure 11. Schematic example of an inverter chain between
two sequential elements.

CLK
FF1
CLK
FF2

Inv1 Inv2 Inv3 Inv4 Inv5 Inv6
Figure 12. Distribution of (a) path delays and (b) viola-
tions under variations in TD and RD model parameters
in s5378 circuit.

0 20 40 60 80 100 120
0
10
20
30
40
50
s5378 circuit
Time=2x10
6
s
TD model
C
o
u
n
t
s
ADelay(ps)
TD model
s5378 circuit
50%


RD model RD model
(b)
~5X
(a)
0 10 20 30 40
0
10
20
30
40
50
60
Setup Violations


Table 1. Fresh and aged analysis of circuit in Figure 11

Gates
in
path
Fresh
Tr.
type
Aged (2x10
6
s)
Gate
delay
(ps)
Path
delay
(ps)
RD
Model
Gate
delay
(ps)
TD
Model
Gate
Delay
(ps)
RD
Model
Path
delay
(ps)
TD
Model
Path
delay
(ps)
DFF1 192.6 192.6 Fall 192.6 192.6 192.6 192.6
Inv1 20.7 213.3 Rise 22.8 22 215.4 214.6
Inv2 11.1 224.4 Fall 11.1 11.1 226.5 225.7
Inv3 17.2 241.6 Rise 19.2 18.5 245.7 244.2
Inv4 11 252.6 Fall 11 11 256.7 255.2
Inv5 17.1 269.7 Rise 19.1 18.4 275.8 273.6
Inv6 10.9 280.6 Fall 10.9 10.9 286.7 284.5
Required data
arrival time
285
Required data
arrival time
285 285
Setup slack +4.4 Setup slack -1.7 0.5

143
Table II: Setup Violations under RD and TD models in
ISCAS89 sequential circuits.
Design
Clock
period
(ns)
t=1year t=5years t=10years
RD TD RD TD RD TD
S27 0.48 1 1 1 1 1 1
S382 0.9 1 1 2 2 2 2
S386 0.87 2 2 3 2 3 2
S444 1.05 1 1 1 1 1 1
S510 0.95 1 1 2 1 2 1
S641 2.76 3 3 4 4 4 4
S820 2.3 4 1 4 1 4 1
S832 2.4 4 3 4 3 4 3

V
th
has a linear dependence on it. Hence, the predicted degrada-
tion has a narrow distribution under variations due to less sensitivi-
ty of aging model to . Trapping/detrapping based NBTI model
correctly predicts the critical paths under aging, avoiding the need
to protect large number of paths during the design stage. Compre-
hensive demonstration of our aging analysis is demonstrated in
different ISCAS89 benchmark circuits and summarized in Table II.
Initially the clock period is fixed for each design such that all the
paths in the circuit meet the timing requirements. Aging analysis is
conducted by setting all the inputs to 0V and operation times of 1, 5
and 10 years. As the number of gates and inputs in the circuit in-
crease, there is an increase in the number of setup violations. Also,
RD model overestimates the failure due to aging in majority of the
circuits. Therefore, TD based BTI model correctly predicts the
degradation and guide designers to correctly predict the guard band
under device to device variations.
3.4 Supply Voltage Variations
Along with variations at the device level, supply voltage variations
also impact aging due to strong dependence of NBTI to V
DD
. When
a circuit is operated under multiple V
DD
, the degradation can be
computed by using the boundary condition in Eq. (5). Figure 13
presents the absolute shift in frequency of an 11 stage RO when
operated under two supply voltages of 1.8V and 1.5V for random
operation times. RD model does not predict any recovery when
operated under a lower V
DD
and hence, predicts monotonic RO
frequency shift. However, TD model correctly predicts the recov-
ery under a lower V
DD
and estimates the upper bound of degrada-
tion accurately. The situation is more complex when the circuit is
operated under more than 2 supply voltages, which can be handled
by TD aging model using the appropriate boundary condition.
Therefore, our proposed aging prediction under trapping/detrapping
theory facilitates robust long term device and circuit reliability
prediction under V
DD
variations inherent in DVS operation.
4. CONCLUSION
This paper presents statistical aging prediction under NBTI due to
variations at device level and operation conditions. Degradation
models based on trapping/detrapping mechanism are presented and
the proposed model well predicts the device to device aging varia-
bility, which is not captured by conventional RD based BTI model.
In this work, technology parameters are incorporated into TD mod-
els and thereby, accurately predicting the aging when operated
under multiple V
DD
present in DVS operation. Further, statistical
timing analysis is performed under device level variations and
demonstrated in ISCAS89 benchmark circuits; RD model overes-
timates aging and TD model correctly predicts aging under device
to device and supply voltage variations. With solid verification
with measured 65nm device data, the proposed statistical aging
helps designers to accurately monitor and manage circuit lifetime.
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Figure 13. Prediction of delay shift in an 11 stage RO un-
der sequence of V
DD
=1.8V and 1.5V; RD model overesti-
mates circuit aging.

0.0 2.0x10
3
4.0x10
3
6.0x10
3
0.25
0.50
0.75
1.00
1.8V
1.5V
TD model
A
F
r
e
q
u
e
n
c
y
(
a
.
u
.
)
Time(s)
RD model
11 stage RO
20%


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