INTRODUCTION: With the increase in silicon densities, it is becoming feasible for multiple compression systems to be implemented in parallel onto a single chip. A 32-BITsystem with distributed memory architecture is based on haing multiple data compression and decompression engines wor!ing independently on different data at the same time. This data is stored in memory distributed to each processor. The ob"ectie of the pro"ect is to design a lossless parallel data compression system which operates in high- speed to achiee high compression rate. By using #arallel architecture of compressors, the data compression rates are significantly improed. Also inherent scalability of parallel architecture is possible. The main parts of the system are the two $matchpro based data compressors in parallel and the control bloc!s proiding control signals for the %ata compressors, allowing appropriate control of the routing of data into and from the system. &ach %ata compressor can process four bytes of data into and from a bloc! of data eery cloc! cycle. The data entering the system needs to be cloc!ed in at a rate of 'n bytes eery cloc! cycle, where n is the number of compressors in the system. This is to ensure that ade(uate data is present for all compressors to process rather than being in an idle state. COMPONENTS REQUIRED: )ompressor %ecompressor )ontrol Array )omparator )A* )omparator #rocessing +nit. REQUIRMENTS: *odel,im ,imulator ,tudent &dition -.%/ or -&0I/12 programming. Lossless Daa Co!"#ess$o% Me&o's: Sa$s$(al Me&o's: ,tatistical *odeling of lossless data compression system is based on assigning alues to eents depending on their probability. The higher the alue, the higher the probability. D$($o%a#) Me&o's: %ictionary *ethods try to replace a symbol or group of symbols by a dictionary location code. Both software and hardware based dictionary models achiee good throughput and competitie compression. In our pro"ect we use *Ma(&P#o Al+o#$&! . *Ma(&P#o al+o#$&!: $match algorithm is a parallel lossless data compression. This algorithm uses a fi3ed width dictionary . It wor!s by ta!ing a '-byte word and trying to match this word with past data. This past data is stored in a dictionary, which is constructed from a content addressable memory. Initially )A* sets all words in dictionary to 4ero. If the input word is matched,then corresponding address is send to output. If input word is mismatch then miss is registered and a single miss bit of 567 is transmitted followed by the tuple itself. At the beginning of each compression, the dictionary si4e is reset to 4ero. A partial match occurs when at least any tow of the characters in the incoming tuple match e3actly with a dictionary entry. The use of partial matching improes the compression ratio when compared with allowing only ' byte matches. BLOC, DIAGRAM:
International Conference on Electrical, Electronics and Civil Engineering (ICEECE'2011) Pattaya Dec. 2011 Hardware Implementation of PCI Interface Using Verilog & FPGA