Professional Documents
Culture Documents
Code
MAT 616
ENG 601
- EEE 699
Course Title
Computational Techniques
0
2
0
0
4
0
2
2
20
Total credits
26
University Elective
Course
Code
Course Title
University Elective
Total credits
03
Programme Core
Course
EEE
EEE
EEE
EEE
EEE
ECE
EEE
EEE
Code
587
588
589
591
596
508
575
646
Course Title
Physics and Modeling of Semiconductor Devices
Digital IC Design
Analog IC Design
VLSI Digital Signal Processing
ASIC Design
VLSI Testing and Testability
Total credits
L
3
3
3
3
3
3
3
3
T
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0
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P
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2
2
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2
2
29
C
3
4
4
3
4
3
4
4
Programme Elective
Credits to be taken: 15
Cour
se
EEE
EEE
EEE
EEE
EEE
EEE
EEE
ECE
EEE
Cod
e
597
599
601
602
603
605
590
--604
ECE
ECE
614
615
Course Title
3
3
3
3
3
3
3
3
3
3
3
3
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3
3
3
3
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3
3
3
3
3
3
3
3
3
0
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0
0
3
3
Credit Summary
University Core
University Elective
Programme Core Offered
Programme E lective
Total credits Offered (UC+UE+PC+PE)
Minimum Qualifying credits
UC University Core
PC Programme Core
PE Programme Elective
UE University Elective
26
3
29
15
73
73
Cour Cod
se e
Course Title
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7
36
8
36
9
37
0
37
1
37
2
EEE
609
Computational Techniques
Course
Offered
by
SAS
EEE
587
EEE
588
EEE
589
Analog IC Design
EEE
590
IC Technology
EEE
591
ECE
ENG
EEE
---601
699
EEE
46
23
3
38
3
38
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38
5
38
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7
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8
38
Syllabu
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Version
1.00
AC approv
al
Date
18AC
SENSE
1.10
18AC
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29AC
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16AC
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SENSE
SSH
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ASIC Design
SENSE
1.10
EEE
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SENSE
1.00
16AC
PE
EEE
598
SENSE
1.10
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PE
EEE
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SENSE
1.00
16AC
PE
ECE
508
SENSE
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29AC
PC
EEE
601
SENSE
1.00
16AC
PE
EEE
602
SENSE
1.00
16AC
PE
18AC
29AC
15AC
18AC
Course Ty
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UC
PC
PC
UC
PC
PC
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39
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39
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39
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26
1
EEE
603
SENSE
1.00
16AC
PE
EEE
604
SENSE
1.10
18AC
PE
EEE
605
SENSE
1.00
16AC
PE
EEE
XXX
SENSE
1.00
16AC
PE
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SENSE
SENSE
SENSE
SENSE
SENSE
1.00
1.00
1.00
1.10
1.00
16AC
16AC
16AC
18AC
16AC
PE
PE
PE
PE
PE
3
3
0
0
0
0
3
3
SENSE
SENSE
1.00
1.00
16AC
16AC
PE
PE
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3 1.00
16AC
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1.00
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3 1.0
3 1.0
29AC
29AC
PE
PE
1.0
1.0
3 1.0
29AC
PE
1.0
3 1.0
29AC
PE
1.0
EEE
EEE
ECE
ECE
ECE
604
ECE
ECE
EEE
EEE
501
598
EEE
ECE
540
----
ECE
----
ECE
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EEE587
Version No.
Prerequisite
Objectives:
3 0 0
This course will help the students acquire a deep understanding of modeling FET
devices which plays an important role in fabrication of integrated circuits. This is
likely the most advanced course on this topic that students will encounter. It
should prepare students for research or development of device technology or
digital or analog circuits for many years to come.
Expected
A student completing this course will be able to
Outcome:
Explain and apply the semiconductor concepts of drift, diffusion, donors
and acceptors, majority and minority carriers, excess carriers, low level
injection, minority carrier lifetime, quasi-neutrality, and quasi-statics;
Explain the underlying physics and principles of operation of p-n junction
diodes, Metal-Oxide-Semiconductor (MOS) capacitors, Bipolar Junction
Transistors (BJTs), and MOS Field Effect Transistors (MOSFETs), and
describe and apply simple large signal circuit models for these devices
which include charge storage elements.
Unit I
Semiconductor Physics
10 Hrs
Metals, insulator, semiconductors, intrinsic and extrinsic semiconductors, direct and indirect
band gap, free carrier densities, Fermi distribution, density of states, Boltzmann statistics,
thermal equilibrium, current flow mechanisms, drift current, diffusion current, mobility, band
gap narrowing, resistance, generation and recombination, lifetime, internal electro-static fields
and potentials, Poissons equation, continuity equations, drift-diffusion equations
Unit II
PN-Junction Diodes:
8
Thermal equilibrium physics, energy band diagrams, space charge layers, internal electro-static
fields and potentials, reverse biased diode physics, junction capacitance, wide and narrow
diodes, transient behavior, transit time, diffusion capacitance, small signal model.
Unit III
Bipolar Transistors:
8
Basic theory and operation, heavy doping effects, double diffused transistors, Ebers-Moll
model, low forward bias, junction and diffusion capacitance, transit times, parasitic, smallsignal models, Early effect, saturation and inverse operation, breakdown mechanisms, punchthrough.
Unit IV
MOS Transistors
10
MOS capacitor, accumulation, depletion, strong inversion, threshold voltage, contact potential,
oxide and interface charges, body effect, drain current, saturation voltage, gate work function,
channel mobility, sub-threshold conduction, short channel effects, effective channel length,
effects of channel length and width on threshold voltage, Compact models for MOSFET and
their implementation in SPICE. Level 1, 2 and 3, MOS model parameters in SPICE.
UNIT V
UDSM Transistor Design Issues
6
Short channel and ultra short channel effects; Effect tox , effect of high k and low k dielectrics
on the gate leakage and Source drain leakage; tunneling effects; different gate structures in
UDSM - impact and reliability challenges in UDSM
Text Books :
1.Y.P. Tsividis, The MOS Transistor, McGraw-Hill, international edition ed., 1988.
5
2.S.M.Sze, Semiconductor Devices Physics and Technology, John Wiley & Sons Inc, (2/e). .
REFERENCE BOOKS
1. Getreu, Modeling the bipolar transistor, New York, NY: Elselvier, 1978.
2. D. Roulston, Bipolar Semiconductor Devices, McGraw Hill, 1990.
3. N. Arora, MOSFET Models for VLSI Circuit Simulation, Springer-Verlag, 1993.
4. P. Antognetti and G. Massobrio, Semiconductor Device Modeling with SPICE, McGrawHill, 1988.
5. D.W. Greve, Field Effect Devices and Applications, Prentice Hall Series in Electronics and VLSI,
1998
6. M. S. Tyagi, Introduction to Semiconductor Materials and Devices, Wiley India Edition 2010
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
ECEXXX
Version No.
Prerequisite
Objectives:
DIGITAL IC DESIGN
3 0 2
1.0
This course is preparatory for study in the field of Very Large Scale
Integrated (VLSI) digital circuits and engineering practice. The course
focuses upon the systematic analysis and design of basic digital integrated
circuits in CMOS technology. Problem solving and creative circuit design
techniques are emphasized throughout. This course provides the foundation
for subsequent courses in the design of digital integrated circuits and
systems. Basic principles, methodologies, and ad-hoc analysis and design
techniques are emphasized.
Expected
After completion of this course the students will be familiar with modern
Outcome:
VLSI circuits and will be able to design most of them.
Unit I
Introduction
Issues in Digital IC Design. Quality Metrics of a Digital Design. MOS Transistor.
Manufacturing CMOS Integrated Circuits. Design Rules. Layouts.
Unit II
The CMOS inverter
Static CMOS Inverter: Static and Dynamic Behavior Practices of
CMOS Inverter. Components of Energy and Power: Switching, ShortCircuit and Leakage Components. Technology scaling and its impact
on the inverter metrics.
Unit III
CMOS Combinational Logic Circuit Design
Static CMOS Design: Complementary CMOS, Ratioed Logic, Pass Transistor Logic.
Dynamic CMOS Design: Dynamic Logic Design Considerations. Speed and Power
Dissipation of Dynamic logic, Signal integrity issues, Cascading Dynamic gates.
Unit IV
CMOS Sequential Logic Circuit Design
Introduction. Static Latches and Registers. Dynamic Latches and Registers. Pulse Based
Registers. Sense Amplifier based registers. Latch vs. Register- based pipelines structures.
UNIT V
Interconnect and Timing Issues
Interconnects: Resistive, Capacitive and Inductive Parasitics. Computation of R, L and C
for given inter-connects. Buffer Chains.
Timing Issues: Timing classification of digital systems. Synchronous Design - Origins of
Clock Skew/Jitter and Impact on Performance. Clock Distribution Techniques. Latch based
clocking. Synchronizers and Arbiters. Clock Synthesis and Synchronization using a PhaseLocked Loop
Text Books :
1. Jan M.Rabaey, Anantha Chadrakasan, Borivoje Nikolic, Digital Integrated Circuits:
A Design Perspective, (2/e), PHI.2005
2. Neil.H.E.Weste, David Harris, Ayan Banerjee, CMOS VLSI Design: A Circuit and
Systems Perspective, (4/e). Addison Wesley, 2011
REFERENCE BOOKS
1. David A Hodges, Horace G Jackson and Resve A Saleh, Analysis and Design of
Digital Integrated Circuits in Deep Submicron Technology TMH.2005
2. Sung-Mo Kang, Yusuf Leblebicii, CMOS Digital Integrated Circuits- Analysis and
Design McGraw-Hill International Edition.
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
ECEXXX
Version No.
Expected
Outcome:
0 0 2
1.0
At the completion of the design project, students should be able to:
1. Understand how transistor behaves as a device and describe transistor
operations in digital domain.
2. Design an interface circuitry for different IC technologies.
3. Understand and apply low-power high-performance design techniques
in their design.
4. Do a layout of a small IC block, including the routing.
5. Understand and apply advanced layout techniques to minimize the
effects of parasitics, especially on high-speed circuitries.
List of Experiments
1. Introduction to Cadence environment; setup Linux environment; create schematic
and symbol, introduction to netlist, technology library and other stuff.
2. DC and transient analysis of CMOS inverter .
3. Layout, DRC, LVS, RCX and post-layout simulation of CMOS Inverter
4. Design and Analysis of NAND, NOR and complex gates
5. Layout of CMOS NAND, NOR and complex gates
6. Design and characterization of Latches and Flip-flops
7. Design of Memory cells
8. Design of I/O PADs
9. Modeling of interconnects
10. Mini-project
Mode of Evaluation
ECEXXX
Version No.
Prerequisite
Objectives:
ANALOG IC DESIGN
1.1
Problem of Lock acquisition, Phase Detector, Basic PLL and its dynamics, Chargepump PLL, Non-ideal effects in PLL: PFD/CL non idealities, Jitter, Delay Locked
Loop, Applications.
Text Books :
1. Behzad Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2000.
2. Gray, Hurst, Lewis, and Meyer: Analysis and Design of Analog Integrated Circuits, (4/e), John
Wiley and Sons
REFERENCE BOOKS
1. Phillip E. Allen and Douglas R. Holberg, CMOS Analog Circuit Design, (Second Edition)
Oxford University Press, February 2002.
2. David Johns and Ken Martin, Analog Integrated Circuit Design, John Wiley & Sons,
Inc., 1997
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
ECEXXX
Version No.
0 0 2
1.0
Mode of Evaluation
Continuous Assignments/ Quiz/ Project work, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
10
ECEXXX
Version No.
Prerequisite
Objectives:
0 0
1.0
ECEXXX
Version No.
Prerequisite
Objectives:
3 0 0
1.0
Digital Design, Basic graph theory concepts, Data structure
This course reviews the major components of the modern computer-aided
circuit design flow. An important motivation for the course is to explore the
directions in which computer-aided circuit design evolves as it copes with
the challenges brought about by the increased complexity of deep submicron
silicon technology
Expected
After the completion this course the students shall be able to
Outcome:
Understand the techniques and algorithms for physical and logiclevel design automation.
Explain the optimization methods contemplate various performances
such as silicon area, timing, power consumption, and crosstalk.
Unit I
Introduction
Y Chart, Physical design top-down flow. Design styles: Full Custom, Standard Cell, Gate
Arrays, Field Programmable Gate Arrays, Sea of Gates
Logic Synthesis and Technology Mapping:
Unit II
Computer-aided synthesis and optimization, Introduction to Combinational logic synthesis
Binary decision diagrams (BDD): Principles, Implementations and Construction,
Manipulation, Variable ordering. Two-level and multi-level logic optimizations. Sequential
logic optimization.
Unit III
Algorithms for Physical Design Automation:
Partitioning: Problem formulation, Group Migration Algorithms Kernighan-Lin, FiducciaMattheyses algorithm, Performance driven Partitioning.
Floor Planning: Problem Formulation, Integer Programming, Rectangular dualization, Simulated
Annealing based floorplanning
Placement: Breuers algorithm, Cluster Growth approach, Sequence pair technique.
Pin Assignment: General pin assignment, Channel pin assignment.
Routing: Global routing: Problem formulation, Maze routing, Line Probe algorithms, Weighted
Steiner tree approach.
Detailed routing: Problem formulation, Two layer channel routing Left Edge algorithm, Dogleg
router, Net Merge channel router, Three-layer channel routing HVH, VHV router. Introduction to
switch box routing.
Over the Cell Routing: Two layer Over-the-cell routers.
Clock routing: Clocking schemes, Exact Zero skew algorithm.
Power and Ground routing.
Unit IV
Compaction
Problem formulation, One dimensional Compaction Constraint graph based, Virtual Grid based
compaction, Two dimensional compaction, Hierarchical compaction.
12
Timing Analysis
UNIT V
Static and Dynamic timing analysis for single and multiple path data flows. Compensation
techniques. Critical path delays. Back annotation
Text Books :
1. Naveed Sherwani , Algorithms for VLSI Physical design automation, 3e, Springer
International edition, 2005.
2. Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, 1st edition,
McGraw-Hill, 1994
3. H. Yosuff and S.M. Sait, VLSI Physical Design Automation Theory and
Practice, McGraw Hill publication, 1995.
REFERENCE BOOKS
1. Sung Kyu Lim, Practical Problems in VLSI Physical Design Automation
Springer. 2008
2. Michael John Sebastian Smith, Application Specific Integrated Circuits, Pearson
Education Asia, 2001.
3. Sabih. H. Gerez , Algorithms for VLSI design Automation, John Wiley & Sons
Ltd.,2004.
4. M.Sarrafzadeh, C.K.Wong, An introduction to VLSI physical design ,McGrawHill international editions,1996.
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
13
ECEXXX
3 0 0
1.0
Expected
Outcome:
ECEXXX
3 0 0
Expected
Outcome:
1.0
Digital IC Design
To gain a sound knowledge of the sources of power consumption in UDSM
CMOS designs and to develop a broad insight into the methods used to
confront the low power issue from lower level (circuit level) to higher levels
(system level) of abstraction
Layout design of Area efficiency, Single row Vs double row, Inrush current and current
latency
Register Transfer Level Optimization
Unit IV
Low power clock, Interconnect and layout designs, Reducing power consumption in
memory cells, Clock gating, Deglitching for low power, Bus Encoding techniques
Logic Level and Circuit Level Optimization
Unit V
Theoretical background Calculation of Steady state probability, Transition probability,
Conditional probability, Transition density; Estimation and optimization of Switching
activity, Power cost computation model, Transistor variable re-ordering for power
reduction, Low power library cell design (GDI).
Unit VI
Low Power Design of Sub-Modules
Circuit techniques for reducing power consumption in Adders, Multipliers. Synthesis of
FSM for low power, Retiming sequential circuits for low power
Unit VII
Architecture and partitioning for power gating, power controller design for the USB OTG, Issues in
designing portable power controllers, clocks and resets, Packaging IP for reuse with power internet
UNIT VIII Software Level Power Optimization
Text Books
1. Kaushik Roy, Sharat Prasad, Low Power CMOS VLSI circuit design, John Wiley and
Sons Inc., 2000.
2. Soudris, Dimitrios, Christrian Pignet, Goutis, Costas, Designing CMOS circuits for
low power, Springer International, 2004.
REFERENCE BOOKS
1. G.K.Yeap, Farid N.Najm, Low Power VLSI design and technology, World Scientific
Publishing, 1996.
2. A.P.Chandrakasan, R.W.Broderson, Low Power Digital VLSI Design, IEEE Press,
1998.
3. Gary K.Yeap, Practical Low Power Digital VLSI Design, Kluwer Academic Press,
1998.
4. Jan M.Rabaey, Massoud Pedram, Low power Design methodologies, Kluwer
Academic Press, 1996
5. Michael Keating, David Flynn Low Power Methodology Manual for System-On-Chip
Design Springer Publication 2007
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
16
ECEXXX
3 0 0
1.0
Analog IC Design.
This course covers many aspects of the design of dynamic analog circuits
and analog-digital interface electronics in CMOS technology. It covers the
specification and design of analog-to-digital and digital-analog converters
and several sample converter implementations in detail
Expected
Outcome:
17
weighted, Thermometer DAC, Current steering DAC Current cell design in current steering DAC,
Charge Scaling DAC, Pipeline DAC
Oversampling Converter
Unit V
Benefits of Oversampling, Oversampling with Noise Shaping, Signal and Noise Transfer
Functions, First and Second Order Delta-Sigma Converters. Signal Dependent Stability of
Describing Function Method. Introduction to Continuous-time Delta Sigma Modulators,
time-scaling, inherent anti-aliasing property, Excess Loop Delay, Time-constant changes,
Influence of Op amp nonidealities. Effect of OP Amp nonidealities - finite gain bandwidth,
Effect of ADC and DAC nonidealities. Dynamic Element Matching - Dynamic Element
Matching by Data Weighted Averaging, Effect of Clock jitter
Text Books
1. M. Gustavsson, J. Wikner, and N. Tan, CMOS Data Converters for
Communication Kluwer Academic Publishers, 2000.
2. Behzad Razavi, Principles of Data Conversion System Design Wiley-IEEE Press,
1994.
3. David A.Johns, Ken Martin, Analog Integrated Circuit Design John Wiley & Sons
Inc. 1997
REFERENCE BOOKS
1. R.Jacob Baker, CMOS Mixed Signal Circuit Design, IEEE Press Series on
Microelectronic Systems, 2002.
2. Andrzej Handkiewicz, Mixed Signal Systems A Guide to CMOS Circuit Design,
IEEE Press Series on Microelectronic Systems, 2003.
3. Van de Plsddvhr, Rudy J, CMOS Integrated A/D and D/A Converters BS
Publications,2005
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
18
ECEXXX
Version No.
Prerequisite
Objectives:
Expected
Outcome:
IC TECHNOLOGY
3 0 0
1.0
This course introduces students to the fundamentals of VLSI manufacturing
processes and technology.
After the completion of this course, Students will be able to
Understand physics of the Crystal growth, wafer fabrication and basic
properties of silicon wafers.
Learning lithography techniques and concepts of wafer exposure
system, types of resists etc.
Understand Concepts of thermal oxidation and Si/SiO2 interface and
its quality measurements.
Learn concepts of thin film deposition including chemical Vapor
Deposition and Physical vapor deposition.
Understand back-end technology to define contacts, interconnect,
gates, source and drain, and measurements techniques to insure
quality of designs.
Understand MOS and Bipolar Process Integration.
Unit I
Introduction
Introduction to Semiconductor Manufacturing and fabrication. Physics of the Crystal
growth, wafer fabrication and basic properties of silicon wafers
Unit II
Lithography, Thermal Oxidation of Silicon:
The Photolithographic Process, Etching Techniques, Photomask Fabrication, Exposure
Systems, Exposure sources, The Oxidation Process, Modeling Oxidation, Masking
Properties of Silicon Dioxide, Technology of Oxidation, Si-SiO2 Interface.
Unit III
Diffusion, Ion Implantation, Film Deposition:
The Diffusion Process , Mathematical Model for Diffusion, Constant- ,The Diffusion
Coefficient , Successive Diffusions, Diffusion Systems, Implantation Technology,
Mathematical Model for Ion Implantation, Selective Implantation, Channeling, Lattice
Damage and Annealing, Shallow Implantations, Chemical Vapor Deposition, Physical
Vapor Deposition, Epitaxy
Interconnections and Contacts, Packaging and Yield
Unit IV
Metal Interconnections and Contact Technology, Diffused Interconnections, Polysilicon
19
Text Books
1. J. Plummer, Michael D. Deal and Peter B. Griffin, Silicon VLSI Technology,
fundamentals, practice and modeling Pearson Education, 2009.
2. Richard C. Jaeger , Introduction to Microelectronic Fabrication, Second Edition
REFERENCE BOOKS
1. C.Y. Chang and S. M. Sze, ULSI Technology, McGraw Hill 1996
2. S.K. Ghandhi, VLSI Fabrication Principles, Wiley. 2nd edition 1994
3. Stanley wolf , Silicon Processing for VLSI era, volume 4, Deep sub-micron
process technology Lattice Press.1990
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
20
ECEXXX
3 0 0
1.0
Objectives:
To have the students develop a fundamental understanding of the basic principles used in
the packaging of modern electronics so that when faced with a packaging issue they can
recognize the various methods available and perform the tradeoffs necessary to select the
appropriate/optimum packaging solution for the applications
Expected
Outcome:
An undergraduate degree in a scientific or engineering area, including familiarity with computeraided design and engineering analysis methods for electronic circuits and systems
Solder Edge Conductors. Thin Film Conductors on Face-of-a-Cube - A flip-chip bonded to faces of the
stack - Blind Castellation Interconnection. Area Interconnection between Stacked MCMs: Arrays of
Contacts between MCMs with through hole vias. Limitations of 3D Packaging Technology.
Signal Integrity Problems in On-Chip Interconnects
Unit IV
Interconnect Figures of Merit. Interconnect Parasitics Extraction. Signal Integrity Analysis. Design Solutions for
Signal Integrity
IC Interconnect Synthesis
Unit V
Overview & static topology optimization- Global routing Topology: finding high quality sink permutation, tree
construction for a given permutation- optimization of multisource nets: linear time computation of ARD(T) under
Elmore delay, repeater insertion algorithm- timing driven Maze routing. Noise in interconnect modelingcrosstalk effects in digital circuits- noise detection in logic circuits.- techniques for avoiding interconnect noise
REFERENCE BOOKS
1. John H. Lau,Ball Grid Array Technology.
2. John H. Lau, Flip Chip Technologies
3. Said F. Al-Sarawi and Derek Abbott, 3D VLSI Packaging
(http://www.eleceng.adelaide.edu.au/personal/alsarawi/packaging_www.html)
4. Chung-KuanCheng, John Lillis, Shen Lin, Interconnect Analysis and Synthesis,
John Wiley & sons, 2000.
Technology
Norman Chang,
5. Jeffrey.A.Davis, James
D.Meindl. Interconnect techniques and design for Giga scale
integration, Kluwer academic publishers, 2003.
6. Ban P. Wong, Nano-CMOS circuit and physical design John Wiley. 2005.
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
22
ECEXXX
RFIC DESIGN
Version No.
Prerequisite
Objectives:
1.0
Analog Integrated Circuit Design and knowledge on Electromagnetic theory
This course is for IC designers who would like to become familiar with the
design of integrated radio front-end circuits.
Expected
Outcome:
Unit I
Introduction to RF & Wireless Technology
Complexity, design and applications. Choice of Technology. Basic concepts in RF Design:
Nonlinearly and Time Variance, intersymbol Interference, random processes and Noise.
Definitions of sensitivity and dynamic range, conversion Gains and Distortion
Unit II
Passive and Active Devices:
Passive devices: monolithic capacitors, resistors, inductors, RLC networks, transmission
lines, lumped and distributed resonators, impedance matching networks, transformers, and
baluns. Active devices: MOSFET operations (in both long channel and deep submicron
regimes), practical limitations, and other various silicon transistors and technologies
(Si/SiGe Bipolar, SOI, etc.).
Unit III
Analog & Digital Modulation for RF Circuits:
Comparison of various techniques for power efficiency. Coherent and Non coherent
defection. Mobile RF Communication systems and basics of Multiple Access techniques.
Receiver and Transmitter Architectures and Testing heterodyne, Homodyne, Image-reject,
Direct-IF and sub-sampled receivers. Direct Conversion and two steps transmitters. BJT
and MOSFET behavior at RF frequencies. Modeling of the transistors and SPICE models.
Noise performance and limitation of devices. Integrated Parasitic elements at high
frequencies and their monolithic implementation
Unit IV
Low Noise Amplifiers design in various technologies, Design of Mixers at GHz frequency
range. Various Mixers, their working and implementations, Oscillators: Basic topologies
VCO and definition of phase noise. Noise-Power trade-off. Resonatorless VCO design.
23
1.0
This course will cover various aspects of semiconductor memories, including
basic operation principles, device design considerations, device scaling,
device fabrication, addressing, and readout circuits and testing memories
Expected
Outcome:
General Fault Modeling Read Disturb Fault Model Precharge Faults False Write
Through Data Retention Faults Decoder Faults. Zero/one Pattern Exhaustive Test
Patterns Walking, Matching and Galloping Pseudo Random Pattern CAM pattern
Unit V
Design For Test and BIST
Weak Write Test mode Bit Line Contact Resistance PFET Test Shadow Write and
Shadow Read
REFERENCE BOOKS
1. M.Bushnell, V.Agrawal, Essentials of Electronic Testing for Digital, Memory &
Mixed-Synal VLSI Citcuits, Springer, 1st edition 2nd printing 2005
Text Books :
1. R.Dean Adams, High Performance Memory Testing : Design Principles, Fault
Modeling and Self Test , Springer, 2002.
2. Brent Keeth, R. Jacob Baker, Brian Johnson, Feng Lin, DRAM Circuit Design:
Fundamental and High-Speed Topics, 2E, Wiley - IEEE press December 2007.
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
25
ECEXXX
Version No.
Prerequisite
Objectives:
RECONFIGURABLE ARCHITECTURES
3 0 0
1.0
Knowledge in Graph Algorithms and basics of Computer Architecture.
The objective is to deal with topics, starting from a historical perspective on
early reconfigurable systems, ranging across a wide variety of results and
techniques for reconfigurable models, examining more recent developments
such as optical models and run-time reconfiguration (RTR), and finally
touching on an approach to implementing a dynamically reconfigurable
model.
Expected
Outcome:
Unit I
Introduction to reconfigurable architectures
Principles and issues, examples, R-Mesh at a glance, Important Issues
Unit II
Reconfigurable Mesh:
Reconfigurable Mesh-Two Dimensional R-Mesh, Expressing R-Mesh Algorithms,
Fundamental Algorithmic Techniques-Data movement, Efficiency Acceleration, Neighbor
Localization, Sub-R Mesh Generation, Distance Embedding, Connectivity Embedding,
Function Decomposition.
Unit III
Models of Reconfiguration:
Restricted bus structure, word size, accessing buses, higher dimensions, one-way streets,
More ways of reconfiguration-Reconfigurable Network, Reconfigurable Multiple Bus
Machine, Optical Models, Reconfiguration in FPGAs, How powerful is Reconfiguration
Unit IV
Scalability of Algorithms - for HVR,LR, FR, meshes and Matrix Manipulations, Concepts
on dis-joints, Bus structures including Multiple bus machines, Degrees of scalability, Tradeoffs. Mapping of Higher order meshes, What are the salient difference between PRAMs, ERMBMs, F-RMBM, S-RMBM, B-RMBM and Randomized PRAMS
Unit V
Arithmetic on the Mesh
26
Expected
Outcome:
After the completion of this course the students can be able to:
Understand terminologies for EMI and EMC
Analyze, understand, explain and quantify an EMC problem
Design hardware to achieve the necessary isolation between RF stages
Understand and reduce crosstalk coupling mechanisms
Design a digital power bus to achieve the required noise budget
Learn and understand ESD (electrostatic discharge)
Aware of the different EMC regulations worldwide
Unit I
EMI ENVIRONMENT
Sources of EMI, conducted and radiated EMI, Transient EMI, EMI-EMC Definitions and units of
parameters
Unit II
EMI COUPLING PRINCIPLES:
Conducted, Radiated and Transient Coupling, Common Impedance Ground Coupling, Radiated
Common Mode and Ground Loop Coupling, Radiated Differential Mode Coupling, Near Field
Cable to Cable Coupling, Power Mains and Power Supply Coupling.
Unit III
EMI MEASUREMENTS:
EMI SPECIFICATION / STANDARDS / LIMITS: Units of specifications, Civilian standards
Military standards. EMI Test Instruments/Systems, EMI Test, EMI Shielded Chamber, Open Area
Test Site, TEM Cell Antennas, Conductors Sensors/Injectors/Couplers, Military Test Method and
Procedures, Calibration Procedures
EMI CONTROL TECHNIQUES
Unit IV
27
28
Unit VIII
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
29
ECEXXX
Version No.
Prerequisite
Objectives:
HARDWARE/SOFTWARE CO-DESIGN
3 0 0
1.0
Digital design and Programming and Hardware description languages.
To understand the methodologies related to High level synthesis and Compiler
optimization.
Expected
Outcome:
Unit I
Specification of embedded systems:
Why Co-design? - Comparison of co-design approaches MoCs: State oriented, Activity oriented,
Structure oriented, Data oriented and Heterogeneous Software CFSMs Processor
Characterization.
Unit II
HW/SW Partitioning methodologies:
Principle of hardware/software mapping - Real time scheduling - design specification &
constraints on Embedded systems - Tradeoffs - Partitioning granularity - Kernigan-Lin Algorithm Extended Partitioning - Binary Partitioning: GCLP Algorithm
Unit III
Co-synthesis & Estimation:
Software synthesis Hardware Synthesis - Interface Synthesis Co-synthesis Approaches:
Vulcan, Cosyma, Cosmos, Polis and COOL Estimation: Hardware area, execution timing and
power; Software memory and execution timing.
Co-simulation & Co-verification
Unit IV
Principles of Co-simulation Abstract Level; Detailed Level Co-simulation as Partitioning
support Co-simulation using Ptolemy approach
Text Books:
Felice Balarin, Massimiliano Chiodo, Paolo Giusto, Harry Hsieh, Attila Jurecska, Luciano
30
References :
Peter Marwedel, Embedded System Design, Springer, 2006, ISBN:1402076908.
Russell John Rickford, Bernd Kleinjohann, Design and Analysis of Distributed Embedded
Systems, Springer, 2002, ISBN:1402071566.
Achim Rettberg, Mauro C Zanella, Franz J Rammig, From Specification to Embedded
Systems Application, Springer, 2005, ISBN:0387275576
http://embedded.eecs.berkeley.edu/research/hsc/class.F04/index.html
http://www.tik.ee.ethz.ch/tik/education/lectures/ES/
http://www1.cs.columbia.edu/~sedwards/classes/2004/4840/
1. http://courses.cs.tamu.edu/rabi/cpsc489/resources.shtml
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
ECE614
Version No.
Prerequisite
Objectives:
DSP ARCHITECTURES
3 0 0
1.0
Familiarity with digital filters, matrix algebra, and random signal analysis.
This course on digital signal processing architectures which focuses on the
implementation and design of families of DSP architectures with in-depth
analysis of the relevant algorithms. Students learn the essential advanced topics
in digital signal processing, Internal DSP architectural requirements for a DSP
device, system level hardware design of DSP Architectures and interfacing
peripherals to programmable DSPs.
Expected
Outcome:
Unit I
ARCHITECTURES FOR PROGRAMMABLE DSP DEVICES :
Basic Architectural features, DSP Computational Building Blocks, Bus Architecture and Memory,
Data Addressing Capabilities, Address Generation Unit, Programmability and Program
Execution, Speed Issues, Features for External interfacing.
Unit II
EXECUTION CONTROL & PIPELINING:
Hardware looping, Interrupts, Stacks, Relative Branch support, Pipelining and Performance,
Pipeline Depth, Interlocking, Branching effects, Interrupt effects, Pipeline Programming models
Unit III
ADSP ARCHITECTURES AND SYNTHESIS :
Top Down approach to DSP LSI, Circuit Synthesis, High Performance Data conversion
Techniques, LSI Algorithms and Architectures, Hierarchical Design of Processor Arrays, Systolic
Arrays, Stack Filters, Wave-front Array Processors, Floating Point DSP processors, Systolic
Processors for Image Processing; Standard digital signal processors, Application Specific ICs for
DSP, ADSP system architectures, Standard DSP architecture, Ideal DSP architectures, Equalizers,
Adaptive Equalizers, Multiprocessors and multi-computers, Systolic and Wave front arrays,
Shared memory architectures. Mapping of DSP algorithms onto hardware, Implementation based
31
References :
1. B.VenkataRamani and M. Bhaskar, Digital Signal Processors, Architecture, Programming
and Applications, TMH, 2004.
2. Jonatham Stein, Digital Signal Processing, John Wiley, 2005.
3. Bayoumi, MA, VLSI Design Methodology for DSP Architectures, Klumer, 1994.
4. Sung-Yuan Kung, Robert E.Owen, J.Gerg Nash, VLSI Signal Processing Vol.1, Vol.II.
IEEE Press. 1986
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
ECEXXX
Version No.
Prerequisite
Objectives:
3 0 0
1.0
Design of digital systems.
With the VLSI, Field Programmable Gate Array (FPGA), and System On a
Chip(SOC) technologies, transistors are getting smaller and smaller thus
today's digital systems are more complex than ever before. This increased
complexity leads to more cross-talk noise and other sources of transient errors
( like single event upset) during normal operation. Traditional off-line testing
strategies cannot guarantee detection of these transient faults. The critical
applications that are relying on faster operations need built-in fault-tolerant
and self-checking mechanisms to assure reliable and dependable operation.
Expected
Outcome:
Course Topics
1. Introduction to fault tolerance and failsafe design techniques. Goals
& applications of fault tolerance. Classification of faults.
Reconfiguration Techniques using SRAM based Field
Programmable Gate Arrays (FPGAS).
2. Modeling of the faults in hardware and software. Test vector
generation, and Built In Self Test (BIST) concepts. Test data
32
References :
B.W. Johnson, "Design and analysis of Fault Book Tolerant Digital Systems ", Addison-Wesley
Publishing Company, 1989.
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
33
ECEXXX
Version No.
Prerequisite
Objectives:
3 0 0
1.0
Design and Analysis of Algorithms, C or C++ programming languages and object
oriented design, Matrix Algebra, Fourier Transforms.
To develop theoretical and algorithmic principles
behind the acquisition,
display, manipulation and processing of digital images. To explore the methods
used to digitize, transfer, display, organize, process and compare digital images
and image sequences. To analyze technique in image compression.
Expected
Outcome:
34
Text Books:
1. Steven W. Smith , Digital Signal Processing: A Practical Guide for Engineers and
Scientists , Elsevier, 2003
2. Anil.K.Jain, Fundamentals of Digital Image Processing PHI, 1995.
3. R.C.Gonzalez and R.E. Woods, Digital Image Processing, PHI, 2002.
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
ECEXXX
Version No.
Prerequisite
Objectives:
3 0 0
1.0
Semiconductor device physics, Quantum Physics, Nanoelectronics
Single Electronics and the devices are emerging as the futuristic devices
for ultra-dense digital IC designs and their understanding and modeling
techniques are required to be learnt. Students will be exposed to this
emerging field.
Expected
Outcome:
The students exposed this area of Single Electron and a few electron devices,
their characteristics and advanced concepts of such devices for futuristic
Integrated devices will enable students to get opportunities in the advanced
technology R & D groups in India and Abroad. Unique opportunity exist for
such students.
Unit I
Basic Single Electron devices:
Single Electron Box, Single Electron transistor, Single-Electron Traps, Single-Electron
Turnstile and Pumps, SET Oscillators, Comparison Between FET and SET Circuit Designs
Unit II
Unit III
Unit IV
Text Books:
1. Shunri Oda and David Ferry, Silicon Nanoelectronics,CRC Press, Taylor & Francis
Group, 2006.
2. D. V. Averin, Y. V. Nazarov, Macroscopic quantum tunneling of charge and cotunneling, in H. Grabert, M. H. Devoret (eds.), Single charge tunneling: Coulomb
blockade phenomena in nanostructures, Plenum Press and NATO Scientific Affairs
Division, New York and London, 1992, pp. 217-247.
3. Christoph Wasshuber, Computational Single-Electronics", 2001, Springer-Verlag
References Book :
1.
2.
3.
36
ECEXXX
Version No.
Prerequisite
Objectives:
1.0
Expected
Outcome:
3 0 0
Unit I
Introduction To MEMS:
Historical background of Micro Electro Mechanical Systems, role of MEMS in improved
efficiency, Smart materials and structures, materials-processing, synthesis, Multifunctional
polymers.
Unit II
Material Processing and Device Fabrication:
Lithography, Ion Implantation, Etching, Wafer bonding, Integrated processes, Bulk silicon micro
machining, surface micro machining, CVD oxide process,
Unit III
Micro Sensors and Micro actuators:
Micromechanical components springs, bearings, gears and connectors, High temperature
sensors, Capacitive pressure sensor, bulk micro-machined accelerometer, Surface micro machined
micro spectrometer
Applications of MEMS:
Unit IV
Blood Pressure Monitoring Transducers, Disposable Blood Pressure Monitoring Transducers. MEMS
devices Infusion pumps, Kidney dialysis, Respirators, Active noise and vibration control, Intelligent
37
structures, micro robots, Smart structures for aircraft, automotive requirements, automobile, Satellite,
Buildings and Manufacturing systems
Text Books:
1. Tai-Ran Hsu, MEMS & Microsystem, Design and Manufacture, McGraw Hill, 2002
References Book :
1. Julian W.Gardner, Vijay. K.Varadhan, Osama O.Awadelkahn (2001), MicroSensors,
MEMS and Smart Devices, Wiley Publishers
2. Gregory T.A.Kovacs (1995), Micromachined Transducers Source Book, McGraw Hill
Publishers ISBN : 0-07-116462-6
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
ECEXXX
Version No.
Prerequisite
Objectives:
NANOELECTRONICS
3 0 0
1.0
Physics and modeling of Semiconductor Device
Nanoelectronics is the next transition in the device and integrated circuit
technologies which are necessitated due to the need for several 10s to
100s of THz device requirements for various demands for speeds and
drastic reduction of power requirements
Expected
Outcome:
39
ECEXXX
Version No.
Prerequisite
Objectives:
3 0 0
1.0
To provide an overview on the present state design technology for System-OnChip
Expected
Outcome:
Unit I
INTRODUCTION:
Architecture of the present-day SoC - Design issues of SoC- Hardwar-Software Codesign Core
Libraries EDA Tools
Unit II
DESIGN METHODOLOGY FOR LOGIC CORES:
SoC Design Flow guidelines for design reuse Design process for soft and firm cores
Design process for hard cores System Integration
Unit III
DESIGN METHODOLOGY FOR MEMORY AND ANALOG
CORES:
Embedded memories design methodology for embedded memories Specification of analog
circuits High speed circuits
DESIGN VALIDATION:
Unit IV
Core-Level validation Core Interface verification - SoC design validation
Unit V
CORE AND SoC DESIGN EXAMPLES:
Microprocessor Cores Core Integration and On-chip bus Examples of SoC
40
Text Books:
Rochit Rajsuman, System-on-a-Chip: Design and Test, Artech House, 2000
References Book :
1. Steve Furber, ARM System-on-Chip Architecture, 2nd ed, Addison-Wesley Professional,
2000
2. Ricardo Reis & Jochen A.G. Jess, Design of System on a Chip : Devices & Components,
Kluwer, 2004
3. Laung-Terng Wang, Charles E. Stroud, Nur A. Touba, System-on-Chip Test Architectures,
Morgan Kaufmann, 2007
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
ECEXXX
Version No.
Prerequisite
Objectives:
COMPUTATIONAL TECHNIQUES
3 1 0
1.0
By the end of the course, students will have a broad understanding of the various
notions used in computational complexity theory to classify computational
problems as hard or easy to solve. They will become familiar with the important
complexity classes, how they are related to each other, typical problems in those
classes. They will be familiar with Finite difference methods and probability
theory and random process
Expected
Outcome:
evaluation algorithms, average running time, tractable, intractable, graph coloring problem
Probability, Stochastic and Random Processes:
Unit IV
Deterministic and probabilistic function, Probabilistic space, Joint probability, conditional
probability, Bernoulli Trails, Bayes Theorem, Entropy, M.S.E., Normal Random variables, Central
Limit Theorem, Stochastic Processes, Markovian Processes, Stationary and Non-stationary
processes, Time variant and Time invariant signals, Ergodic processes, Covariance, Correlation,
Auto & cross correlations, Power Spectrum
Unit V
Finite Difference Method:
Ordinary differential equations of second order finite difference methods, Finite difference
methods. Forelliptic equations, Diffusion equation explicit method Von-Neumann stability
condition, CrankNikolson Implicit method. Wave equationexplicit method, CFL stability
condition
Text Books:
1. J.P. Trembley and R. Manohar, Discrete Mathematical Structures with Applications to
Computer Science, Tata McGraw Hill 13th reprint (2001).
2. Edward A. Bender & S. Gill Williamson Mathematics for Algorithm and Systems Analysis,
Dover (2005) ISBN 0-486-44250-0
3. S. Lipschutz and M. Lipson, Discrete Mathematics, TMH, 2 nd Edition (2000).
4. Murray R. Spiegal, Theory and problems of Statistics Schaums series,TMH,.1999
References Book :
1. J A Bondy and U S R Murthy, Graph Theory with Applications, Elsevier Publishing
Co., Inc., New York, 1976.
2. Lipschutz, Seymour, Schaum's Outline of Theory and Problems of Set Theory and
Related Topics, McGraw-Hill Companies, July 1998
3. Liu "Elements of Discrete Mathematics" McGraw Hill.
4. Richard Johnsonbaugh, Discrete Mathematics, 5th Edition, Pearson Education (2001).
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
42
ECEXXX
Version No.
Prerequisite
Objectives:
3 0 2
1.0
This course covers the advanced design and analysis of digital circuits with
HDL. The primary goal is to provide in depth understanding of logic and system
design. The course enables students to apply their knowledge for the design of
advanced digital hardware systems with help of FPGA tools.
Expected
Outcome:
Types of Programmable Logic Devices- PLA & PAL- FPGA Generic Architecture.
Timing Analysis and Power analysis
Soft-core Processor- System Design Examples using FPGAs Traffic light Controller, Real Time Clock
- Interfacing using FPGA: VGA, Keyboard, LCD
Text Books:
1. S.Ramachandran, Digital VLSI System Design: A Design Manual for implementation of
Projects on FPGAs and ASICs Using Verilog Springer Publication,2007
2. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis Prentice Hall,
Second Edition,2003
References:
Charles H Roth, Jr Digital Systems design using VHDL, Thomson Books/Cole
Wayne Wolf , FPGA Based System Design, Prentices Hall Modern Semiconductor Design Serie
Mark Balch, Complete Digital design A Comprehensive Guide to Digital Electronics and
Computer system Architecture, Mc Graw Hill, 2003
Stephen Brown & Zvonko Vranesic, Digital Logic Design with VerilogHDL TATA Mc Graw Hill
Ltd. 2nd Edition 2007
ALTERA Quartus II Handbook Ver10.0
CAT- I & II, Assignments/ Quiz, Term End Examination
Mode of Evaluation
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
ECEXXX
Version No.
Prerequisite
Objectives:
0 0 2
1.0
This course is introduced for designing digital logic using Verilog HDL. It
provides the students with advanced concepts of design such as: interfacing
between systems on different clocks, FPGA interface with external devices and
performance analysis of the system
List of Experiments:
1. Design and Implementation of Combinational Circuits
a. Basic Gates Using Dataflow, Structural, Behavioral
Modeling
b. Half-Adder and Full-Adder using structural Modeling
c. Half-Subtractor and Full-Subtractor using dataflow
44
modeling.
d. Decoder and Encoder using case, casex and casez
statements.
e. Code Convertor & parity generators using reduction
operators
f. Multiplexer and De-multiplexer using nested if-else
construct
2. Design and Implementation of Sequential Circuits
a. Flip-Flop using behavioral modeling
b. Serial-In Serial Out, Parallel-In Parallel Out Shift register
using Structural Modeling
c. Serial-In Parallel Out, Parallel-In Serial Out Shift register
using behavior level Modeling
d. Ring Counter and Johnson counter using behavior level
Modeling and structural level modeling.
3. Design and Implementation of FSM
a. Sequence detector using FSM
b. Traffic Light Controller using FSM
c. Vending machine problem using FSM
4. FPGA Interfacing using Quartus-II
a. Displaying given string (Using LCD Interface )
b. Displaying given string on LCD (Using Keyboard Interface)
5. System Design using SOPC and NIOS-II
a. Real time video display on Monitor ( Using camera
interface)
b. RGB to Gray Scale Conversion
EDA Tools:
i.
ALTERA Quartus II,
ii. NIOS-II IDE
iii.
SOPC Builder
Hardware:
ALTERA DE2 Board
Interfaces:
5.1 Megapixel Camera
PS2 Keyboard
LCD Display
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
45
ECEXXX
Version No.
Prerequisite
Objectives:
3 0 0
1.0
The objective of this course is to introduce verification techniques and writing a
scrip to automate a tool
Expected
Outcome:
After the course the students will be familiar with verification methodology of VLSI
circuits and Scripting language for VLSI design automation
Unit I
Introduction:
History and Concepts of PERL, Scalar Data ,Arrays and List Data, Control structures, Hashes,
Basics I/O, Regular Expressions ,Functions, Miscellaneous control structures, Formats , Directory
access , File and Directory manipulation , process management ,System database access , User data
manipulation
Unit II
Tool Command Language:
An Overview of TCL and Tk , Tcl Language syntax ,Variables ,Expressions, Lists , Control flow ,
procedures, Errors and exceptions ,String manipulation , Accessing files , Processes , Managing Tcl
Internals ,History
Unit III
Applications:
Automatic code generation , Report Filtering , Netlist patching , Test Vector Generation ,
Controlling Tools
Verification:
Unit IV
Introduction to Verification , Verification Process-Specification Design Decomposition,
Functional Test Strategies ,Transformation Test Strategies ,Coverage ,Event monitors
and Assertion checkers
Unit V
Verification Techniques
RTL Logic Simulation - Simulation history, Project simulation phases ,operation, optimization
,Random two state simulation methods
RTL Formal Verification Introduction ,Transformation Verification ,Formal Functional
Verification ,Model checking methodology
Verifiable RTL Style
Text Books
1.John K. Ousterhout, Tcl and the Tk Toolkit, Addison-Wesley Publishing Company, Inc.,2011
2. Lionel Bening and Harry Foster,Principles of Verifiable RTL Design, Kluwer Academic
publishers,2001
46
References :
Michael L. Bushnell, Vishwani D. Agrawal, ESSENTIALS OF ELECTRONIC TESTING FOR
DIGITAL, MEMORY AND MIXED-SIGNAL VLSI CIRCUITS:, KAP, 2002
Brent B. Welch and Ken Jones, Practical Programming in Tcl and TK,Pearson education,2003
Larry Wall, Tom Christiansen, John Orwant, Programming PERL, Oreilly Publications, 3rd Edn.,
2000
Randal L, Schwartz Tom Phoenix, Learning PERL, Oreilly Publications, 3rd Edn., 2000
ECEXXX
Version No.
0 0 2
1.0
List of Experiments
1. Automatic code generation
2. Report Filtering
3. Netlist patching ,
4. Test Vector Generation
5. Controling Tools
6. Verifying CRC-8 with generator x8+x2+x+1
7. Verification of Translate Look aside Buffer
8. Self checking environment using random test cases
9. Code coverage based Verification Methodology
10. Predictor Based Verification
Tools required: Linux, Cadence.
Language: Perl and TCL
Mode of Evaluation
Continuous Assignments/ Quiz/ Project work, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
47
ECEXXX
Version No.
Prerequisite
Objectives:
ASIC DESIGN
3 0 2
1.0
Familiarity with digital filters, matrix algebra, and random signal analysis.
To study the issues relating to the design of application-specific integrated circuits
(ASICS) for digital systems.
Expected
After completion of this course
Outcome:
Students will be able to design and synthesize a complex digital functional
block using Verilog HDL.
Students will demonstrate an understanding of how to optimize the
performance, area, and power of a complex digital functional block, and the
tradeoffs between these.
Students will demonstrate an understanding of issues involved in ASIC
design, including technology choice, Timing analysis, tool-flow
Unit I
Introduction:
5
Implementation Strategies for Digital ICs: Custom IC Design, Cell-based Design Methodology.
Array based implementation approaches. Traditional and Physical Compiler based ASIC Flow
Unit II
RTL Coding and Synthesis:
10
Review of Verilog - RTL Coding and RTL Synthesis RTL coding guidelines, Synthesizable coding
style, FSM Coding style.
RTL Synthesis
Partitioning for synthesis - RTL synthesis Flow Synthesis Environment - technology library
basics components of technology library Constraints (delay, area, power) Netlist optimization
Reports interpretation of RTL synthesis Timing and performance driven synthesis.
Unit III
Static Timing Analysis:
10
Overview of timing verification and static timing analysis Elements of Timing Verification Critical path, Multicycle paths, false paths, and timing constraints (such as setup, hold, recovery,
and pulse width). Timing analysis for combinational circuits Timing analysis for sequential
circuits -. Clocking and clock skew optimization
Physical Design:
Unit IV
Partitioning - Objective of partitioning- Kernighan-Lin algorithm Floor Planning - Objective Simulated Annealing based floor planning Placement Goals of placement- Breuers algorithm,
Routing- Goals of routing - Global routing Maze routing, Detailed routing- Problem formulation
- Left Edge Over the Cell Routing - Two layer Over-the-cell routers. Clock routing - Clocking
schemes, Exact Zero skew algorithm, Power and Ground routing, Clock tree synthesis.
High performance Algorithms and Architectures for ASIC
Case Studies : 2D Discrete Cosine Transform and Automatic Quality control scheme for Image
Compression
48
Text Books:
1. M.J.S .Smith, Application Specific Integrated Circuits, Addison Wesley Longman Inc.,
1997.
2. Naveed Sherwani, Algorithms for VLSI Physical design automation, 3e, Springer
International edition, 2005
References :
1. J.Bhaskar, Verilog HDL for synthesis, BS publication , 2004.
2. Himanshu Bhatnagar, Advanced ASIC Chip Synthesis (2/e), Kluwer Academic Publisher,
2002
3. Farzad Nekoogar, Timing Verification of Application-Specific Integrated Circuits Farzad
Nekoogar, Prentice-Hall. 1999
4. Sachin Sapatnekar , "Timing , Kluwer Academic Publishers, 2004, Newyork
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
0 0 2 1
1.1
List of Experiments
Working with VLSI CAD Tools(like Cadence IUC, RTL Compiler, SoC
Encounter, ModelSim etc.)
EDA tools and design kit configuration
Design project organization
HDL examples
Text editing
Design flow steps
Verilog simulation
Digital System Design using Verilog HDL
RTL synthesis
Starting the Design Vision graphical environment
RTL model analysis
Design elaboration
Design environment definition
Design constraint definitions
Design mapping and optimization
49
50
ECE508
3 0 0 3
VLSI TESTING AND TESTABILITY
Version No. 1.0
Prerequisite
Objectives:
Expected
Outcome:
Unit I
Fault Modeling and Test Generation:
5
Importance of Testing. Testing during the VLSI Lifecycle. Challenges in the VLSI Testing: Test
Generation, Fault Models. Levels of Abstraction in VLSI Testing. Historical Review of VLSI
Test Technology. Functional Versus Structural Testing. Levels of Fault Models. Single Stuck-at
Fault. Testability measures: Controllability and Observability. Fault Simulation: Serial, Parallel,
deductive, Concurrent,Fault Sampling. Combinational Test Generations: Random Test
generation, ATPG for Combinational Circuits: D-Algorithm, PODEM. Sequential Circuit Test
Generations: ATPG for single-clock synchronous circuits, Designing a Sequential ATPG,
Untestable Fault Identification.
Unit II
Design For Testability:
10
Design for Testability Basics: Ad Hoc Approach, Structured Approach. Scan Cell Designs. Scan
Architectures. Scan Design Rules. Scan Design Flow. Special-Purpose Scan Designs. RTL
Design for Testability.
Unit III
Logic Built-In Self-Test:
10
BIST Design Rules: Unknown Source Blocking, Re-Timing. Test Pattern Generation:
Exhaustive Testing, Pseudo-Random Testing, Pseudo-Exhaustive Testing, Delay Fault Testing.
Output Response Analysis. Logic BIST Architectures: BIST Architectures for Circuits with and
without Scan Chains, BIST Architectures Using Register Reconfiguration. Fault Coverage
Enhancement: Test Point Insertion, Mixed-Mode BIST, Hybrid BIST
Test Compression and Boundary Testing:
10
Unit IV
Test Stimulus Compression: Code-Based Schemes, Linear-Decompression-Based Schemes. Test
Response Compaction: Space Compaction, Time Compaction, Mixed Time and Space
Compaction, Digital Boundary Scan (IEEE Std. 1149.1).
Unit V
Analog and Mixed-Signal Testing :
10
Analog and Mixed-Signal Circuit Trends. Functional DSP-Based Testing. Static ADC and DAC
Testing Methods. Analog Fault Models. Types of Analog Testing. Analog Fault Simulation.
Introduction to IDDQ Test
Text Books:
1. Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, VLSI TEST PRINCIPLES
AND ARCHITECTURES The Morgan Kaufmann, 2006
2. Michael L. Bushnell, Vishwani D. Agrawal, ESSENTIALS OF ELECTRONIC
TESTING FOR DIGITAL, MEMORY AND MIXED-SIGNAL VLSI CIRCUITS:,
KAP, 2002
References:
1.M. Abramovici, M.A. Breuer and A.D. Friedman, "DIGITAL SYSTEMS AND
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52
ECEXXX
Version No.
Prerequisite
Objectives:
3 0 0
1.0
Physics and Modeling of Semiconductor Devices
The goal of the course is to impart the concepts of the principles of design, analysis,
modeling and optimization of VLSI interconnects.
The main objectives of the course are:
The study of VLSI interconnects design, modeling and optimization.
The study of interconnects parasitic parameters influence on the circuits performance.
Expected
After completion of this course the students will be familiar with modern VLSI
Outcome:
interconnects design, the recent trends of optimization and modelling
Unit I
Introduction:
Moores law, Technological trends, Device and chip scaling, Interconnect scaling, Gate and
interconnect delay, Cross-section of hierarchical scaling, 3-D interconnect view, Device technology
roadmap. Interconnect technology roadmap.
Unit II
Interconnect Delay Modeling:
Typical interconnect structure, Extraction of interconnect parameters, Properties of models,
Interconnect resistance, capacitance, inductance. Extended Miller effect, Alternatives for extraction.
Modeling interconnect drivers, Switch-level RC model, k-factor equations. Network interconnect
mode, effective capacitance modeling, Modeling interconnect wires. General interconnect network,
RC tree.
Unit III
Interconnection Length Prediction :
Rents Rule, Rents parameters. Donaths length estimation model, Average interconnection length.
Wire load models, Technology extrapolation. Performance prediction, BACPAC model.
Interconnect-power, Interconnect -power definition. Activity factors generation, Power estimation
accuracy, Model calibration, Interconnect length distribution, Total dynamic power. Local and global
interconnect, Power breakdown by net types. Interconnect length prediction, Future of interconnect
power, Interconnect power prediction, Interconnect power model.
Inductance of Interconnects
Unit IV
Increasing the effects of inductance, Problems with modeling On-Chip inductance, Inductance basics.
Partial inductance, Partial inductances of basic configurations, Application of partial inductance. Skin
effect and its influence on resistance and inductance, Partial element equivalent circuit (PEEC)
method. Design solutions to counter the effects of inductance.
Unit V
Driving interconnect for circuit speed optimization
Evolution of the speed optimization problem, Speed optimization with ideal interconnect, Logical
effort method: first optimization, Logical effort method: second optimization, Merging the 2
optimizations. Speed optimization with capacitive interconnect, A heuristic for cascaded buffers with
local interconnect capacitance, Speed optimization with resistive interconnect.
Interconnect scaling , The bottom of deep submicron, The future of wires, Bakoglus solution:
Repeaters. Optimal number of repeaters, Upsizing the repeaters, Planning for performance, Power in
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repeated lines. Accurate repeater placement and scaling, Tapered driver andloader for a repeated line.
Heuristic construction. Results of heuristic construction.
Interconnect effort. Logic gates as repeaters, LGR circuit model, LGR delay modeling, Optimal wire
segmenting, Optimal gate scaling, LGR vs. traditional repeater insertion, Integrated LGR with
repeater insertion, Boosters vs. repeaters. Wire sizing, spacing, fat wires. Speed optimization in
RLC lines. Repeater insertion in RLC Lines, Driving RC trees
Unit VI
Crosstalk Noise :
Crosstalk configuration, Critical outcomes of noise, DC noise margins, Dealing with AC noise: noise
sensitivity, noise stability. Static noise analysis, Approximations for peak noise, Capacitive charge
sharing model, Two-pole analysis, Effect of resistances, Peak noise vs. wire length for a fixed stage
delay. Part-way coupling, Multiple aggressors. Delay uncertainty, Aggressor alignment, Victim delay
change because of crosstalk. Delay change curve, DCC and noise waveform, DCC modeling,
Parameter definition of coupling noise on quiet victim and without-noise waveform. Delay
uncertainty calculation, Reasons for high delay uncertainty, Switch factor modeling of delay
uncertainty. Noise-aware static timing analysis, Design approaches to deal with noise, Buffer
insertion for noise
References :
1. C-K. Cheng, J. Lillis, S. Lin, N. H. Chang. Interconnect Analysis and Synthesis. Wiley,
2000
2. M. Celik, L. Pillegi, A. Odabasioglu. IC Interconnect Analysis. Kluwer, 2002
3. J. A. Davis, J. D. Meindl. Interconnect Technology and Design for Gigascale Integration.
Kluwer, 2003
4. F. Moll, M. Roca. Interconnection Noise in VLSI Circuits. Kluwer, 2004.
5. M. Celik, L. Pileggi, A. Odabasioglu. IC Interconnect Analysis. Kluwer, 2002.
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
54
ECEXXX
Version No.
Prerequisite
Objectives:
3 0 0
1.0
Physics and Modeling of Semiconductor Devices
To learn the physics behind high speed semiconductor devices and to study their
characteristics
Expected
Clear understanding of physics and materials involved in high speed devices and
Outcome:
realization of high speed circuits using these devices
Unit I
Silicon Based MOSFET and BJT Circuits for High Speed Operation:
Important Parameters of High Speed Performance of Devices: Transit Time of Charge CarriersJunction Capacitances- ON-Resistances and Their Dependence on the Device Geometry and SizeCarrier Mobility- Doping Concentration and Temperature. Contact Resistance and
Interconnection/Interlayer Capacitances in the Integrated Electronic Circuits. Emitter Coupled
Logic (ECL) and CMOS Logic Circuits with Scaled Down Devices. Silicon on Insulator (SOI)
Wafer Preparation Methods - SOI Based Devices - SOICMOS Circuits for High Speed Low Power
Applications..
Unit II
Materials for High Speed Devices :
Merits of III V Binary and Ternary Compound Semiconductors (GaAs- InP- InGaAs- AlGaAs)
Silicon-Germanium Alloys and Silicon Carbide for High Speed Devices as Compared to
Silicon Based Devices. Dopants and Electrical Properties such as Carrier Mobility- Velocity
Versus Electric Field Characteristics of these Materials, Material and Device Process Technique
with These III-V and IV IV Semiconductors.
Unit III
MISFET- MESFET and III V Semiconductor Devices:
Metal Semiconductor Contacts- Schottky Barrier Diode. Thermionic Emission Model for
Current Transport and Current-Voltage (I-V) Characteristics. Effect of Interface States and
Interfacial Thin Electric Layer on the Schottky Barrier Height and the I-V Characteristics. Pinch
off Voltage and Threshold Voltage of MESFETs. D.C. Characteristics and Analysis of Drain
Current. Velocity Overshoot Effects and the Related Advantages of GaAs- InP and GaN Based
devices for High Speed Operation. Sub Threshold Characteristics- Short Channel Effects and the
Performance of Scaled Down Devices.
High Electron Mobility Transistors (HEMT) & Hetero Junction Bipolar
Transistors
Unit IV
(HBTS)
Hetero-Junction Devices - The Generic Modulation Doped FET(MODFET) Structure for High
Electron Mobility Realization - Principle of Operation and the Unique Features of HEMT.
InGaAs/Inp HEMT Structures. Principle of Operation and the Benefits of Hetero Junction BJT for
High Speed Applications - GaAs and InP Based HBT Device Structure and the Surface
Passivation for Stable High Gain High Frequency Performance - SiGe HBTs and the Concept of
Strained Layer Devices.
Unit V
High Speed Circuits
GaAs Digital Integrated Circuits for High Speed Operation- Direct Coupled Field Effect Transistor
Logic (DCFL)- Schottky Diode FET Logic (SDFL)- Buffered FET Logic(BFL). GaAs
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References :
1. S.M Sze, High Speed Semiconductor Devices Wiley,2008
2. C.Y Chang & F.Kat GaAs High speed devices : Physics Technologies and Circuit
applicationsWilney,N.Y,,1994.
3. H.Beneking High speed semiconductor devices: circuit aspects and fundamental
behaviour Chapman and Hall, London,1994.
4. Michael Shur GaAS Devices and Circuits,Plenum press,NY,1989.
5. N.G Einsprush and R.Weisseman VLSI Electronics: GaAs Microelectronics, Academic
Press,NY, 1985
Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
56
ECEXXX
3 0 0 3
NANOSCALE DEVICES AND CIRCUIT DESIGN
Version No. 1.0
Prerequisite Semiconductor Devices and Technology
Objectives: This course will help the students in acquiring knowledge of fabrication technologies,
device physics/operation, circuit design trends, and issues in nanoscale CMOS and
emerging devices
Expected
Outcome:
After the successful completion of the course, the students will be familiar
with the novel semiconductor devices and circuits
Unit I
INTRODUCTION TO NOVEL MOSFETS:
MOSFET scaling, short channel effects, channel engineering , source/drain engineering, high k
dielectric, copper interconnects , strain engineering, SOI MOSFET, multigate transistors, single
gate, double gate, triple gate, surround gate, quantum effects, volume inversion, mobility, threshold
voltage , inter sub band scattering, multigate technology, mobility, gate stack
Unit II
PHYSICS OF MULTIGATE MOS SYSTEM :
MOS Electrostatics, 1D, 2D MOS Electrostatics, MOSFET Current-Voltage Characteristics CMOS
Technology, Ultimate limits, double gate MOS system, gate voltage effect, semiconductor thickness
effect, asymmetry effect, oxide thickness effect , electron tunnel current, two dimensional
confinement, scattering, mobility
Unit III
NANOWIRE FETS AND TRANSISTORS AT THE MOLECULAR
SCALE:
Silicon nanowire MOSFETs, Evaluvation of I-V characteristics, The I-V characteristics for nondegenerate carrier statistics, The I-V characteristics for degenerate carrier statistics, CNT, Band
structure of CNT, CNT-FET, CNT-TUBFET, CNT-SET, CNT memories, CNT based switches,
Logic Gates, CNT based RF devices, CNT based RTDs, Band structure of graphene, Electronic
conduction in molecules, General model for ballistic nano transistors, MOSFETs with 0D, 1D, and
2D channels, Molecular transistors , Single electron charging, Single electron transistors
RADIATION EFFECTS
Unit IV
Radiation effects in SOI MOSFETs, total ionizing dose effects, single gate SOI, multigate devices,
single event effect, scaling effects
Unit V
CIRCUIT DESIGN USING MULTIGATE DEVICES
Digital circuits, impact of device performance on digital circuits, leakage performance trade off,
multi VT devices and circuits, SRAM design, analog circuit design, trans-conductance, intrinsic
gain, flicker noise, self heating, band gap voltage reference, operational amplifier , comparator
designs, mixed signal, successive approximation DAC, RF circuits
References :
1. J P Colinge, FINFETs and other multi-gate transistors, Springer Series on integrated circuits
and systems, 2008
2. Mark Lundstrom Jing Guo, Nanoscale Transistors: Device Physics, Modeling and Simulation,
Springer, 2006.
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Mode of Evaluation
CAT- I & II, Assignments/ Quiz, Term End Examination
Date of Approval by the Academic Council: 29th Academic council Dt:26-04-2013
58