COURSE CODE: EXPERIMENT NO: 2

COURSE INSTRUCTOR: DATE:

TITLE: MARKS
OBJECTIVE:
PRELAB :
1 /2
2 /3
/ 5
EXPERIMENT RESULT:
Table 2-1 /4
Table 2-2 /1
/ 5
POST LAB:
1 /3
2 /2
3 /3
4 /1
/ 9
CONCLUSION: / 1
INSTRUCTOR COMMENTS: TOTAL
/ 20
UNIVERSITI TENAGA NASIONAL
Dept of Electronics and Communication Engineering
College of Engineering
EEEB141
pn JFET Characteristics
The objectives of this laboratory experiment is to study the characteristics related to pn JFETs
Semester: 2 Academic Year: 2011 / 2012
TIME:
STUDENT NAME: STUDENT ID:
SECTION:

WORKBENCH NO:
GROUP MEMBER: STUDENT ID:
EEEB141 ELECTRONICS DESIGN LAB, Lab 2
1
LAB 2 PN JUNCTION FIELD EFFECT TRANSISTOR (JFET)
CHARACTERISTICS

LEARNING OBJECTIVES
By the end of this experiment, you should be able to:
1. Determine the effect of drain-to-source voltage V
DS
on drain current I
D
and reverse
gate-to-source bias voltage V
GS
.
2. Determine and plot the family of drain characteristics of a pn JFET.
3. Determine and plot a pn JFET transfer curve.


MATERIALS
Transistor: 1 2N3819 (JFET)


EQUIPMENT
Tektronix PS280 DC Power Supply
Fluke 45 Dual Display Multimeter


PRE-LAB ASSIGNMENT

1. Draw the cross section area of an n-channel pn JFET. Label

the source, drain, gate,
and depletion regions.







2. Describe the relationship between the drain current, I
D
and the depletion region
(space-charge region) as the gate to source voltage, V
GS
is varied. Draw the
appropriate figures.
EEEB141 ELECTRONICS DESIGN LAB, Lab 2
2
BACKGROUND

There are two principle types of transistors, which are the bipolar junction transistors (BJTs)
and Field Effect Transistors (FETs). In this experiment however, we will limit the study to
FETs (particularly pn JFETs) and BJTs will be discussed in the next experiments.

A FET is a straight forward device. The basic idea of a FET is to control the charge density
of a channel by means of a bias controlled electric field. To minimize the leakage current of
the input signal, the bias voltage is connected to a contact that is isolated from the channel,
named a gate. Two types of FETs are the Metal-Oxide-Semiconductor FET (MOSFET) and
Junction FET (JFET).

Two general categories of JFETs are the pn JFET and the Metal-Semiconductor FET
(MESFET). pn-JFET utilizes a pn-junction for the gate isolation, while MESFET utilizes
Schottky barrier. Typical transistors have three leads, and in case of JFETs, a voltage on one
lead (called the gate) is used to control a current between two other leads (called drain and
source). The figure below illustrated the circuit symbol of n-channel and p-channel JFET
where G, D and S refers to gate, drain and source, respectively.









n-channel p-channel

IN-LAB ACTIVITIES


Gate Short-Circuited To Source
1. Construct the circuit as shown in Figure 3-1.


Figure 2-1: Gate short-circuited to source circuit

D
G
S
I
D
V
DS
+

-

+

V
GS
-

S
G
D
+

V
GS
-

V
SD
+

-

I
D
EEEB141 ELECTRONICS DESIGN LAB, Lab 2
3
2. Set V
DD
= 0.0V. Note that V
DD
= V
DS
. Measure and record the drain current I
D
for
V
DS
= 0V, and V
GS
= 0V.

3. Increase V
DD
to 1.0V. By using the DMM, measure and record I
D
for V
DS
= 1.0V,
and V
GS
= 0V.

4. Repeat for each value of V
DS
as listed in Table 2-1.

5. Reset V
DD
to zero, and POWER OFF.


Gate Is Reverse-Biased
6. Remove the short circuit between the gate and the source and connect voltage source
V
GG
as shown in Figure 2-2.


Figure 2-2: Reverse-biased gate circuit

7. Set V
GG
= -0.2V (note: V
GG
= V
GS
), at V
DD
= V
DS
= 0V. Measure and record the
drain current I
D
.

8. Maintain V
GG
at -0.2V. Repeat step 7, for each value of V
DS
as listed in Table 2-1.

9. Reset all the voltage sources back to zero.

10. Repeat for each value of V
GS
and V
DS
listed in Table 2-1.

11. Reset all the voltage sources back to zero and POWER OFF.


Transfer Characteristic
12. Set V
DD
= 15V, and V
GG
= -2.5V. Measure and record the drain current I
D
.

13. Repeat step 12 for each value of V
GS
listed in Table 2-2, at V
DD
= 15V.


EEEB141 ELECTRONICS DESIGN LAB, Lab 2
4
RESULTS


V
GS
(V)
0 -0.2 -0.5 -0.8 -1.0 -1.2 -1.5 -1.8 -2.0 -2.5
V
DS
(V) I
D
(mA)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0
12.0
13.0
14.0
15.0

Table 2-1


V
GS
(V) -2.5 -2.0 -1.8 -1.5 -1.2 -1.0 -0.8 -0.5 -0.2 0
I
D
(mA)

Table 2-2
EEEB141 ELECTRONICS DESIGN LAB, Lab 2
5
POST LAB DISCUSSIONS

1. Plot drain characteristics graph (I
D
(mA) versus V
DS
(V)) for this JFET (all V
GS
in one
graph).

2. Describe the characteristic curve by its V
GS
value. Is it what you expected?
















3. Plot a transfer characteristic graph (I
D
(mA) versus V
GS
(V)) for this JFET.
4. Identify V
P
(pinch-off voltage) and I
DSS
(saturation current) in the graph of question 3.
(V
P
= V
GS
, when I
D
= 0mA. I
DSS
= I
D
, when V
GS
= 0V)







STUDENTS CONCLUSION
Free Plain Graph Paper from http://incompetech.com/graphpaper/plain/
Free Plain Graph Paper from http://incompetech.com/graphpaper/plain/