Assignment 2

VLSI beyond Moores law and SoC

Linux commands










- Rayyan Sayeed
1MS12EC098
Variation of Design Metrics
In the field of VLSI circuit, the scaling down or the decrease in size of
the semiconductors has happened roughly at an exponential rate. This
has in turn has resulted in a significant increase in the density of the
circuits on the chip. At the nanometer level, due to the effects of
manufacturing process variations, the design optimization process has
transitioned from the deterministic domain to the stochastic domain,
and the inter-relationships among the specication parameters like
delay, power, reliability, noise and area have become more intricate.
ITRS
The International Technology Roadmap for Semiconductors, known
throughout the world as the ITRS, is the fifteen-year assessment of the
semiconductor industrys future technology requirements. These
future-needs drive present-day strategies for world-wide research and
development among manufacturers research facilities, universities,
and national labs.
Technology Nodes over the past years and Moores Law
We can see the technology nodes over the past years and draw an
inference that the Semiconductor VLSI technology is roughly following
the Moores law. Moores law basically states that the number
of transistors in a dense integrated circuit doubles approximately every
two years. The law is named after Gordon E. Moore, co-founder of the
Intel Corporation.


Year Technology Node
1971 10 m
1974 6 m
1977 3 m
1982 1.5 m
1985 1 m
1989 800 nm
1994 600 nm
1995 350 nm
1997 250 nm
1999 180 nm
2001 130 nm
2004 90 nm
2006 65 nm
2008 45 nm
2010 32 nm
2012 22 nm
2014 14 nm

Using Moores law we can hence predict the technologies for the
coming years and determine the technology node.
2016 10 nm
2018 7 nm
2020 5 nm

5 nm by 2020!!!!
Transistor Count
As the size of the transistor reduces it is quite obvious that we find the
no. of transistors to increase. And yet again Moores law comes into
picture.
So we see that the count of transistors has increased drastically. In
1971 the count had been around 2000 In 2011 the transistor count
increased to 2.6 billion!!!! Although this trend has continued for more
than half a century, Moore's law should be considered
an observation or conjecture and not a physical or natural law. Sources
in 2005 expected it to continue until at least 2015 or 2020. However,
the 2010 update to the International Technology Roadmap for
Semiconductors predicted that growth will slow at the end of
2013, when transistor counts and densities are to double only every
three years.
Chip Size
In a similar manner, extending Moores law to the feature size as well


Frequency trend

Making of Transistors over the past Years

NPN (discrete)
Transistor Fabrication
The first step is the
selection of an n-type
wafer this will act as
the collector of the
device. The wafer must
be heavily doped (N
D
~
10
26
m
-3
) in order to
reduce the series
resistance of the collector. A lightly-doped n-type epitaxial layer is then grown on
the surface to increase the reverse-breakdown voltage at the collector-base
junction, which is reverse biased under normal operation. (The breakdown
voltage of a p-n junction decreases as the doping on either side increases.) Then
processes such as Photo-Lithography, MASKING, and etching are carried out to
fabricate the rest
NMOS Fabrication
A layer of silicon di
oxide (SiO2) typically
1 micrometer thick is
grown all over the
surface of the wafer
to protect the
surface, acts as a
barrier to
the dopant during
processing, and
provides a
generally insulating s
ubstrate on to which other layers may be deposited and patterned. The surface is
now covered with the photo resist which is deposited onto the wafer and spun to
an even distribution of the required thickness. The photo resist layer is then
exposed to ultraviolet light through masking which defines those regions into
which diffusion is to take place together with transistor channels. Assume, for
example, that those areas exposed to UV radiations are polymerized (hardened),
but that the areas required for diffusion are shielded by the mask and remain
unaffected. Thick oxide (SiO2) is grown over all again and is then masked with
photo resist and etched to expose selected areas of the poly silicon gate and the
drain and source areas where connections are to be made. (Contacts cut) The
whole chip then has metal (aluminum) deposited over its surface to a thickness
typically of 1 micro m. This metal layer is then masked and etched to form the
required interconnection pattern.
Multi-Gate Devices
The multiple gates may be controlled by a single gate electrode,
wherein the multiple gate surfaces act electrically as a single gate, or by
independent gate electrodes. A multi-gate device employing
independent gate electrodes is sometimes called a Multiple
Independent Gate Field Effect Transistor (MIGFET).
FinFET
In the technical literature, FinFET is used somewhat generically to
describe any fin-based, multi-
gate transistor architecture
regardless of number of gates.
The distinguishing characteristic
of the FinFET is that the
conducting channel is wrapped
by a thin silicon "fin", which
forms the body of the device.
The thickness of the fin
(measured in the direction from
source to drain) determines the
effective channel length of the device.
Gate-all-around (GAA) FET
Gate-all-around FETs are similar in concept to FinFETs except that the
gate material surrounds the channel region on all sides. Depending on
design, gate-all-around FETs can have two or four effective gates. Gate-
all-around FETs have been successfully built around a silicon nanowire
and etched InGaAs nanowires.
Tri-gate FETs
These transistors employ a single gate
stacked on top of two vertical gates
allowing for essentially three times the
surface area for electrons to travel. Intel
reports that their tri-gate transistors
reduce leakage and consume far
less power than current transistors. This
allows up to 37% higher speed, or power consumption at fewer than
50% of the previous type of transistors used by Intel. Intel was the first
company to announce this technology.







ASIC Design Flow


We can broadly classify the ASIC flow design as FRONT end and BACK
end. The back end process is carried out by the Tool. The front end
process is controlled by the user and the process here can be optimized
greatly.
SPECIFICATION:
Specication is the most important portion of an ASIC design ow.In thi
s step, the features and functionalities of an ASIC chip are dened.
Chip planning is also performed in this step. During this process,
architecture and microarchitecture are derived from
the required features and functionalities.
ARCHITECTURAL DESIGN:
Based on the functional specifications and design goals, the top level,
block level architecture would be design on hierarchy. The
dened architecture must take into consideration all required timing,
voltage, and speed/performance of the design.
Architectural simulations need to be performed on the drafted
architecture to ensure that it meets the required specication.
SYNTHESIS:
Synthesis is actually a process wherein Source code, .synth scripts, and
DESIGN CONSTRAINTS are inputs to the process. And the outputs would
be Reports & Bugs, Design Database, And the Gate level Verilog
Description.
PLACEMENT:
Each block is allocated its respective place in the floor and optimization
is done.
CLOCK TREE SYNTHESIS:
The clock skews the delays that need to be taken care of and all these
tasks are done in clock tree synthesis.
DFT:
Design For testability is the test done on the logic blocks. For example,
the test of flip-flops is done through Muxes. And using scan inserted
net-list files, and tested again if bugs are found.
FLOOR PLANNING & POWER PLANNING:
Basically work for the optimization of the given logic based on the
power consumption and also the position of each block of logic, based
on its interconnection with other blocks of logic.

VLSI beyond Moores Law
Moore's Law makes things useful. By increasing the number of
transistors on integrated circuits to several billions and reducing their
size to mere nanometers, engineers can produce ever-faster
microprocessors that are the same size, or even smaller, than the ones
in today's computers. At the same time, Moore's Law increases
efficiency and reduces costs of production. Moore's Law makes things
useful. By increasing the number of transistors on integrated circuits to
several billions and reducing their size to mere nanometers, engineers
can produce ever-faster microprocessors that are the same size, or
even smaller, than the ones in today's computers. At the same time,
Moore's Law increases efficiency and reduces costs of production.
In addition to this I also read an article which was quite interesting and
seemed very apt for the Beyond Moores Law topic.
Crossbar nanowire chips combine to form tiny CPU for beyond-
Moores-law electronics:
As transistor technology continues its march forward with smaller,
faster components, were getting ever closer to the point at which the
realities of atomic scale will put an end to Moores law unless we
find a way around it. A team of researchers from Harvard and non-
profit research company Mitre have devised a possible solution to the
problem using nanowires as a stand-in for traditional transistors in tiny
processors.
The device created in the lab is by no means a match for modern
computer processors, but it is built on a completely new process. The
chip designed by chemist Charles Lieber and his team uses germanium
core nanowires just 15 nanometers wide. The wires themselves are
coated in silicon and are laid out in parallel on a silicon dioxide
substrate. Embedded in the surface of the chip is a network of
chromium and gold contacts, but these run the opposite way, creating
a crisscross pattern.
Each of the points in the chip where the nanowire crosses the
embedded contacts can act as a programmable transistor node.
Applying voltage to the nanowires toggles them between on and off.
The researchers call this a crossbar array.
Study of ITRS Road map
The objective of the ITRS is to ensure cost-effective advancements in
the performance of the integrated circuit and the advanced products
and applications that employ such devices, thereby continuing the
health and success of this industry. The sponsoring organizations are
the European Semiconductor Industry Association, the Japan
Electronics and Information Technology Industries Association, the
Korean Semiconductor Industry Association, the Taiwan Semiconductor
Industry Association, and the United States Semiconductor Industry
Association.
With the progressive externalization of production tools to the
suppliers of specialized equipment, the need arose for a clear roadmap
to anticipate the evolution of the market and to plan and control the
technological needs of IC production. For several years,
the Semiconductor Industry Association (SIA) gave this responsibility of










coordination to the United States, which led to the creation of an
American style roadmap, the National Technology Roadmap for
Semiconductors (NTRS).
(b) ITRS Table StructureKey Lithography-related Characteristics by Product
Type

Near-term Years Long-term Years


YEAR of Production
200
3
200
4
200
5
200
6
200
7
200
8
200
9
201
0
201
2
201
3
201
5
201
6
201
8
Technology Node
hp90

hp65

hp45

hp32

hp22

DRAM Pitch (nm) 100 90 80 70 65 57 50
45 35 32 25 22 18
MPU/ASIC M1 Pitch (nm) 120 107 95 85 75 67 60 54 42 38 30 27 21
MPU/ASIC Poly Si Pitch (nm) 107 90 80 70 65 57 50

45 35 32 25 22 18
MPU Printed Gate Length (nm) 65 53 45 40 35 32 28

25 20 18 14 13 10
MPU Physical Gate Length (nm) 45 37 32 28 25 22 20

18 14 13 10 9 7


(c) Additional Design Technology Requirements
Year of Production 2003 2004 2005 2006 2007 2008 2009 2012 2015 2018 Driver
Technology Node

hp90

hp65

DRAM Pitch (nm) 100 90 80 70 65 57 50 35 25 18

MPU/ASIC Pitch (nm) 107 90 80 70 65 57 50 35 25 18

MPU Printed Gate Length (nm) 65 53 45 40 35 32 28 20 15 10

MPU Physical Gate Length (nm) 45 37 32 28 25 22 20 14 10 7

SOC new design cycle (months) 12 12 12 12 12 12 11 11 10 9 SOC
SOC logic Mtx per designer-year
(10-person team)
1.9 2.5 3.3 4.3 5.4 7.4 10.6 24.6 73.4 113 SOC
SOC dynamic power reduction
beyond scaling (X)
0 0.1 0.1 0.2 0.2 0.2 0.2 6 4.7 8.1 SOC
SOC standby power reduction
beyond scaling (X)
0.37 1.4 2.4 3.4 5.1 6.4 8.73 18.8 44.4 232 SOC
%Test covered by BIST 20 20 25 30 35 40 45 60 75 90
MPU,
SOC

MtxMillion transistors

Manufacturable solutions exist, and are being optimized
Manufacturable solutions are known
Interim solutions are known
Manufacturable solutions are NOT known
Source: 2003 ITRS, Tables A, B, and 19, 1, 7, 124.



Basic Linux Commands
mkdir
This command is used to create a new directory or simply a new
folder inside the folder of the current path
Syntax: mkdir folder_name
Example: $ mkdir ADLD
cd
This command is basically used to change our working directory.
The directory name specified should have been created already.
Syntax: cd folder_name
Example: cd SIM
cd ~
This is used to go to the root folder directly
cd ..
This command is used to go the parent folder of the current
working directory
vi
vi basically opens the text editor after creating the file specified.
The file will be open for editing once the insert / I key is
pressed.
Syntax: $ vi file_name.extension
Example: $ vi file.v
:q!
Is used to exit the editor without saving the current file.
Command basically works after Escape key is pressed.
:wq!
Is used to write into the file and then quit it. Command basically
works after Escape key is pressed.
:x
executes the file and then quit. Command basically works after
Escape key is pressed.
cp
Command to copy file1 to file2 preserving the mode, ownership
and timestamp.
$ cp -p file1 file2
Copy file1 to file2. if file2 exists prompt for confirmation
before overwriting it.
$ cp -i file1 file2
mv
command to rename file1 to file2. if file2 exists prompt for
confirmation before overwriting it.
$ mv -i file1 file2
$ mv -v will print what is happening during file rename.
ls
This command lists out all the files in the working directory, and
lists the information of the files.
Usage can be made anywhere.
ls a
lists out even the hidden files and folders in the working directory.
cat
The most common use of cat is to read the contents of files, and
cat is often the most convenient command for this purpose.
Syntax: cat file_name
Example: cat file1
cat file1 > file2
the output from cat is written to file2 instead of being displayed
on the monitor screen.
cat >file.extension
This commands creates the file with the extension and also
enables the user to write into it at the same time.
cat file1 file2 >file3
The contents of file1 and file2 will be copied into file3, with the
contents of file2 after file2.
pwd
This is a quite helpful command which gives the path of the
working directory


References:
Wikipedia, couple of journals, ITRS website..