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SUBJECT: Computer Systems 3B (RKE3B)

TITLE: Practical Assessment 4 Outcome C
DATE: 16 September 2013
MARKS: 30
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Build a Mathematical Processor
1.) Introduction:

Your objective is to develop your own hardware mathematical processor on the Altera DE0
FPGA development board. This mathematical processor can take as input two 4 bit BCD
numbers (A and B) and perform the following operations:
Add or Subtract the 2 input numbers A and B, switch between the Add and Subtract
operation using a slider switch.
Display the input numbers A and B as well as the resulting value S using the on-board
7-segment displays.
Calculate if the resulting number S is prime using logic gates and multiplexers
derived using Shannons Expansion of the two Most significant bits S4 and S3. If it is
prime turn a Lights ON and if it is not turn the Light OFF.

You are allowed to use 74 Series chips in your implementation. A list of 74 series chips can
be found here: http://en.wikipedia.org/wiki/List_of_7400_series_integrated_circuits.
Here are some 74 Series chips that may be useful for your implementation:
7446 BCD to 7-segment decoder/driver
74283 4-bit binary Full adder
74153 Dual 4 to 1 multiplexer

2.) Input/Output constraints:
Input:
Input Value A Use switch SW9, SW8, SW7 and SW6 to input a 4 bit number where
SW6 is the least significant bit (LSB)
Input Value B Use switch SW5, SW4, SW3 and SW2 to input a 4 bit number where
SW2 is the least significant bit (LSB)
Operation ADD/SUBTRACT Switch between ADD (SW0=0) or the
SUBTRACT(SW0=1) operation with switch SW0.

Output:
Input Value A HEX3_D 7-Segment Display
Input Value B HEX2_D 7-Segment Display
Output Value S (A+B or A-B) HEX0_D 7-Segment Display
Prime test Light LEDG9




3.) Submission and Practical Notes:
Submit only the *.bdf - Block Diagram/Schematic file for the Practical on Edulink.
Both group members need to submit the project design files on their blackboard
accounts.
Only groups of 2 allowed Except when I have provided permission.
No submission = No Mark No extensions will be given.
All work must be completed before 16:40 at the date of the practical session. If you
have not yet completed your work by 16:40, a mark will be assigned based on your
progress.
Signed mark sheets (controlled by Demis) are used as attendance.
You need to show your calculations on paper or no marks (0%) will be awarded.

4.) Mark Distribution Guide:
Description Mark

Question (30)
Not present Fail the course
Implemented on FPGA but not working 4/30 (13%) [4 Marks]
ADDITION operation Working 4/30 -> 11/30 (13%-37%) [7 Marks]
7-Segment Displays Working 11/30 ->18/30 (37%-60%) [7 Marks]
SUBTRACTION operation Working 18/30 -> 25/30 (60%-83%) [7 Marks]
PRIME test Working 25/30 -> 30/30 (83%-100%) [5 Marks]