F

m
Boolean Algebra.co
s
r
& ee
n
i
g
Logic
Gates
n
E
O
o
D
a
a

Common Postulates (Boolean Algebra)

Closure
N={1,2,3,4,5,..}
It is closed w.r.t +
i.e. a+b=c
as
a,b,cN
Associative Law
(x*y)*z = x*(y*z)
for all x,y,z,S
Commutative Law
x*y = y*x for all x,yS
x+y = y+x

m
o

c
.
rs

e
e
in

g
n

E
O

a
a
F

o
D

x+y = y+x
x.Y = y.x

Common Postulates (Boolean Algebra)

Identity Element
x+0 = 0+x = x
x.1 = 1.x = x

xS

m
o

c
.
rs

e
e
x+x = 1 x*y = e a*1/a = 1in
x+y = e
g
x.x = 0
n
a+(-a) = 0 E
O
Distributed Law
o
x*(y.z) =D
(x*y) . (x*z)
a
a
x.(y+z)
= (x.y) + (x.z)
F
x+(y.z) = (x+y) . (x+z)

Inverse

e*x = x*e = x
e+x = x+e = x
0+x = x+0 = x
1*x = x*1 = x

Boolean Algebra and Logic Gates

x

x.y

x+y

m
o

c
.
x.(y+z) = (x.y)+(x.z) rs
e
e
n
i
g
n
E
O
o
D
z

Y+z

x.(y+z)

x.y

x.z

(x.y)+x.z

0
1
1

aa
1

Postulates and Theorems of Boolean Algebra

Postulate 2

(a) x+0 = x

(b) x.1 = x

Postulate 5

(a) x+x = 1

(b) x.x = 0

Theorem 1

(a) x+x = x

Theorem 2

(a) x+1 = 1

m
o

e
e
in

g
n

Theorem3, involution

(x) = x

c
.
rs

(b) x.x = x

(b) x.0 = 0

Postulate3, commutative

(a) x+y = y+x

(b) xy = yx

Theorem4, associative

E
O

(a) x+(y+z)=(x+y)+z

(b) x(yz) = (xy)z

Postulate4, distributive

(a) x(y+z)=xy+xz

(b) x+yz = (x+y)(x+z)

Theorem5, DeMorgan

(a) (x+y) = xy

(b) (xy) = x+y

Theorem6, absorption

(a) x+xy = x

(b) x(x+y)=x

o
D

a
a
F

Theorems
1a.

x+x = x
x+x = (x+x).1
= (x+x)(x+x)
= x+xx
=x+0
=x
x.x = x (Remember Duality of 1a)
x.x = xx+0
= xx+xx
= x(x+x)
= x.1
=x

m
o

c
.
rs

1b.

e
e
in

g
n

E
O

a
a
F

o
D

Theorems
2a.

2b.
2a)

x+1 = 1
x+1 =1.(x+1)
m
o
c
.
= (x+x)(x+1) rs
e
e
= (x+x) in
g
n
= x+x
E
O
o
=
1
D
a
a
F X.0 = 0 (Remember Duality of
of

3.

6a

(x) = x
Complement of x = x
Complement of x = (x) = x
x+xy = x
x+xy = x.1+xy
= x(1+y)
= x.1
=x
x(x+y) = x (Remember Duality of 6a)

m
o

c
.
rs

e
e
in

g
n

6b.

E
O

a
a
F

o
D

Can also be proved using truth table method

xy

x+xy

1
x=x+xy

1
1

aa
0
1

c
.
rs

(x+y)

xy

g
n

e
e
in

x+y

E
O

o
D

m
o

(x+y) = xy DeMorgans Theorem

(xy) = x +y DeMorgans Theorem

Operator Precedenceom
c
.
s
2.( )
r
e
e
n
i
3.NOT
g
n
E
4.AND oO
D
a
5.OR
a
F

y
xy

xy

xy

m
o

c
.
rs

xy

e
e
in

VENN DIAGRAM ILLUSTRATION X=XY+X

VENN DIAGRAM FOR TWO VARIABLES

E
O

g
n

o
D

a
a
F
x+(y+z)

z
xy+xz

VENN DIAGRAM ILLUSTRATION OF THE DISTRIBUTIVE LAW

TRUTH TABLE FOR F1=xyz, F2=x+yz, F3=xyz+xyz+xy and

F4=xy+xz
x

F1

F2

1
1

a
a
F
1
1

c
.
s

F4

r
e

e
in

g
n

E
O

o
D

m
o

F3

z
x
y

F2

F1
y

m
o

c
.
rs

(b) F2 = x+yz

(a) F1 = xyz

e
e
in

g
n

E
O

o
D

a
a
F

(c) F3 = xyz+xyz+xy

F3

m
o

c
.
rs

e
e
in

g
n

E
O

F4

(c) F4 = xy+xz

o
D

a
a
F

Implementation of Boolean Function with GATES

Algebraic Manipulations for Minimization of Boolean Functions

(Literal minimization)

1.

x+xy = (x+x)(x+y)
= 1.(x+y)=x+y
3. x(x+y) = xx+xy
= 0+xy=xy
5. xyz+xyz+xy
= xz(y+y)+xy
= xz+xy
8. xy+xz+yz
(Consensus Theorem)
=xy+xz+yz(x+x)
=xy+xz+xyz+xyz
=xy(1+z)+xz(1+y)
=xy+xz
13. (x+y)(x+z)(y+z)=(x+y)(x+z)
by duality from function 4

m
o

c
.
rs

e
e
in

g
n

E
O

a
a
F

o
D

Complement of a Function
(A+B+C) = (A+X)
= AX
= A.(B+C)
= A.(BC)
= ABC
(A+B+C+D+..Z) = ABCD..Z
(ABCD.Z) = A+B+C+D+.+Z
Example using De Morgans Theorem (Method-1)
F1 = xyz+xyz
F1 = (xyz+xyz)
= (x+y+z)(x+y+z)
F2 = x(yz+yz)
F2= [x(yz+yz)]
= x+(y+z)(y+z)

m
o

c
.
rs

e
e
in

g
n

E
O

a
a
F

o
D

Example using dual and complement of

each literal (Method-2)

F1 = xyz + xyz

m
o

Dual of F1 = (x+y+z)(x+y+z) .c
s
r
Complement F1 = (x+y+z)(x+y+z)
e

e
in

g
n

F2 = x(yz+yz)
E
O
Dual of F2=x+(y+z)(y+z]
o
D
a
Complement
a =F2= x+ (y+z)(y+z)

Minterm or a Standard Product

n variables forming an AND term provide 2n possible
combinations, called minterms or standard products
(denoted as m1, m2 etc.).
Variable primed if a bit is o
Variable unprimed if a bit is 1
Maxterm or a Standard Sum
n variables forming an OR term provide 2n possible
combinations, called maxterms or standard sums
(denoted as M1,M2 etc.).
Variable primed if a bit is 1
Variable unprimed if a bit is 0

m
o

c
.
rs

e
e
in

g
n

E
O

a
a
F

o
D

MINTERMS AND MAXTERMS FOR THREE BINARY VARIABLES

MINTERMS

MAXTERMS

Term

Designation

xyz

m0

xyz

m1

xyz

m2

xyz

xyz

Term

c
.
rs

m
o

x+y+z

ee

Designation
M0

x+y+z

M1

x+y+z

M2

m3

x+y+z

M3

m4

x+y+z

M4

xyz

m5

x+y+z

M5

xyz

m6

x+y+z

M6

xyz

m7

x+y+z

M7

n
E

O
o

D
a
a

n
i
g

FUNCTION OF THREE VARIABLES

x

Function f1

Function f2

a
a
F
f1 = xyz+xyz+xyz

e
e
in

c
.
rs

0
1
0

g
n

E
O

o
D

m
o
0

=m1 + m4 + m7
f2 = xyz+xyz+xyz+xyz = m3 + m5 + m6 + m7

MINTERMS AND MAXTERMS FOR THREE BINARY VARIABLES

f1 = xyz+xyz+xyz
f1 = xyz+xyz+xyz+xyz+xyz
f1 =(x+y+z)(x+y+z)(x+y+z)(x+y+z) (x+y+z)
= M0.M2.M3.M5.M6
= M0M2M3M5M6
f2 = xyz+xyz+xyz+xyz
f2 = xyz+xyz+xyz+xyz
f2 = (x+y+z)(x+y+z)(x+y+z)(x+y+z)
= M0 M1 M2 M4
Canonical Form
Boolean functions expressed as a sum of minterms or product of
maxterms are said to be in canonical form.
M3+m5+m6+m7 or M0 M1 M2 M4

m
o

c
.
rs

e
e
in

g
n

E
O

a
a
F

o
D

Sum of Minterms (Sum of Products)

Example:
F = A+BC
F = A(B+B)+BC(A+A)
= AB+AB+ABC+ABC
= AB(C+C)+AB(C+C)+ABC+ABC
= ABC+ABC+ABC+ABC+ABC+ABC
= ABC+ABC+ABC+ABC+ABC
= m1+m4+m5+m6+m7
F(A,B,C)=(1,4,5,6,7)

m
o

c
.
rs

e
e
in

g
n

E
O

a
a
F

o
D

ORing of term

AND terms of variables A,B &C

They are minterms of the function

Product of Maxterms (Product of sums)

Example:
F = xy+xz
F = xy+xz
F = (xy+x)(xy+z)
distr.law (x+yz)=(x+y)(x+z)
= (x+x)(y+x)(x+z)(y+z)
= (x+y)(x+z)(y+z)
= (x+y+zz)(x+z+yy)(y+z+xx)
= (x+y+z)(x+y+z)(x+z+y)(x+z+y)(y+z+x)(y+z+x)
= (x+y+z)(x+y+z)(x+y+z)(x+y+z)
= M0 M2 M4 M5
F(x,y,z) = (0,2,4,5)

m
o

c
.
rs

e
e
in

g
n

E
O

o
D

a
a
F

ANDing of terms

Maxterms of the function (4 OR terms

of variables x,y&z)

Conversion between Canonical Forms

F(A,B,C) = (1,4,5,6,7)
sum of minterms
F(A,B,C) = (0,2,3)
= m0+m2+m3
F(A,B,C) = (m0+m2+m3)
= m0.m2.m3
= M0 M2 M3
= (0,2,3)
Product of maxterms

e
e
in

c
.
rs

g
n

E
O

a
a
F

o
D

Similarly
F(x,y,z) = (0,2,4,5)
F(x,y,z) = (1,3,6,7)

m
o

Standard Forms
Sum of Products (OR operations)
F1 = y+xy+xyz
(AND term/product term)
Product of Sums (AND operations)
F2=x(y+z)(x+y+z+w)

(OR term/sum term)

Non-standard form
F3=(AB+CD)(AB+CD)

E
O

g
n

a
a
F

o
D

Standard form of F3
F3=ABCD + ABCD

e
e
in

c
.
rs

m
o

TRUTH TABLE FOR THE 16 FUNCTIONS OF

TWO BINARY VARIABLES
x

F0

F1

F2

F3

F4

F5

F6

F7

F8

F9

F10

F11

F12

F13

F14

F15

c
.
rs

m
o

Operator
symbols

F0 = 0

F1 = xy

F4 = xy

F5 = y

F8 = (x+y)
F12 = x

n
i
g

n
E

O
o

ee

F2 = xy

F3 = x

F6 = xy +xy

F7= x +y

F9 = xy +xy

F10 = y

F11 = x +y

F13 = x + y

F14 = (xy)

F15 = 1

aD

a
F

BOOLEAN EXPRESSIONS FOR THE 16 FUNCTIONS OF TWO VARIABLE

BOOLEAN
FUNCTIONS

OPERATOR
SYMBOL

NAME

F0 =0

NULL

COMMENTS

F1=xy

x.y

F2=xy
F3=x
F4=xy
F5=y
F6=xy+xy
F7=x+y
F8=(x+y)
F9=xy+xy
F10=y
F11=x+y
F12=x
F13=x+y
F14=(xy)
F15=1

x/y

BINARY CONSTANT 0

c
.
rs

AND

e
e
in

y/x
x
y
x+y
x y
x
y
y
xy
x
xy
x
y

a
a
F

g
n

E
O

o
D

inhibition
transfer
inhibition
transfer
exclusive-OR
OR
NOR
*equivalence
complement
implication
complement
implication
NAND
IDENTITY

m
o

x and y

x but not y
x
y but not x
y
x or y but not both
x or y
not OR
x equals y
not y
if y then x
not x
if x then y
not AND
BINARY CONSTANT 1

 *Equivalence is also known as equality, coincidence, and

exclusive NOR
16 logic operations are obtained from two variables x &y
Standard gates used in digital design are: complement,
transfer, AND, OR , NAND, NOR, XOR & XNOR (equivalence).

m
o

c
.
rs

e
e
in

g
n

E
O

a
a
F

o
D

H and L LEVEL IN IC LOGIC FAMILIES

IC Family Voltage
High-level voltage Low-level
Type
Supply (V)
(V) voltage (V)

m
o

c
.
rs

e
e
in

g
n
Vcc=5
2.4-5
3.5
E
O
VEE=-5.2
-0.95- -0.7 -0.8
o
D
a
VDD=3--10
VDD
VDD
a
F
Range

TTL
ECL
CMOS
Positive Logic:
Negative Logic

Typical

Range

Typical

0-0.4
0.2
-1.9-- -1.6 -1.8
0-0.5
0
Logic-1 Logic-0
Logic-0 Logic-1

TYPICAL CHARACTERISTICS OF IC
LOGIC FAMILIES
IC Logic
Family
Standard TTL
Shottky TTL
Low power
Shottky TTL
ECL
CMOS

Fan out

Power
Dissipation (mw)

10
10

10
22

20
25
50

2
25
0.1

Propagation
delay (ns)
10
3

E
O

g
n

e
in

10
2
25

o
D

a
a
F

m
o

c
.
s

r
e

TTL basic circuit : NAND gate

ECL basic circuit: NOR gate
CMOS basic circuit: Inverter to construct NAND/NOR

Noise Margin (v)

0.4
0.4
0.4
0.2
3

DIGITAL LOGIC GATES

NAME

GRAPHIC
SYMBOL

ALGEBRIC
FUNCTION

AND

F=XY

TRUTH
TABLE

X
Y

e
e
in

g
n

OR

a
a
F

o
D

E
O

X
Y

F=X+Y

c
.
rs

m
o
X Y
0 0
0 1
1 0
1 1

F
0
0
0
1

X Y
0 0
0 1
1 0
1 1

F
0
1
1
1

NAME

GRAPHIC
SYMBOL

ALGEBRIC
FUNCTION

Inverter

TRUTH
TABLE

F=X

e
e
in

F=X

g
n

NAND

a
a
F

o
D

E
O

X
Y

F=(XY)

F
1
0

X
0
1

F
0
1

m
o

c
.
rs

Buffer

X
0
1

X Y
0 0
0 1
1 0
1 1

F
1
1
1
0

NAME

GRAPHIC
SYMBOL
X
Y

NOR

ALGEBRIC
FUNCTION

TRUTH
TABLE

F=(X+Y)

X Y
0 0
0 1
1 0
1 1

F
1
0
0
0

X Y
0 0
0 1
1 0
1 1

F
0
1
1
0

X Y
0 0
0 1
1 0
1 1

F
1
0
0
1

m
o

c
.
rs

g
n

X
Y

Exclusive-OR
(XOR)

e
e
in

E
O

F=XY+XY
=XY

o
D

a
a
F

Exclusive-NOR
or
Equivalence

X
Y

F=XY+XY
=X Y

(X+Y)

[Z+(X+Y)]

(X

Y) Z=(X+Y) Z
=XZ+YZ

m
o

c
.
rs

ee

n
i
g

n
E

O
o

(Y+Z)

Y
Z

(X ( Y Z)=X(Y+ Z)

[X+(Y+Z)]

D
a
a

Demonstrating the nonassociativity of the NOR operator

(X Y) Z X (Y Z)

=XY+XZ

X
Y
Z

X
Y
Z

(X+Y+Z)

m
o

(a) There input NOR gate

(b) There input NAND gate

c
.
rs

e
e
in

A
B
C

D
E

(XYZ)

g
n

E
O

a
a
F

o
D

F=[(ABC). (DE)]=ABC+DE

(c) Cascaded NAND gates

Multiple-input AND cascaded NOR and NAND gates

TRUTH TABLE
X
Y

F=X Y Z

X
0
0
0
0
1
1
1
1

g
n

Z
0
1
0
1
0
1
0
1

m
o

c
.
rs

e
e
in

(a) Using two input gates

Y
0
0
1
1
0
0
1
1

o
D

1
0
0
1
0
1
1
0

F=X Y Z

aa

(b) Three input gates

0
1
1
0
1
0
0
1
XOR

E
O

X
Y
Z

(b) Three input exclusive OR gates

XNOR
Odd
function
Even
function

IC DIGITAL LOGIC FAMILIES

TTL

Transistor- Transistor Logic

Very popular logic family.

It has a extensive list of digital functions.
It has a large number of MSI and SSI devices, also has LSI devices.

m
o

c
.
rs

ECL Emitter Coupled Logic

Used in systems requiring high speed operations.

It has a large number of MSI and SSI devices, also LSI devices.

MOS Metal-Oxide Semiconductor

e
e
in

g
n

Used in circuit requiring high component density

It has a large number of MSI and SSI devices, also LSI devices
(mostly)

E
O

o
D

CMOS Complementary MOS

Used in systems requiring low power consumption.

It has a large number of MSI and SSI devices, also has LSI devices.

a
a
F

I2L Integrated - Injection Logic

Used in circuit requiring high component density.

Mostly used for LSI functions

Some Typical IC Gates

VCC
14

VCC
13

12

11 10

m
o

c
.
rs

14 13

12

11 10

e
e
in

g
n

o
D

E
O

a
a
F

GND

7404 Hex Inverters

TTL gates

GND

7400 Quadruple 2-input

NAND gates

VCC 2
16 15

Some Typical IC Gates

14

13

12

11

10

10107 Triple
Exclusive OR/
NOR gates

m
o

1 2
VCC 1

VCC 2
16

15

14

12

e
e
in

g
n

E
O

13

c
.
rs

11

VEE 2 (-5.2V)

10

o
D

a
a
F
VCC 1

10102 Quadruple
2-Input NOR gate

VEE (-5.2V)

(3-15 V)

VDD
14

13

12

NC
11

10

m
o

c
.
rs

e
e
in

C MOS

g
n

GATES

E
O

a
a
F

o
D

4002 dual 4 input NOR gates

NC

Vss (GND)

NC

NC
16 15

14

13

12

11

10

m
o

c
.
rs

e
e
in

VDD

(3-15 V)

E
O

g
n

o
D

a
a
F

4050 Hex buffer

8 Vss
(GND)

CMOS
GATES

LOGIC

SIGNAL

LOGIC

VALUE

VALUE

VALUE

D
a
a

O
o

Positive Logic

1
Negative Logic

Signal amplitude assignment and type of logic

m
o

c
.
rs

ee

n
i
g

n
E

SIGNAL
VALUE

e
e
in

g
n

x
y

Truth table for positive logic

H=1,

E
O

o
D

a
a
F
1

m
o

Gate block diagram

H and L
y

c
.
rs

Truth table in terms of

TTL
7400
GATE

L=0

Graphic symbol for

positive logic NAND gate

x
y

m
o

c
.
rs

Graphic symbol for negative logic

NOR gate

e
e
in

g
n

Truth table for negative logic

L=1

E
O

H=0

o
D

a
a
F

Same gate can function

+ive logic NAND or -ive logic NOR
+ive logic NOR or -ive logic NAND

DEMONSTRATION OF POSITIVE AND

NEGATIVE LOGIC

Characteristics of IC logic families

(parameters)
Fan-out
Specifies the number of standard loads (the amount of current needed by
an input of another gate in the same IC family) that the output of a gate can
drive without impairing its normal operation. it is expressed by a number.
Power dissipation
It is the supplied power required to operate the gate. It is expressed in mw.
Propagation delay
It is the average transition delay time for a signal to propagate from input to
output when the binary signals change in value. It is expressed in ns.
Noise margin
It is the maximum noise voltage added to the input signal of a digital circuit
that does not cause an undesirable change in the circuit output. It is
expressed in volts (v).

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