8255 Programmable Peripheral Interface

(PPI)
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system
data bus. Data is transmitted or received by the buffer upon execution of input or
output instructions by the CPU. Control ords and status informa-tion are also
transferred throu!h the data bus buffer.
Read/Write and Control Logic
The function of this bloc" is to mana!e all of the internal and external transfers of
both Data and Control or #tatus ords. $t accepts inputs from the CPU %ddress and
Control busses and in turn& issues commands to both of the Control 'roups.
(CS) Chip #elect. % (lo( on this input pin enables the communcation beteen the
8255 and the CPU.
(RD) )ead. % (lo( on this input pin enables 8255 to send the data or status
information to the CPU on the data bus. $n essence& it allos the CPU to (read from(
the 8255.
(WR) *rite. % (lo( on this input pin enables the CPU to rite data or control ords
into the 8255.
(A0 and A1) Port #elect + and Port #elect ,. These input si!nals& in con-unction ith
the )D and *) inputs& control the selection of one of the three ports or the control
ord re!ister. They are normally connected to the least si!nificant bits of the address
bus .%+ and %,/.
(RESET) )eset. % (hi!h( on this input initiali0es the control re!ister to 12h and all
ports .%& 2& C/ are set to the input mode.

%, %+ #343CT$56
+ + P5)T %
+ , P5)T 2
, + P5)T C
, , C56T)54
Grou A and Grou B Controls
The functional confi!uration of each port is pro!rammed by the systems softare. $n
essence& the CPU (outputs( a control ord to the 8255. The control ord contains
information such as (mode(& (bit set(& (bit reset(& etc.& that initiali0es the functional
confi!uration of the 8255. 3ach of the Control bloc"s .'roup % and 'roup 2/ accepts
(commands( from the )ead7*rite Control lo!ic& receives (control ords( from the
internal data bus and issues the proper commands to its associated ports.
!orts A" B" and C
The 8255 contains three 8-bit ports .%& 2& and C/. %ll can be confi!ured to a ide
variety of functional characteristics by the system softare but each has its on
special features or (personality( to further enhance the poer and flexibility of the
8255.
!ort A 5ne 8-bit data output latch7buffer and one 8-bit data input latch. 2oth (pull-
up( and (pull-don( bus-hold devices are present on Port %.
!ort B 5ne 8-bit data input7output latch7buffer and one 8-bit data input buffer.
!ort C 5ne 8-bit data output latch7buffer and one 8-bit data input buffer .no latch for
input/. This port can be divided into to 8-bit ports under the mode control. 3ach 8-
bit port contains a 8-bit latch and it can be used for the control si!nal output and
status si!nal inputs in con-unction ith ports % and 2.

Bloc# Diagra$ of t%e &'(( !rogra$$a)le !eri%eral *nterface (!!*)


+ode Definition ,or$at

3xamples of $675UT instructions and 8+89 assembly lan!ua!e
pro!rammes.
8255 Programmable Peripheral Interface
(PPI)
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system
data bus. Data is transmitted or received by the buffer upon execution of input or
output instructions by the CPU. Control ords and status informa-tion are also
transferred throu!h the data bus buffer.
Read/Write and Control Logic
The function of this bloc" is to mana!e all of the internal and external transfers of
both Data and Control or #tatus ords. $t accepts inputs from the CPU %ddress and
Control busses and in turn& issues commands to both of the Control 'roups.
(CS) Chip #elect. % (lo( on this input pin enables the communcation beteen the
8255 and the CPU.
(RD) )ead. % (lo( on this input pin enables 8255 to send the data or status
information to the CPU on the data bus. $n essence& it allos the CPU to (read from(
the 8255.
(WR) *rite. % (lo( on this input pin enables the CPU to rite data or control ords
into the 8255.
(A0 and A1) Port #elect + and Port #elect ,. These input si!nals& in con-unction ith
the )D and *) inputs& control the selection of one of the three ports or the control
ord re!ister. They are normally connected to the least si!nificant bits of the address
bus .%+ and %,/.
(RESET) )eset. % (hi!h( on this input initiali0es the control re!ister to 12h and all
ports .%& 2& C/ are set to the input mode.

%, %+ #343CT$56
+ + P5)T %
+ , P5)T 2
, + P5)T C
, , C56T)54
Grou A and Grou B Controls
The functional confi!uration of each port is pro!rammed by the systems softare. $n
essence& the CPU (outputs( a control ord to the 8255. The control ord contains
information such as (mode(& (bit set(& (bit reset(& etc.& that initiali0es the functional
confi!uration of the 8255. 3ach of the Control bloc"s .'roup % and 'roup 2/ accepts
(commands( from the )ead7*rite Control lo!ic& receives (control ords( from the
internal data bus and issues the proper commands to its associated ports.
!orts A" B" and C
The 8255 contains three 8-bit ports .%& 2& and C/. %ll can be confi!ured to a ide
variety of functional characteristics by the system softare but each has its on
special features or (personality( to further enhance the poer and flexibility of the
8255.
!ort A 5ne 8-bit data output latch7buffer and one 8-bit data input latch. 2oth (pull-
up( and (pull-don( bus-hold devices are present on Port %.
!ort B 5ne 8-bit data input7output latch7buffer and one 8-bit data input buffer.
!ort C 5ne 8-bit data output latch7buffer and one 8-bit data input buffer .no latch for
input/. This port can be divided into to 8-bit ports under the mode control. 3ach 8-
bit port contains a 8-bit latch and it can be used for the control si!nal output and
status si!nal inputs in con-unction ith ports % and 2.

Bloc# Diagra$ of t%e &'(( !rogra$$a)le !eri%eral *nterface (!!*)


+ode Definition ,or$at

3xamples of $675UT instructions and 8+89 assembly lan!ua!e
pro!rammes.
8255 Programmable Peripheral Interface
(PPI)
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system
data bus. Data is transmitted or received by the buffer upon execution of input or
output instructions by the CPU. Control ords and status informa-tion are also
transferred throu!h the data bus buffer.
Read/Write and Control Logic
The function of this bloc" is to mana!e all of the internal and external transfers of
both Data and Control or #tatus ords. $t accepts inputs from the CPU %ddress and
Control busses and in turn& issues commands to both of the Control 'roups.
(CS) Chip #elect. % (lo( on this input pin enables the communcation beteen the
8255 and the CPU.
(RD) )ead. % (lo( on this input pin enables 8255 to send the data or status
information to the CPU on the data bus. $n essence& it allos the CPU to (read from(
the 8255.
(WR) *rite. % (lo( on this input pin enables the CPU to rite data or control ords
into the 8255.
(A0 and A1) Port #elect + and Port #elect ,. These input si!nals& in con-unction ith
the )D and *) inputs& control the selection of one of the three ports or the control
ord re!ister. They are normally connected to the least si!nificant bits of the address
bus .%+ and %,/.
(RESET) )eset. % (hi!h( on this input initiali0es the control re!ister to 12h and all
ports .%& 2& C/ are set to the input mode.

%, %+ #343CT$56
+ + P5)T %
+ , P5)T 2
, + P5)T C
, , C56T)54
Grou A and Grou B Controls
The functional confi!uration of each port is pro!rammed by the systems softare. $n
essence& the CPU (outputs( a control ord to the 8255. The control ord contains
information such as (mode(& (bit set(& (bit reset(& etc.& that initiali0es the functional
confi!uration of the 8255. 3ach of the Control bloc"s .'roup % and 'roup 2/ accepts
(commands( from the )ead7*rite Control lo!ic& receives (control ords( from the
internal data bus and issues the proper commands to its associated ports.
!orts A" B" and C
The 8255 contains three 8-bit ports .%& 2& and C/. %ll can be confi!ured to a ide
variety of functional characteristics by the system softare but each has its on
special features or (personality( to further enhance the poer and flexibility of the
8255.
!ort A 5ne 8-bit data output latch7buffer and one 8-bit data input latch. 2oth (pull-
up( and (pull-don( bus-hold devices are present on Port %.
!ort B 5ne 8-bit data input7output latch7buffer and one 8-bit data input buffer.
!ort C 5ne 8-bit data output latch7buffer and one 8-bit data input buffer .no latch for
input/. This port can be divided into to 8-bit ports under the mode control. 3ach 8-
bit port contains a 8-bit latch and it can be used for the control si!nal output and
status si!nal inputs in con-unction ith ports % and 2.

Bloc# Diagra$ of t%e &'(( !rogra$$a)le !eri%eral *nterface (!!*)


+ode Definition ,or$at

3xamples of $675UT instructions and 8+89 assembly lan!ua!e
pro!rammes.
8255 Programmable Peripheral Interface
(PPI)
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system
data bus. Data is transmitted or received by the buffer upon execution of input or
output instructions by the CPU. Control ords and status informa-tion are also
transferred throu!h the data bus buffer.
Read/Write and Control Logic
The function of this bloc" is to mana!e all of the internal and external transfers of
both Data and Control or #tatus ords. $t accepts inputs from the CPU %ddress and
Control busses and in turn& issues commands to both of the Control 'roups.
(CS) Chip #elect. % (lo( on this input pin enables the communcation beteen the
8255 and the CPU.
(RD) )ead. % (lo( on this input pin enables 8255 to send the data or status
information to the CPU on the data bus. $n essence& it allos the CPU to (read from(
the 8255.
(WR) *rite. % (lo( on this input pin enables the CPU to rite data or control ords
into the 8255.
(A0 and A1) Port #elect + and Port #elect ,. These input si!nals& in con-unction ith
the )D and *) inputs& control the selection of one of the three ports or the control
ord re!ister. They are normally connected to the least si!nificant bits of the address
bus .%+ and %,/.
(RESET) )eset. % (hi!h( on this input initiali0es the control re!ister to 12h and all
ports .%& 2& C/ are set to the input mode.

%, %+ #343CT$56
+ + P5)T %
+ , P5)T 2
, + P5)T C
, , C56T)54
Grou A and Grou B Controls
The functional confi!uration of each port is pro!rammed by the systems softare. $n
essence& the CPU (outputs( a control ord to the 8255. The control ord contains
information such as (mode(& (bit set(& (bit reset(& etc.& that initiali0es the functional
confi!uration of the 8255. 3ach of the Control bloc"s .'roup % and 'roup 2/ accepts
(commands( from the )ead7*rite Control lo!ic& receives (control ords( from the
internal data bus and issues the proper commands to its associated ports.
!orts A" B" and C
The 8255 contains three 8-bit ports .%& 2& and C/. %ll can be confi!ured to a ide
variety of functional characteristics by the system softare but each has its on
special features or (personality( to further enhance the poer and flexibility of the
8255.
!ort A 5ne 8-bit data output latch7buffer and one 8-bit data input latch. 2oth (pull-
up( and (pull-don( bus-hold devices are present on Port %.
!ort B 5ne 8-bit data input7output latch7buffer and one 8-bit data input buffer.
!ort C 5ne 8-bit data output latch7buffer and one 8-bit data input buffer .no latch for
input/. This port can be divided into to 8-bit ports under the mode control. 3ach 8-
bit port contains a 8-bit latch and it can be used for the control si!nal output and
status si!nal inputs in con-unction ith ports % and 2.

Bloc# Diagra$ of t%e &'(( !rogra$$a)le !eri%eral *nterface (!!*)


+ode Definition ,or$at

3xamples of $675UT instructions and 8+89 assembly lan!ua!e
pro!rammes.
8255 Programmable Peripheral Interface
(PPI)
Data Bus Buffer
This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system
data bus. Data is transmitted or received by the buffer upon execution of input or
output instructions by the CPU. Control ords and status informa-tion are also
transferred throu!h the data bus buffer.
Read/Write and Control Logic
The function of this bloc" is to mana!e all of the internal and external transfers of
both Data and Control or #tatus ords. $t accepts inputs from the CPU %ddress and
Control busses and in turn& issues commands to both of the Control 'roups.
(CS) Chip #elect. % (lo( on this input pin enables the communcation beteen the
8255 and the CPU.
(RD) )ead. % (lo( on this input pin enables 8255 to send the data or status
information to the CPU on the data bus. $n essence& it allos the CPU to (read from(
the 8255.
(WR) *rite. % (lo( on this input pin enables the CPU to rite data or control ords
into the 8255.
(A0 and A1) Port #elect + and Port #elect ,. These input si!nals& in con-unction ith
the )D and *) inputs& control the selection of one of the three ports or the control
ord re!ister. They are normally connected to the least si!nificant bits of the address
bus .%+ and %,/.
(RESET) )eset. % (hi!h( on this input initiali0es the control re!ister to 12h and all
ports .%& 2& C/ are set to the input mode.

%, %+ #343CT$56
+ + P5)T %
+ , P5)T 2
, + P5)T C
, , C56T)54
Grou A and Grou B Controls
The functional confi!uration of each port is pro!rammed by the systems softare. $n
essence& the CPU (outputs( a control ord to the 8255. The control ord contains
information such as (mode(& (bit set(& (bit reset(& etc.& that initiali0es the functional
confi!uration of the 8255. 3ach of the Control bloc"s .'roup % and 'roup 2/ accepts
(commands( from the )ead7*rite Control lo!ic& receives (control ords( from the
internal data bus and issues the proper commands to its associated ports.
!orts A" B" and C
The 8255 contains three 8-bit ports .%& 2& and C/. %ll can be confi!ured to a ide
variety of functional characteristics by the system softare but each has its on
special features or (personality( to further enhance the poer and flexibility of the
8255.
!ort A 5ne 8-bit data output latch7buffer and one 8-bit data input latch. 2oth (pull-
up( and (pull-don( bus-hold devices are present on Port %.
!ort B 5ne 8-bit data input7output latch7buffer and one 8-bit data input buffer.
!ort C 5ne 8-bit data output latch7buffer and one 8-bit data input buffer .no latch for
input/. This port can be divided into to 8-bit ports under the mode control. 3ach 8-
bit port contains a 8-bit latch and it can be used for the control si!nal output and
status si!nal inputs in con-unction ith ports % and 2.

Bloc# Diagra$ of t%e &'(( !rogra$$a)le !eri%eral *nterface (!!*)


+ode Definition ,or$at

3xamples of $675UT instructions and 8+89 assembly lan!ua!e
pro!rammes.
8251 pro!rammable interrupt controller
825, U#%)T
$ntel C825,
The 825, Universal #ynchronous7%synchronous )eceiver7Transmitter pac"a!ed in a 28-pin D$P made
by $ntel. $t is typically used for serial communication and as rated for ,1.2 :bits per second si!nallin! rate.
$t is commonly confused ith the much more common 825+ U%)T that as made popular as the serial port
in the $2; Personal Computer.
$t includes 5 sections
,. read7rite control lo!ic
2. transmitter
<. receiver
8. data bus system
5. modem control