TSMC

Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
1Confidential-
Security
C TSMC Hierarchical Design Flow Diagram
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
1Confidential-
Security
C TSMC Hierarchical Design Flow Diagram
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
2Confidential-
Security
C
RC Correlation
(StarRCXT->
Apollo->
FE)
flattened prototyping
(FE)
IR
drop analysis
(MarsRail)
hierarchical prototyping
(FE)
Netlist, Timing
Constraint, Size
top
level trial route (
APO)
floorplanning
(FE)
Prototyping
RC Correlation(
FE->
PC)
block
frame view
and
pdb
generation(
APO)
block
preCTS
implementation (PC)
:
placement, timing
optimization
block
timing
model
generation
top
preCTS
implementation
(
PC):
placement, timing
optimization
top/
block
implementation
(
APO):
CTS, track
assign, SDF
RC Correlation
(
APO->
PC)
block/top post
CTS
implementation
(PC)
block/top detail
route (
APO):
double via, xtalk,
antenna
fullchip
STA
(
PT,
StarRCXT,
NDC)
characterizing
timing-
violated
blocks(PT)
budgeting
(PT)
Hierarchical Timing Closure
full chip
verification:
IR analysis (Voltage
Storm)
DRC
LVS
(Calibre)
Formal Verification
(Formality,
Verplex)
xtalk
(CeltIc)
Fullchip
Verification
APO:
Apollo
FE: First
Encounter
NDC:
Nautilus
DC
PC: Physical Compiler
PT: PrimeTime
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
2Confidential-
Security
C
RC Correlation
(StarRCXT->
Apollo->
FE)
flattened prototyping
(FE)
IR
drop analysis
(MarsRail)
hierarchical prototyping
(FE)
Netlist, Timing
Constraint, Size
top
level trial route (
APO)
floorplanning
(FE)
Prototyping
RC Correlation(
FE->
PC)
block
frame view
and
pdb
generation(
APO)
block
preCTS
implementation (PC)
:
placement, timing
optimization
block
timing
model
generation
top
preCTS
implementation
(
PC):
placement, timing
optimization
top/
block
implementation
(
APO):
CTS, track
assign, SDF
RC Correlation
(
APO->
PC)
block/top post
CTS
implementation
(PC)
block/top detail
route (
APO):
double via, xtalk,
antenna
fullchip
STA
(
PT,
StarRCXT,
NDC)
characterizing
timing-
violated
blocks(PT)
budgeting
(PT)
Hierarchical Timing Closure
full chip
verification:
IR analysis (Voltage
Storm)
DRC
LVS
(Calibre)
Formal Verification
(Formality,
Verplex)
xtalk
(CeltIc)
Fullchip
Verification
APO:
Apollo
FE: First
Encounter
NDC:
Nautilus
DC
PC: Physical Compiler
PT: PrimeTime
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
3Confidential-
Security
C
RC Correlation
(StarRCXT->
Apollo->
FE)
flattened prototyping (FE)
floorplanning (
FE)
hierarchical prototyping
(FE)
Netlist, Timing
Constraint, Size
Prototyping
Hierarchical Timing Closure
Fullchip
Verification
original
netlist
timing constraint
(sdc)
timing library(.
lib)
standard
cell
library(.
cdump)
technology
file
initial
floorplan
(
I/O,
critical
macro
placement)
Amoeba Place
congestion
OK?
design
import
CTS
trial
route
Extract
RC
Timing
Analysis
IPO
Is
Timing Met?
no
yes
yes
no
timing repair loop
congestion repair loop
trial
route
save
route
save
place
saved initial
placement
saved initial
routing
create
fences
(shaping,
resizing)
Amoeba
place
feed-through
buffer
insertion,
refine
placement,
trial route
save floorplan
save
placement
save
netlist
commit
partition
top level
route
Congestion
OK?
floorplan
file(
.
fp)
placement
file(
.
place)
netlist(
.
v)
saved
initial
placement
and
routing
congestion repair loop
CTS
trial route
Extract RC
Timing
Analysis
IPO
Is
Timing
Met?
yes
no timing repair loop
no
yes
Save
Partition
Partitioned
netlist,
constraint,
floorplan
original
netlist
timing
constraint
(
sdc)
timing
library(
.
lib)
standard
cell
library(.cdump)
techno logy
file
IR drop analysis
(MarsRail)
top
level trial route (
APO)
specify partition
macro
placement
refinement
power
planning
trial route
load
placement,
load
routing
design
import
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
3Confidential-
Security
C
RC Correlation
(StarRCXT->
Apollo->
FE)
flattened prototyping (FE)
floorplanning (
FE)
hierarchical prototyping
(FE)
Netlist, Timing
Constraint, Size
Prototyping
Hierarchical Timing Closure
Fullchip
Verification
original
netlist
timing constraint
(sdc)
timing library(.
lib)
standard
cell
library(.
cdump)
technology
file
initial
floorplan
(
I/O,
critical
macro
placement)
Amoeba Place
congestion
OK?
design
import
CTS
trial
route
Extract
RC
Timing
Analysis
IPO
Is
Timing Met?
no
yes
yes
no
timing repair loop
congestion repair loop
trial
route
save
route
save
place
saved initial
placement
saved initial
routing
create
fences
(shaping,
resizing)
Amoeba
place
feed-through
buffer
insertion,
refine
placement,
trial route
save floorplan
save
placement
save
netlist
commit
partition
top level
route
Congestion
OK?
floorplan
file(
.
fp)
placement
file(
.
place)
netlist(
.
v)
saved
initial
placement
and
routing
congestion repair loop
CTS
trial route
Extract RC
Timing
Analysis
IPO
Is
Timing
Met?
yes
no timing repair loop
no
yes
Save
Partition
Partitioned
netlist,
constraint,
floorplan
original
netlist
timing
constraint
(
sdc)
timing
library(
.
lib)
standard
cell
library(.cdump)
techno logy
file
IR drop analysis
(MarsRail)
top
level trial route (
APO)
specify partition
macro
placement
refinement
power
planning
trial route
load
placement,
load
routing
design
import
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
4Confidential-
Security
C
Prototyping
Hierarchical Timing Closure
Fullchip
Verification
1.
partitioned
netlist
2.
partitioned
timing
constraint
3.
standard
cell library
4.
macro library
5.
timing
library
Design Import
Load Floorplan
AmoebaPlace
Partitioned
Floorplan
(.fp)
CTS
TrialRoute
congestion
OK?
Extract RC
Timing
Analysis
IPO
Is timing
met?
modify
top level
floorplan
Macro Placement
PT:
Budgeting
RC Correlation
Extract
RC
SPEF
Setload
Delay
Calculation
SDF
Save
netlist
Save Placement
Netlist
PDEF
no
yes
no
yes
Create Stamp Model
Model Definition
Model Data
RC Correlation
(StarRCXT->
Apollo->
FE)
flattened prototyping
(FE)
floorplanning
(FE)
hierarchical
prototyping
(FE) (Block
Level)
Netlist, Timing
Constraint, Size
IR
drop
analysis (MarsRail)
top
level trial route (
APO)
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
4Confidential-
Security
C
Prototyping
Hierarchical Timing Closure
Fullchip
Verification
1.
partitioned
netlist
2.
partitioned
timing
constraint
3.
standard
cell library
4.
macro library
5.
timing
library
Design Import
Load Floorplan
AmoebaPlace
Partitioned
Floorplan
(.fp)
CTS
TrialRoute
congestion
OK?
Extract RC
Timing
Analysis
IPO
Is timing
met?
modify
top level
floorplan
Macro Placement
PT:
Budgeting
RC Correlation
Extract
RC
SPEF
Setload
Delay
Calculation
SDF
Save
netlist
Save Placement
Netlist
PDEF
no
yes
no
yes
Create Stamp Model
Model Definition
Model Data
RC Correlation
(StarRCXT->
Apollo->
FE)
flattened prototyping
(FE)
floorplanning
(FE)
hierarchical
prototyping
(FE) (Block
Level)
Netlist, Timing
Constraint, Size
IR
drop
analysis (MarsRail)
top
level trial route (
APO)
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
5Confidential-
Security
C
Prototyping
Hierarchical Timing Closure
Fullchip
Verification
Stamp Models
of
Each
Partition
1.Macro Libraries
of
Each
Partition
(.cdump)
2.
Top
Level Netlist
3.Top Level
Timing
Constraints
1.
Standard Cell
Library
2.
Timing
Library
3.
Technology
file
Top Level
Floorplan
Design Import
Load Floorplan
AmoebaPlace
CTS
Trial Route
congestion
OK?
Extract RC
Timing
Analysis
IPO
Is timing
met?
PT:
Budgeting
RC Correlation
Extract RC
SPEF
Setload
Delay
Calculation
SDF
Save
netlist
Save
Partition
Netlist
no
yes
no
yes
Save IO
File
(pin
locations)
.tdf
RC Correlation
(StarRCXT->
Apollo->
FE)
flattened prototyping
(FE)
floorplanning
(FE)
hierarchical
prototyping
(FE) (Top Level)
Netlist, Timing
Constraint, Size
IR
drop
analysis (MarsRail)
top
level trial route (
APO)
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
5Confidential-
Security
C
Prototyping
Hierarchical Timing Closure
Fullchip
Verification
Stamp Models
of
Each
Partition
1.Macro Libraries
of
Each
Partition
(.cdump)
2.
Top
Level Netlist
3.Top Level
Timing
Constraints
1.
Standard Cell
Library
2.
Timing
Library
3.
Technology
file
Top Level
Floorplan
Design Import
Load Floorplan
AmoebaPlace
CTS
Trial Route
congestion
OK?
Extract RC
Timing
Analysis
IPO
Is timing
met?
PT:
Budgeting
RC Correlation
Extract RC
SPEF
Setload
Delay
Calculation
SDF
Save
netlist
Save
Partition
Netlist
no
yes
no
yes
Save IO
File
(pin
locations)
.tdf
RC Correlation
(StarRCXT->
Apollo->
FE)
flattened prototyping
(FE)
floorplanning
(FE)
hierarchical
prototyping
(FE) (Top Level)
Netlist, Timing
Constraint, Size
IR
drop
analysis (MarsRail)
top
level trial route (
APO)
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
6Confidential-
Security
C
Hierarchical Timing Closure
Prototyping
Fullchip
Verification
RC Correlation(
FE->
PC)
block
frame view
and
pdb
generation(
APO)
block
level
preCTS
implementation
(PC):
placement, timing
optimization
block
timing model
extraction
top level
preCTS
implementation
(PC):
placement, timing
optimization
top/
block
level
implementation
(
APO):
CTS, track
assign, SDF
RC Correlation(
APO->
PC)
block/top post
CTS
implementation
(PC)
block/top detail
route (
APO):
double via, xtalk,
antenna
fullchip
STA
(PT,
StarRCXT,
NDC)
characterizing
timing-
violated
blocks
(PT)
budgeting
(PT)
PC

netlist

timing constraint
design
import
write boundary
parasitics
PC .SPEF
remove SDF
on
boundary
1.
boundary
net
transition
time
2.
boundary capacitance
load
boundary
parasitics
extract timing
model
PC .SDF
PC
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
6Confidential-
Security
C
Hierarchical Timing Closure
Prototyping
Fullchip
Verification
RC Correlation(
FE->
PC)
block
frame view
and
pdb
generation(
APO)
block
level
preCTS
implementation
(PC):
placement, timing
optimization
block
timing model
extraction
top level
preCTS
implementation
(PC):
placement, timing
optimization
top/
block
level
implementation
(
APO):
CTS, track
assign, SDF
RC Correlation(
APO->
PC)
block/top post
CTS
implementation
(PC)
block/top detail
route (
APO):
double via, xtalk,
antenna
fullchip
STA
(PT,
StarRCXT,
NDC)
characterizing
timing-
violated
blocks
(PT)
budgeting
(PT)
PC

netlist

timing constraint
design
import
write boundary
parasitics
PC .SPEF
remove SDF
on
boundary
1.
boundary
net
transition
time
2.
boundary capacitance
load
boundary
parasitics
extract timing
model
PC .SDF
PC
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
7Confidential-
Security
C
Hierarchical Timing Closure
Prototyping
Fullchip
Verification
RC Correlation(
FE->
PC)
block
frame view
and
pdb
generation(APO)
block
level
preCTS
implementation
(PC):
placement, timing
optimization
block
timing
model
extraction
top level
preCTS
implementation
(PC):
placement, timing
optimization
top/
block
level
implementation
(
APO):
CTS, track
assign, SDF
RC Correlation(
APO->
PC)
block/top post
CTS
implementation
(PC)
block/top detail
route (
APO):
double via, xtalk,
antenna
fullchip
STA
(PT,
StarRCXT,
NDC)
characterizing
timing-
violated
blocks
(PT)
budgeting
(PT)
Create
Lib (Ref = Std)
NetlistIn
load floorplan script
Make Macro
Create
Timing
Model
Load
Timing
Constraint
Load
Timing
CLF
Dump LEF
(
dumpLibLEF.
scm)
.CLF
.CLF
with
clock
port capacitance,
clock port subtype,
port direction
lef2plib
.LEF
PLIB
Read PLIB
write
PDB
PDB
FE

netlist(
simplified)

floorplan script
tdf files

Timing
constraints
(Clock information
only)
APO CTS
PC
metal_
case.
pl
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
7Confidential-
Security
C
Hierarchical Timing Closure
Prototyping
Fullchip
Verification
RC Correlation(
FE->
PC)
block
frame view
and
pdb
generation(APO)
block
level
preCTS
implementation
(PC):
placement, timing
optimization
block
timing
model
extraction
top level
preCTS
implementation
(PC):
placement, timing
optimization
top/
block
level
implementation
(
APO):
CTS, track
assign, SDF
RC Correlation(
APO->
PC)
block/top post
CTS
implementation
(PC)
block/top detail
route (
APO):
double via, xtalk,
antenna
fullchip
STA
(PT,
StarRCXT,
NDC)
characterizing
timing-
violated
blocks
(PT)
budgeting
(PT)
Create
Lib (Ref = Std)
NetlistIn
load floorplan script
Make Macro
Create
Timing
Model
Load
Timing
Constraint
Load
Timing
CLF
Dump LEF
(
dumpLibLEF.
scm)
.CLF
.CLF
with
clock
port capacitance,
clock port subtype,
port direction
lef2plib
.LEF
PLIB
Read PLIB
write
PDB
PDB
FE

netlist(
simplified)

floorplan script
tdf files

Timing
constraints
(Clock information
only)
APO CTS
PC
metal_
case.
pl
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
8Confidential-
Security
C
Hierarchical Timing Closure
Prototyping
Fullchip
Verification
RC Correlation(
FE->
PC)
block
frame view
and
pdb
generation(
APO)
block
level
preCTS
implementation
(PC):
placement, timing
optimization
block
timing
model
extraction
top level
preCTS
implementation
(PC):
placement, timing
optimization
top/block level
implementation
(APO):
CTS, track assign,
SDF
RC Correlation(
APO->
PC)
block/top post
CTS
implementation
(
PC)
block/top detail
route (
APO):
double via, xtalk,
antenna
fullchip
STA
(PT,
StarRCXT,
NDC)
characterizing
timing-
violated
blocks
(PT)
budgeting
(PT)
NetlistIn
*_
cts_
fixed.pdef
PC
netlist .pdef
Load floorplan
script
Load power plan
script
Load
timing
constraints
Read PDEF
(readPDEF3.scm)
Purge clock
net/
default TranDelay
CTS
Report
skew
Dump
PDEF
(dumpPDEF3.scm)
Hierarchical Netlist
Out
Write SDF/Setload
1.floorplan
script
2.power plan
script
3.tdf
FE
FE
timing
constraint
(clock
information
only)
*.
hvout
*_
cts_
fixed.sdf
*_
cts_
fixed.dc
Define
Synchronous
Pin
pdef_pc2apo.pl
pdef_
apo2pc.pl
sdf_
apo2pc.pl dc_apo2pc.pl
Create Lib
(RefLib = Std)
Block
level
Create Lib
(RefLib = Std cell,
generated pdb
library)
Top level
CTS related
files
metal_
case.
pl
PC
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
8Confidential-
Security
C
Hierarchical Timing Closure
Prototyping
Fullchip
Verification
RC Correlation(
FE->
PC)
block
frame view
and
pdb
generation(
APO)
block
level
preCTS
implementation
(PC):
placement, timing
optimization
block
timing
model
extraction
top level
preCTS
implementation
(PC):
placement, timing
optimization
top/block level
implementation
(APO):
CTS, track assign,
SDF
RC Correlation(
APO->
PC)
block/top post
CTS
implementation
(
PC)
block/top detail
route (
APO):
double via, xtalk,
antenna
fullchip
STA
(PT,
StarRCXT,
NDC)
characterizing
timing-
violated
blocks
(PT)
budgeting
(PT)
NetlistIn
*_
cts_
fixed.pdef
PC
netlist .pdef
Load floorplan
script
Load power plan
script
Load
timing
constraints
Read PDEF
(readPDEF3.scm)
Purge clock
net/
default TranDelay
CTS
Report
skew
Dump
PDEF
(dumpPDEF3.scm)
Hierarchical Netlist
Out
Write SDF/Setload
1.floorplan
script
2.power plan
script
3.tdf
FE
FE
timing
constraint
(clock
information
only)
*.
hvout
*_
cts_
fixed.sdf
*_
cts_
fixed.dc
Define
Synchronous
Pin
pdef_pc2apo.pl
pdef_
apo2pc.pl
sdf_
apo2pc.pl dc_apo2pc.pl
Create Lib
(RefLib = Std)
Block
level
Create Lib
(RefLib = Std cell,
generated pdb
library)
Top level
CTS related
files
metal_
case.
pl
PC
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
9Confidential-
Security
C
Hierarchical Timing Closure
Prototyping
Fullchip
Verification
RC Correlation(
FE->
PC)
block
frame view
and
pdb
generation(
APO)
block
level
preCTS
implementation
(PC):
placement, timing
optimization
block
timing
model
extraction
top level
preCTS
implementation
(PC):
placement, timing
optimization
top/
block
level
implementation
(
APO):
CTS, track
assign, SDF
RC Correlation(
APO->
PC)
block/top post
CTS
implementation
(PC)
block/top
detail route
(APO)
:
double via, xtalk, antenna
fullchip
STA
(PT,
StarRCXT,
NDC)
characterizing
timing-
violated
blocks
(PT)
budgeting
(PT)
Create Lib
(RefLib = Std)
Create Lib
(RefLib = Std cell,
generated pdb
library)
NetlistIn
Read PDEF
preRoute
CTS
APO
CTS related
files
generated
after
CTS
Route
Xtalk reduction route
Antenna-
fixing route
PC
netlist .pdef
Block
level
Top level
Define
Synchronous Pin
(
Top
level
only)
*_
cts_
fixed.pdef
Dump
PDEF
(dumpPDEF3.scm)
Write SDF/Setload
*_
cts_
fixed.sdf
*_
cts_
fixed.dc
pdef_
apo2pc.pl sdf_
apo2pc.
pl
dc_apo2pc.
pl
Write SPEF
*_
route.
SPEF
Load floorplan
script
Load power plan
script
1.floorplan
script
2.power plan
script
3.tdf
FEmetal_
case.
pl
PC STA
TSMC
Hierarchical Design
Flow
Diagram
/
TSMC
Reference
Flow
Release 3.0
9Confidential-
Security
C
Hierarchical Timing Closure
Prototyping
Fullchip
Verification
RC Correlation(
FE->
PC)
block
frame view
and
pdb
generation(
APO)
block
level
preCTS
implementation
(PC):
placement, timing
optimization
block
timing
model
extraction
top level
preCTS
implementation
(PC):
placement, timing
optimization
top/
block
level
implementation
(
APO):
CTS, track
assign, SDF
RC Correlation(
APO->
PC)
block/top post
CTS
implementation
(PC)
block/top
detail route
(APO)
:
double via, xtalk, antenna
fullchip
STA
(PT,
StarRCXT,
NDC)
characterizing
timing-
violated
blocks
(PT)
budgeting
(PT)
Create Lib
(RefLib = Std)
Create Lib
(RefLib = Std cell,
generated pdb
library)
NetlistIn
Read PDEF
preRoute
CTS
APO
CTS related
files
generated
after
CTS
Route
Xtalk reduction route
Antenna-
fixing route
PC
netlist .pdef
Block
level
Top level
Define
Synchronous Pin
(
Top
level
only)
*_
cts_
fixed.pdef
Dump
PDEF
(dumpPDEF3.scm)
Write SDF/Setload
*_
cts_
fixed.sdf
*_
cts_
fixed.dc
pdef_
apo2pc.pl sdf_
apo2pc.
pl
dc_apo2pc.
pl
Write SPEF
*_
route.
SPEF
Load floorplan
script
Load power plan
script
1.floorplan
script
2.power plan
script
3.tdf
FEmetal_
case.
pl
PC STA