N.

Ram Reddy,
Surya Pratap Reddy
Sai Rajeev
Email: ramreddy_sanaece@yahoo.com

Sana Engineering College, Kodad

 ABSTRACT

In this paper we explained about “VLSI” design with

overview of “Integrated Circuit” (or) IC and it types and applications .

We are given few details about

1) Size of chip & Circuit complexity.

2) Classification of IC

3) Multi-project chip & its examples, and also

4) VLSI based Electronic device.

INTRODUCTION TO VLSI
As a result of improvements in fabrication technology, Large Scale Integrated (LSI)
electronic circuitry has become so dense that a single silicon LSI chip may contain tens of
thousands of transistors. Many LSI chips, such as microprocessors, now consist of
multiple complex subsystems, and thus are really integrated systems rather than
integrated circuits.

What we have seen so far is only the beginning. Achievable circuit density now
doubles with each passing year or two. Physical principles indicate that transistors can be
scaled down to less than 1/100th of their present area and still function as the sort of
switching elements with which we can build digital systems. By the late 1980s it will be
possible to fabricate chips containing millions of transistors. The devices and
interconnections in such very large scale integrated (VLSI) systems will have linear
dimensions smaller than the wavelength of visible light. New high-resolution lithographic
techniques have already been demonstrated that will enable fabrication of such circuitry.

VLSI electronics presents a challenge, not only to those involved in the

development of fabrication technology, but also to computer scientists and computer
architects. The ways in which digital systems are structured, the procedures used to
design them, the trade–offs between hardware and software, and the design of
computational algorithms will all be greatly affected by the coming changes in integrated
electronics. We belief this will be a major area of activity in computer science on through
the 1980s.

Until recently the design of integrated circuitry has been the province of circuit
and logic designers working within semiconductor firms. Computer architects have
traditionally composed systems from standard integrated circuits designed and
manufactured by these firms but have seldom participated in the specification and design
of these circuits. Electrical Engineering and Computer Science (EE/CS) curricula reflect
this tradition , with courses in device physics and integrated circuit design aimed at a
different group of students than those interested in digital system architecture and
computer science.

VLSI DESIGN
VLSI is a very large scale integrated . It is nothing but a chip (or) Integrated
Circuit. In this present generation VLSI plays a major role.
 What is meant by INTEGRATED CIRCUIT?

Integrated circuit (or) IC is a miniature, low cost electronic circuit consisting of

active and passive components that are irreparably joined together on a single
crystal chip of silicon.

 Applications of Integrated Circuits.

1) Miniaturization and hence increased equipment density.

2) Cost reduction due to batch processing.
3) Increased system reliability due to elimination of soldered joints.
4) Improved functional performance (as it is possible to fabricate even
complex circuits for better characteristics.
5) Matched devices.
6) Increased operating speeds (due to the absence of parasitic capacitance
effect)
7) Reduction in power consumption.

Classification of IC’s

Integrated circuits offer a vide range of applications and could be broadly

classified
I) Digital Ics
 II) Liner ICs.

Based on above requirements, two distinctly different IC technologies namely

MONOLITHIC Technology and HYBRID technology have been developed.

In monolithic integrated circuits all circuit components both active and passive
elements and their interconnections are manufactured into (or) on top of a single
chip of silicon.

In Hybrid circuits, separate components parts are attached to a ceramic substrate

and inter connected by means of either metallization pattern (or) wire bonds.

Classification of ICs

 IC Chip size and Circuit Complexity.

* The first transistor was a “Germanium” allay Jn transistor, developed in the

year 1948.

“Silicon devices” come up in the mid-to late 1950s and the concept of integrated
circuit was introduced early 1960s by both Texas instruments and Fairchild
Semiconductors. Since that time, the size and complexity of ICs have increased
slapping show brief chronology.

Invention of Transistor (Ge) - 1948

Development of Silicon Transistor - 1955-1959
Silicon Planar Technology - 1959
First ICs , Small scale Integration (SSI) - 1960
3 to 30 gates/chip.

Medium scale integration 30 to 200 gates/chip - 1965-1970

Large scale Integration 300 to 3000 gates/chip - 1970-1975
Very Large scale Integration 3000 gages/chip - 1975
First commercial VLSI chip: 64K RAM - Late 1970s
 256K Ram - Early 1980s

* 512K RAM, IMROM, very high speed GaAs Ics.

* The chip areas range from Imm2 (1600mis2)
The SSI chip to Icm2 (160,000 mil2) for the LSI chip

Integrated Circuit Chip (a) SSI Chip (b) MSI Chip (c) VLSI chip

IMPLEMENTING INTEGRATED SYSTEM DESIGN: From circuit topology to Patterning

Geometry to wafer Fabricator.

MULTIPROJECT CHIP:

• A large , complex VLSI system could be quickly and successfully developed by

designers able to easily implement and test prototype of its subsystem. The separate
systems can be implemented, tested, debugged and then merged together to produce
the over all system layout.

• A Photomicrograph of a Caltech class project chip containing 15 separate student

projects. The individual projects were simply merged in together on to are moderate
sized chip layout, approximately ‘3 mm’ by 4 mm’ and implemented simultaneously
as one chip type.

• Following fabrication the wafers containing such multi project chips are scribed,
deced and then divided up among the participants. The typical minimum fabrication
shun yields about 10 to 20 wafers. Each wafer ~ 7.5 to 10 cm in diamter. Thus even
a minimum run provides a few thousand chip, and each participant ends up with many
chips.

Organizing a multi project chip involves.

1) Creating the layout of starting frame, into which the various projects are to be
merged.
2) Gathering , relocating and merging the project layout into the starting frame to
create one design five and generating from this the PG files for the overall project.
Chip.
3) Documenting various parameters and specs to be used during mask marking
and fabrication.

• The contents of the starting frame must be carefully worked out to meet the
requirements and constrains of the chosen mask house and fab line . The important
factor for turns and time for the entire mask and fab sequences may be reduced to
• same extent by repeatedly using a relatively standard starting frame, which then
become familiar to all those involved. Some typical 1978 values for the time involved
3 to 5 weeks for mask making and then 3 to 4 weeks for fabrication

Photo MIicrograph of Caltech Class Project chip

Examples of multi project chips.

• Although several of the projects in the set are fairly large, all were individually
designed to yield chip sizes packagable in standard 40 pin packages., which can hold
chips up to ~ 7 mm squarer. The pattern generator at the intended mask house was a
Ge A/D.W.Mann 3600, and the photo repeater was a Mann 3696 together this
equipment can produce 10 X reticle having field sizes as large as 10cm square and
can reduce, step and repute these at a maximum of 10m *(x,y) intervals into masks.
Therefore, the 3600/3696 can provide masks for square chips up to 10mm *(10,000
m) on a side.

• A 10 mm square chip can hold the patterns of several normal sized chips. By
including “interior Scribe Lines” in the starting frame, as indicated in one reticle a
number of different chips. In the example x and y stepping distances were both ~
9700 microns. Fabricated wafers are scribed and deiced on all scribe lines, including
the interior ones, to yield chips of typical sizes.

Examples were input contact pads with attached “lightning arrestor” circuits to protect
the input MOSFET gates, and output drivers snaked around and attached to output
pads. A square pad ~ 75 mm on a side is a rather small bonding target, 125um on a
side is easier for the native to hit. Perhaps ~ 100 um square pads separated by ~ 75 um
is a good compromise, and these should be at least 2um from any other metal lines to
avoid cutting (as shorting the lines when boundary metal paths (1978) are ~ 1 um thick
and carry ~ 1ma per um width.

Metal conductors must be wide enough so that the current density limit is not exceeded
(be sure to check major VDD and GND Paths). Power densities should be low enough so
that thermal problem do not develop. Even in large systems composed of closely spaced
boards fully populated with packaged chips, a power dissipation of ~ 0.05 watts per cm 2
of board area is easily handled with air cooling. Conventional packaging techniques
require about 20 cm2 of board area for each 1cm2 of silicon chips are chip dissipating
less than 1 watt per cm2 of trial chip area require no special cooling consideration.

The scribe lines on this chip set were laid out as 140 um vide cuts down to 160 um vide
paths on the diffusions level, to provide lanes free of oxide for scribing (or) sawing. Metal
paths 30um vide were than laid out straddling the boundary.

A software blow back of the metal mask PG files of another project set, organized at
caltech, the total area of this multi-project chip set is ~ cm 2 . It is sub divided in to four
major sections. The lower right quadrant contains the cm2 data path chip described lay
out u/ = 2.5 um.

Collaborative Xerox (PARC)/ Caltech Multiproject Chip

MODERN VLSI DESIGN

Features:
Xilinx Spartan 3 FPGA XC3S-400 based
144 user programmable general purpose I/O
400 K Gates capacity.
JTAG/Slave serial based programming facility.
Sample Programs in VHDL.

ADC & DAC Interface:

12 Channel 12 bit high speed serial ADC with 4 msps throughput.
8 channel 12 bit high speed serial DAC.

PWM, Capture & GPIO Liens;

Software controlled 8 PWM output.
Software controlled 6 Capture input.
Software controlled 8 GPIO

Other Features
I C& SPI Serial ports
Opto isolated RS 232 serial port.
LCD & Matrix Keypad module

Applications:
AC-DC Converter ( 1O & 3 O) applications.
AC—AC Regulator, cyclo converter applications.
DC-DAC Inverter applications.
DC-DC Chopper applications.
V/F Control of 1 O/ 3 O Induction Motor.
Space Vector Control of 3 O Induction Motor.
DC Motor Control
BLDC Motor Control.