Snubber-less NPC inverter by a novel reduction technique of parasitic

inductance for magnet power supplies

K. Koseki
n
, Y. Morita
High Energy Accelerator Research Organization (KEK), 1-1 Oho, Ibaraki, Tsukuba 305-0801, Japan
a r t i c l e i n f o
Article history:
Received 28 February 2014
Received in revised form
21 April 2014
Accepted 23 May 2014
Available online 2 June 2014
Keywords:
Magnet
Power supply
Parasitic inductance
Surge voltage
NPC inverter
a b s t r a c t
The effects induced by parasitic inductance were studied in a neutral point clamped (NPC) inverter. The
energy stored in the parasitic inductance by the output current causes a surge voltage during the turn-
off period of semiconductor switches. The effect is serious in a magnet power supply for which a large
excitation current is required. It is predicted by a circuit analysis that the parasitic inductance causes an
electrical breakdown of the semiconductor switches. It was found that the most promising way to
mitigate the effect is to reduce the parasitic inductance. With newly developed circuitry and layout of an
NPC inverter, cancelation of the induced magnetic eld, which is based on Ampere's circuital law, in
power devices has been accomplished. The newly developed NPC inverter has been operated success-
fully with both a resistive dummy load and the dipole magnets in the main ring synchrotron at the
J-PARC facility.
& 2014 Elsevier B.V. All rights reserved.
1. Introduction
The T2K experiment [1] aims to search for CP violation in the
lepton sector following the precision measurement of the last
unknown mixing angle,
13
, in neutrino oscillations [2]. For this
purpose, we investigated a beam-power upgrade for future multi-
MW operation at the main ring of J-PARC [3] by reducing the
accelerator's operational cycle from the current value of about 2.5
1 s. Therefore, a new magnet power supply with a shorter repetition
cycle needs to be developed. To enable the stable acceleration of
MW-class beams and to deliver protons not only to the neutrino
facility by fast extraction [4,5] but also to the hadron facility by slow
extraction, the new magnet power supply should generate an
excitation current with a ripple of less than 2 ppm. Recently, a
new operational method that uses a neutral point clamped (NPC)
inverter to reject the disturbing effect of common-mode noise was
proposed [6]. It also has been reported that by using an NPC inverter
with reduced switching sequences, a magnet power supply with
sub-ppm ripple performance can be obtained.
In a conventional inverter circuit, 4 identical insulated gate
bipolar transistors (IGBT) are used to form a full-bridge circuit. By
proper gate signals, the conventional inverter can generate 3 out-
put voltages: Vc, 0 V and Vc. Here, Vc is the charging voltage
of the capacitor bank. In contrast in an NPC inverter, it is possible
to generate 5 output voltages (Vc, Vc/2, 0 V, Vc/2 and Vc)
by increasing the number of IGBTs for the precise control of the
output voltage or the reduction of harmonic components. There-
fore, the NPC inverter requires twice as many IGBTs than that of
the conventional inverter circuit. Because of the increased number
of high-power devices compared to a conventional inverter circuit,
an NPC inverter is likely to have a larger parasitic inductance
caused by the wiring between each high-power component. A
certain amount of magnetic energy is stored in the parasitic
inductance by the excitation current. During the turn-off period,
the fact that the excitation current in the IGBT is blocked causes a
spike voltage, also known as a surge voltage, to be induced in the
IGBT. The effect is more serious for a larger current, such as in an
accelerator magnet power supply. It is often observed that the
surge voltage induces undesired operational performance, such as
an increased switching loss or, at worst, an electrical breakdown of
the IGBT. Conventionally, a snubber circuit is used to suppress the
disturbing effects of the surge voltage in an NPC inverter [7,8].
Although the surge voltage is sufciently reduced by adoption of
the snubber circuit, the resulting slow switching time is a
disadvantage of this method.
To track the beam energy during acceleration, the magnet
power supply must generate a pattern current with sufcient
precision. For this purpose, a pulse width modulation (PWM)
control is utilized, which actively controls the widths of the pulsed
output voltages from the inverter. On the one hand, during the
period of beam extraction from the synchrotron, relatively wider
pulsed voltages are generated for a larger excitation current. On
the other hand, a narrow pulse width is required for a smaller
excitation current during the period of beam injection into the
Contents lists available at ScienceDirect
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Nuclear Instruments and Methods in
Physics Research A
http://dx.doi.org/10.1016/j.nima.2014.05.095
0168-9002/& 2014 Elsevier B.V. All rights reserved.
n
Corresponding author. Tel.: 81 29 864 5200 4698.
E-mail address: kunio.koseki@kek.jp (K. Koseki).
Nuclear Instruments and Methods in Physics Research A 761 (2014) 8691
synchrotron. Moreover, to effectively reduce the ripple compo-
nents in the excitation current by the lter circuit, a higher
switching frequency of the NPC inverter is required in the new
magnet power supply for J-PARC. For example, a charging voltage
of 1.6 kV for the NPC inverter of a QFP focusing magnet is required
for future 1 Hz operation. To generate an output voltage of 11.2 V
during the beam-injection period, which corresponds to a duty
factor of 0.7% for the NPC inverter, a pulse width as narrow as
1.4 s is required. Therefore, the IGBTs must have a sufciently fast
switching speed. The PWM system can dictate the width only by
assuming that the inverter generates pulses with an ideal rectan-
gular shape. Because of the slow switching speed with a snubber
circuit, pulsed output voltages with an ideal rectangular shape are
hard to obtain. Therefore, especially during the beam-injection
period, precise control of the output voltage is disturbed by
adoption of a snubber circuit. Thus, use of a snubber circuit in the
inverter circuit is not suitable for the new magnet power supply.
Therefore, we developed a new technique to reduce the parasitic
inductance in an NPC inverter. Some parameters of the newly
developed NPC inverter are summarized in Table 1. In the devel-
oped NPC inverter, a high-power IGBT with a sufcient switching
time of 300 ns is employed.
In this paper, we present our investigation on the effects
induced by the parasitic inductance in the NPC inverter by using
circuit simulations. Details of the technique to reduce the parasitic
inductance are also discussed. Experimental results are reported
from high-power operation with a resistive dummy load to
conrm the validity of the newly developed technique. Results
are also reported from a high-power test operation using 16
bending magnets at the J-PARC facility to conrm the stability of
the developed NPC inverter.
2. Current-blocking surge
2.1. Parasitic inductance
The circuit schematic of an NPC inverter and its operational
sequences are depicted in Fig. 1. IGBTs are represented by S1-1, S1-2,
S2-1, S2-2, S3-1, S3-2, S4-1, and S4-2 in the gure. Parasitic induc-
tances are indicated by L
cp
, L
cn
, and L14. Stored voltages in the two
capacitor banks are represented by Vc/2 and Vc/2, respectively.
Sequence (a): simultaneously conducting S1-1, S1-2, S4-1 and
S4-2, the charged voltage of Vc in the capacitor bank is applied to
the output terminals. Correspondingly, an excitation current
indicated by the dashed arrow ows to the load. In this operation
sequence, a certain amount of magnetic energy is stored in the
parasitic inductances.
Sequence (b): by turning off S1-1 and S4-2, the excitation
current from the capacitor bank is blocked. Therefore, the current
loop changes as depicted by the dashed arrow. The NPC inverter in
this operational sequence is in the ywheel mode, in which no
voltage is induced at the output terminals. At the switching time
of this operational sequence, stored magnetic energy in the
parasitic inductances, L
cp
, L
cn
, and L14, induces surge voltages
at each IGBT because of the sudden change of the current.
During the switching period from sequence (a) to (b), the
excitation current is blocked by 2 IGBTs, S1-1 and S4-2. Corre-
spondingly, because of the sudden change in the current, parasitic
inductances, L
cp
, L
cn
, and L14, induce surge voltages. The ampli-
tude of the voltage applied to an IGBT is expressed as
V
s11

1
2
V
c
L
cp
L1
dI
dt
: 1
Here, I is the current blocked by S1-1. From Eq. (1) it can be
seen that in a power supply with a large output current, such as
for a synchrotron magnet, the effects induced by the parasitic
inductance are strong. By increasing the peak amplitude of the
voltage during the switching period, the switching loss in an IGBT
is increased. In the worst case, with a surge voltage larger than the
rated voltage of the IGBT, an electrical breakdown can occur.
To conrm the validity of Eq. (1) and to investigate the nature
of the surge voltage, we performed simulation studies based on
the circuit schematic in Fig. 1. In the simulation, an output current
of 300 A which is supplied from a capacitor voltage of 1400 V to a
resistive load of 4.7 is switched by IGBTs in the NPC inverter. The
IGBT is modeled by an ideal switch without parasitic elements,
such as the output capacitance and turn-on resistance. The
CollectorEmitter voltages of S1-1 for various parasitic induc-
tances (Lcp, Lcn, L1, L2, L3 and L4) are shown in Fig. 2.
The results show a linear dependence of the peak amplitude of
the surge voltage on the parasitic inductance. A current depen-
dence of the surge voltage is also simulated. The result is shown in
Fig. 3. Various load resistances are used to simulate the Emitter
current of 400 A (a
0
), 300 A (b
0
), 200 A (c
0
), and 100 A (d
0
) by a
charging voltage of 1400 V to the capacitor bank. CollectorEmitter
voltages for the corresponding Emitter currents are indicated by
(a), (b), (c), and (d).
In Fig. 2, the surge voltage superimposed on the CollectorEmitter
voltage is increased linearly with the increase of the parasitic
inductance. Moreover, a linear increase of the surge voltage with
the increase of the Emitter current is observed in Fig. 3. Therefore,
the simulation studies conrm the validity of Eq. (1). To solve the
problem induced by the current-blocking surge voltage, a snubber
circuit is commonly used. However, it is clear from Eq. (1) that
reducing the parasitic inductance is a natural approach. With
sufcient reduction, a snubber-less NPC inverter that is capable of a
faster switching frequency for lower output ripple in the excitation
current is required.
2.2. Reduction method
To reduce the parasitic inductance, it is essential to reduce the
induced magnetic eld by a current loop that includes two
capacitor banks, S1-1, S1-2, and S4-1, S4-2 (see Fig. 1(a)). From
Ampere's circuital law
Z
Hds
i
n
i
I
i
: 2
It is found that the induced magnetic eld is canceled by two
currents with opposite directions but the same amplitude. Here,
I
i
is the current, and n
i
is the number of turns of the ith circuit.
H indicates the total induced magnetic eld. To apply the reduc-
tion method expressed by Eq. (2), power devices and wiring bus
bars with the same current amplitude should be placed side by
side. Thus, the reduction of the parasitic inductance is difcult in a
conventional NPC inverter because S1-1 and S4-2 are placed in
diagonally opposite positions, as shown in Fig. 1. Therefore, new
circuitry for an NPC inverter is proposed. The circuit schematic
is shown in Fig. 4. In the gure, the current loops in sequences
Table 1
Parameters of the developed NPC inverter.
Peak output power 300 kVA
Maximum charging voltage 1800 V
Peak output current 300 A
Repetition rate 5 kHz
IGBT CM1000DUC-34NF
Rise/fall time 300 ns
K. Koseki, Y. Morita / Nuclear Instruments and Methods in Physics Research A 761 (2014) 8691 87
(a) and (b) are depicted by solid and dashed arrows, respectively.
Although twice as many capacitor banks are used in the new
circuit, S1-1 and S4-2 can be easily placed in contiguity with each
other. Therefore, cancellation of the induced magnetic elds
can be accomplished by two wiring bus bars for S1-1 and S4-2.
The structural layout of the new NPC inverter is shown in Fig. 5.
The wide-solid arrow indicates the current loop in sequence (a).
The ywheel diodes are removed from the gure for simplicity.
3. Evaluation
The previous chapter showed that reduction of the parasitic
inductance in an NPC inverter is important to secure stable
operation. For this purpose, new circuitry and its structural design
for an NPC inverter were presented. With this newly proposed
innovative technique, an NPC inverter that is capable of high-
power operation has been developed as shown in Fig. 6.
We conducted a high-power test operation with a resistive
dummy load of 4.6 to evaluate the operational performance of
the newly developed NPC inverter. Although the synchrotron mag-
nets are the large inductive load, the resistive load with compatible
impedance seems to be sufcient to evaluate the voltages and
currents in the IGBT. An Emitter current of about 300 A, which was
supplied from a capacitor voltage of 1400 V, was switched by IGBTs
in the newly developed NPC inverter. The results are shown in Fig. 7.
Results from simulation with the parasitic inductance of 250 nH are
Fig. 1. Circuit schematic of a conventional NPC inverter.
Fig. 2. Simulated surge voltages of S1-1 for various parasitic inductances (Lcp, Lcn,
L1, L2, L3 and L4) of 400 nH (a), 300 nH (b), 200 nH (c) and 100 nH (d). The charging
voltage of the capacitor bank was 1400 V in the simulation. Emitter current of S1-1
is also depicted in (e).
Fig. 3. Simulated surge voltages of S1-1 for various emitter currents. The parasitic
inductances (Lcp, Lcn, L1, L2, L3 and L4) were 300 nH in the simulation.
Fig. 4. Schematic of the proposed circuitry of an NPC inverter. Solid and dashed
arrows indicate the current loop in sequences (a) and (b), respectively.
K. Koseki, Y. Morita / Nuclear Instruments and Methods in Physics Research A 761 (2014) 8691 88
also depicted in Fig. 8 for a comparison between the measurement
and the simulation.
From the peak value of the CollectorEmitter voltage of about
900 V (line (a) in Fig. 7), which is less than the absolute maximum
rated voltage of 1700 V for the IGBT, stable operation is conrmed.
The switching time was also measured by the Emitter current
(b) to be about 280 ns, which is consistent with the specication of
300 ns in the data sheet. By a comparison between the measured
(line (a) in Fig. 7) and simulated (line (a) in Fig. 8) Collector
Emitter voltage, fairly good agreement is also conrmed. There-
fore, each of the parasitic inductances (Lcp, Lcn, L1, L2, L3 and L4 in
Fig. 1) is estimated to be about 250 nH. It was difcult to secure a
stable operation without snubber circuits in a conventional NPC
inverter with the existing technology. The newly developed NPC
inverter demonstrated the snubber-less operation by a sufcient
reduction of the parasitic inductance with the proposed method.
Fig. 5. Structural drawing of the proposed NPC inverter. Solid arrow indicates the current loop in sequence (a).
Fig. 6. Photograph of the developed NPC inverter with reduced parasitic
inductance.
Fig. 7. (a) Measured CollectorEmitter voltage and (b) Emitter current of S1-1
during high-power test operation with a dummy load.
Fig. 8. (a) Simulated CollectorEmitter voltage and (b) Emitter current of S1-1 with
the parasitic inductance of 250 nH.
K. Koseki, Y. Morita / Nuclear Instruments and Methods in Physics Research A 761 (2014) 8691 89
The temporal evolution of the power dissipation in the IGBT
during the turn-off period was also calculated by multiplying the
measured CollectorEmitter voltage and Emitter current (Fig. 9).
By integrating the result over time and multiplying by the switch-
ing frequency of 4 kHz, the switching loss during the turn-off
period is estimated to be about 200 W. From the thermal resis-
tance of about 20 K/kW of an indirect-water cooling system and of
the IGBT itself, the estimated temperature increase in the IGBT is
about 4 K. Stable operation is also conrmed from the viewpoint of
the temperature increase.
4. High-power operation at J-PARC
To conrm stable operational performance, the developed NPC
inverter was installed into a prototype magnet power supply.
The circuit schematic of the magnet power supply is depicted in
Fig. 10. The prototype magnet power supply consists of a 3-phase
input transformer with an output power of 300 kVA, a full-bridge
diode rectier, a 90 mF aluminum electrolytic capacitor bank, the
developed NPC inverter, and a lter circuit. Parameters of the
prototype magnet power supply are summarized in Table 2. High-
power operation with 16 bending magnets, each having an
inductance of 100 mH and a coil resistance of 40 m, was
conducted in the main ring synchrotron at the J-PARC facility with
a peak excitation current of 100 A. The charging voltage for the
capacitor bank was 1800 V in this operation. The measured
excitation current and the output voltage are shown in Fig. 11
(a) and (b), respectively. From these results, stable operation of the
magnet power supply and thus the newly developed NPC inverter
has been conrmed.
5. Conclusion
To secure stable acceleration during future MW-class beam
operations at J-PARC, a new magnet power supply with current
ripple of less 2 ppm is required. For this purpose, we proposed a
new operational method of an NPC inverter for the rejection of
common-mode noise. The NPC inverter is likely to have a larger
parasitic inductance caused by the wiring than would a conven-
tional inverter because of the number of power devices. The surge
voltage induced by the parasitic inductance causes serious effects
on the operation of the NPC inverter, such as increased switching
loss or, at worst, electrical breakdown of the power devices.
Fig. 9. Temporal evolution of the power dissipation in the IGBT (S1-1) during the
turn-off period.
Fig. 10. Circuit schematic of the prototype magnet power supply with the newly developed NPC inverter.
Table 2
Parameters of the prototype magnet power supply
with sub-ppm output ripple.
Charging voltage 1800 V
Maximum current 300 A
Repetition rate 1 Hz
Filter inductance 1.5 mH
Filter resistance 3
Filter capacitance 1.5 mF
Switching frequency of NPC inverter 4 kHz
Capacitor bank 90 mF
Fig. 11. (a) Measured excitation current and (b) output voltage by the newly
developed magnet power supply.
K. Koseki, Y. Morita / Nuclear Instruments and Methods in Physics Research A 761 (2014) 8691 90
To mitigate the disturbing effects by means of reducing the
parasitic inductance, new circuitry and structural layout of an
NPC inverter was developed. With a sufcient reduction, an NPC
inverter was developed that operated successfully with both a
resistive dummy load and the dipole magnets in the main ring
synchrotron at the J-PARC facility. It should be mentioned that
the newly developed method is applicable not only for the NPC
inverter but also for the conventional inverter to reduce the
parasitic inductance and to mitigate the disturbing effect by the
current-blocking surge voltage.
Acknowledgments
The authors are grateful for the continued support of Professors
H. Kobayashi, M. Yoshioka, and H. Matsumoto. One of the authors
(K. Koseki) expresses his gratitude to Dr. Y. Kurimoto, Mr. Kondo
and Mr. Kageshima for their valuable cooperation in developing
the NPC inverter.
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