Professional Documents
Culture Documents
F. Maloberti
Department of Electronics
Integrated Microsystem Group
University of Pavia, 27100 Pavia, Italy
franco@ele.unipv.it
tel. +39-382-505205; fax. +39-0382-505677
474 EE Department
+
_
A(v+ - v )
Z1
V0
Z3
+
Z4
V0
Z4 Z1 + Z2
Z2
= V 2 --------------------- --------------------- V 1 ------Z3 + Z4 Z1
Z1
If the gain of the op-amp is not infinite, an error of the order of 1/A
results. This error must be smaller or comparable to the
impedance matching.
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_
- Q (t)
+
g
+
Q
v 0 ( 0 ) = ------C0
v
m i
r
0
C0
+
1
1
v i ( 0 ) = Q ------- + ----
C0 C
Q
V i ( t ) = V 0 ( t ) ---C
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g m
v 0()
Q
v 0 ( ) ---- = --------------C
r0
gmr 0
Q
v 0 ( ) = ---- -----------------------C 1 + gmr 0
Q
+
C
g
r
0
v
m i
C0
v 0 (t)
C
------gm
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PERFORMANCE CHARATCTERISTICS
Actual op-amps deviate from ideal behavior. The differences are described by the performance characteristics.
DC differential gain:
is the open loop voltage gain measured at DC with a small differential
input signal. Typically Ad = 80 - 100 dB
vout
vi n
+
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in
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vps
Typically:
PSRR = 90 dB (DC)
PSRR = 60 dB (1KHZ)
PSRR = 30 dB (100 KHZ)
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vout
+
vn
[dB]
+
|vn|
vout
log(f)
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|A 0|
[dB]
+
vout
fT
log(f)
Slew rate:
it is the maximum slope of the output voltage for a steply signal applied at the
input. Usually measured with the op-amp in the buffer configuration. The positive slew rate can be different from the negative slew rate, depending on the
specific design. Typically 5-20 V/sec. For micropower operations they drops
to much lower levels.
v
out
vout
slope
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Settling time:
if the phase margin is not good enough the response to an input step
can be affected by some ringing. The settling time is the time required
to settle the output within a given range (usually 0.1%) of the final
value.
Power dissipation:
it depends on the request of speed and bandwidth of the circuit. Typically, for 5 V supply, is around 1 mW. For lower supply the power consumption doesnt scale proportionally
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Technology
0.8 m CMOS
Supply voltage
3.3 V
DC gain
80 dB
gain-bandwidth
20 MHz
Slew rate
5 V/sec
400 n sec
CMRR
40 dB
PSRR, DC
90 dB
PSRR, 1 kHz
60 dB
30 dB
Offset
6 mV
2V
Output swing
2.5 V
Power dissipation
1 mW
Area
100 x 100 m
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Differ.
Gain
Differ.
S. End.
2nd gain
Stage
Output
Stage
Key requirement:
Need absolute stability in unity gain closed loop conditions when
driving maximum load.
Use minimum number of gain stages.
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MB
I Ref
M1
M2
M6
C c Out
M5
M3
M4
15
DC offset:
The input offset is composed of two terms:
Systematic offset
Random offset
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Systematic offset:
It is assumed that the device are perfectly matched.
1/2 M7
M6
Out
M1
M5
M3
17
Random offset:
Due to the geometrical mismatching and process dependent
inaccuracies.
-A 1
vos1
-A 2
vos2
v os
v os2
= v os1 ----------- v os1
A1
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R1
I
V = I 1 R 2 I 2 R 2 = --- R
2
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1 I R
v 0s = --- ---------- -------2 g m1 R 0
Texas A&M University
19
Bipolar:
I
------- 26mV
gm
Mosfet:
V GS V T h
I
------- = ----------------------------- 150 300mV
2
gm
Assuming:
R
----------- = 0.01
2R 0
it results:
v os, bip = 0.26mV
v os, MOS = 1.5 3mV
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DD
M7
MB
I Ref
M1
M3
C c Out
M2
4
3
vn-
M6
M5
M4
DD
21
22
n
VDD
rds6
v-n
M5
It results:
v out
1 g m5
= -------------------------------------------+
+
r
1
g
m5
ds6
vn
r ds6
v out
= ------------------------------------ 1
---------1 g m5 + r ds6
vn
23
v 0 = [ v n V n ]
VDD
C+
CI
vout
C-
VSS
24
Cc
I1
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P2
I2
25
R
g v
m1 in
Cc
C
1
R2
g
C2
v
m2 1
v 1 ( g 1 + sC 1 ) + ( v 1 v 0 ) sC c + g m1 v in = 0
v 0 ( g 2 + sC 2 ) + ( v 0 v 1 ) sC c + g m2 v 1 = 0
sC
1 ----------cg m2
V0
--------- = g m1 R 1 g m2 R 2 ----------------------------------------------------------------------------------------------------------------------------------------2
V in
1 + sR 1 R 2 g m2 C c + S R 1 R 2 [ C 1 C 2 + ( C 1 + C 2 ) C c
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The circuit displays two poles and a zero in the right half plane.
1
p 1 ---------------------------------g m2 R 2 R 1 C c
g m2 C c
p 2 --------------------------------------------------------C 1C 2 + (C 1 + C 2)C c
g m2
z = + ---------Cc
since in practice Cc > C1; Cc C2 and gm1 > 1/R1; gm2 > 1/R2 it results:
1
p 1 --------------R 1C 1
g m2
1
p 2 ---------- --------------C 2 R 2C 2
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The locations of the second pole p2 and of the zero with respect to wT
are derived by considering:
g m2 C c
p2
=
---------- ------- for stability > 2 to 4;
------g m1 C 2
T
m2
z = g
---------------g m1
T
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[dB]
log(f)
log(f)
-90
-180
-270
29
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I2
I2
Disadvantages:
Area
Power dissipation
Actually creates a doublet in the feedback path. Potentially not stable.
Alternative, a substrate emitter follower may be used. (The bipolar
transistor is smaller and has higher gm)
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R z Cc
It results:
V 0 A 0 [ 1 + s ( R z 1 g m2 ) C c ]
--------- ----------------------------------------------------------------------V in
s
s
1 + ----1
+ ------
p 1
p 2
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V0
V1
1
1
g m2 = ------- + ------Rn Rp
VS S
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In non saturation:
W
1
------- = k ' n ------ [ V DD V 1 V Th, n ]
L n
Rn
W
1
------- = k ' p ------ [ V 1 V ss V Th, p ]
L p
Rp
W
------ and ------ such that:
Choose W
W
W
k ' n ------ = k ' p ------
L n
L p
and:
W
g m2 = k n ------ [ V DD V SS V T h, n V T h, p ]
L n
34
SLEW RATE
M4
M3
M5
M1
M2
Cc
IB2
IB1
CL
V
= ----------+t
max
IB1
= -------Cc
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max
IB2
= ---------------------Cc + CL
Since
g m1
= ---------- ,
Cc
it results
IB1
SR = ---------- T = ( V GS 1 V Th ) T
g m1
For
T = 2 5 10
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Telescopic cascode:
J DC gain (gmrds)2
J Low power consumption
J Only one high impedance node:
compensated with a capacitance load
(if necessary)
L Low output swing
L Reference of the input close to the
negative supply
L Two bus lines (VB1, VB2)
B1
M7
M8
M5
M6
M3
+
VB2
M1
M4
M2
M9
L 5 Transistors in series
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Mirrored cascode:
M10
M12
M2
M1
VB1
M13
M11
M3
M4
M5
M6
M7
M8
Out
B2
M9
V outmax = V GS 7 + V sat
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M11
VB3
_
M2
M1
M3
B2
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M9
M4
M5
M6
M7
M8
VB1
Out
40
M11
VB3
_
+
M2
M1
VB1
M4
M3
M5
MA
M6
Out
B2
M9
M8
M7
MB
41
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Single stage:
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CLASS AB AMPLIFIER
Class AB: a circuit which can have an output current which is larger
than its DC quiescent current.
Two stages amplifier with class AB second stage
M6 and M7 act as a level
shifter
M8 and M9 act as a class AB
push-pull amplifier
M4
M3
M8
M6
M1
M2
M9
g m8 + g m9
A 2 = ------------------------------g ds8 + g ds9
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VB
M5
M7
44
The quiescent current in the output stage is bias voltage and technological
variation dependent.
V DD = V GS 8 + V GS 6 + V GS 9
45
M5
M6
VB
I 1 = I 2 = I Bias
M7
M2 M3
for Vin = 0
M1 M4
and I2
I out = K 8, 9 I 1 K 5, 6 I 2
IB
VB
VB
M10
VB
M8
M9
IB
46
2 W
2 W
V B + V in = V GS 2 + V GS 4 = V T h, n + V T h, p + ------- ------ + ------- ------ I 2
k ' p L 4
k 'n L 2
V B V in = V GS 1 + V GS 3
2 W
2 W
= V T h, n + V T h, p + ------- ------ + ------- ------ I 1
k ' p L 1
k 'n L 3
It results:
I out = K 8, 9 ( I 1 I 2 ) = K 8, 9 V B V in
Iout
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Vin
47
M2
gm2 (vin - vA )
A
M4
-gm4 v
A
g m2 ( V in V A ) = g m4 V A
VA
I out = g m4 V A
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g m2 V in
= ---------------------------g m2 + g m4
g m2 g m4
= ---------------------------- V in = G m V in
g m2 + g m4
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in R
in+ R
+
out
in - R
+ - +
out -
out
C
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J Noise from the power supply and clock feedthrough are common
mode signal.
J The output swing is (Vmax+ - Vmax- = 2Vmax) doubled. Since the
noise is unchanged, the dynamic range improves by 6 dB.
L Single ended to differential and double ended to single ended
converters are necessary
L Larger area
L More bussing of bias lines
L Common mode feedback is necessary
SE/DE
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Different.
Processor
DE/SE
50
The blocks SE/DE and DE/SE increase the complexity and introduce
noise. Differential approach is convenient if the differential processor
contains more than 4 stages.
C
in R
in+ R
+
out
in - R
+ - +
out
out
The feedback around the op-amp control the difference of the input
terminal voltages and not their mean value. In turn, there is no control
on the output common mode voltage.
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M10
M11
VB3
_
M2
M1
M3
Out-
M5
B2
M9
M7
VB1
M4
Out+
M6
VB4
M8
VB5
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B2
CMFB
or VB3 or VB5
52
M3
V+
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M1
M2
V-
53
2
1 W
I 2 = --- k ' ------ [ 2 ( V - V Th ) V DS V DS ]
L 1
2
2
1 W
I out = I 1 + I 2 = --- k ' ------ [ V B V DS V Th ]
L 3
2
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M9
VB1
M10
_
+
M1
M2
M3
V B2
V
V
B3
M5
B3
M7
V B5
VCM
M4
Out -
M11
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Out +
M6
M8
M12
55
M9
VB1
+
V B2
Out
M10
_
M1
M2
M3
M4
V B3
V B4
V B5
M6
M5
M8
M7
M11
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Out +
M12
56
Problems:
Dynamic range
Linearity
Compensation of the non linearities of the n-channel and p-channel
CMFB cell.
V+
out
I
I
V-
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V+
I Ref
1
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VI Out
2
C
C'
2
1
2
1
2
C
VCM
58
MICROPOWER OP-AMPS
Required in battery operated system (pocket calculators, pace makers,
hearing aids, electronic telephone, ...)
Consumption < 1 A
Use of MOS transistors in weak inversion (subthreshold)
Low current has, as consequence, low slew rate.
C
M5
1
M3
M1
M4
M6
M2
B/C
M7
M8
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M4
M6
M5
M1
D(I 2-I 1)
D(I 1-I 2)
M2
M7
1
M8
I
Basic idea:
Generate |I1 - I2| and increase the current in the differential stage by
D|I1 - I2|.
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I 0
= ----------------1 D
I1 I2
vi
------------- = tanh
2nv T
The increase of the current in the differential stages becomes significant around:
vi
D tanh -------------- = 1
2nv T
Typical performances
DC gain
ft
SR
I0
Itot
95 dB
130 kHz
0.1 V/ sec
0.5 A
2.5 A
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M8
Bias3
In+
Bias1
M2
M3
In-
Out+
OutM1
M4
Bias4
Bias2
M5
M6
In order to have a maximum output swing the bias voltages BIAS1 BIAS2 must be kept as close as possible to the bias voltages
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During the slewing the current source of the output cascodes can be
pushed in the linear region, hence loosing the advantage of the AB
operation.
The problem is solved with the dynamic biasing
M7 M8
M2 M3
OutM1 M4
Bias2
M5 M6
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NOISE
The noise of an operational amplifier is described with an input
referred voltage source Vn.
The spectrum of Vn is made of a white term and 1/f term.
Vn is due to the contributions, referred to the input, of the noise
generators associated to all the transistors of the circuit (assumed
uncorrelated).
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vn4
M3
M4
v n1
vn2
M2
M1
M5
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Where it is assume gm1 = gm2; gm3 = gm4 (it is assumed that the noise
source of M5 does not contribute) moreover since usually W1 =W2;
L1 = L2; W3 =W4; L3 =L4; V2n1 = V2n2; V2n3 = V2n4;
if we refer Vn,out to the input, we get:
2
g m3 2 2
V nout
V n, out
2
2
2
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W
2C ox ------ I
L
KF
8 kT
1
--------- f
= --- ------- + -------------------2 WL
3
g
m 2C ox
66
The attenuation by the factor (gm3/gm1)2 gives, for the white term:
2
V n, in,
2
2V n1 1
3 I 3 W L 3
g m3
2
+ ---------- = 2V n1 1 + ----------------------------
1 I 1 W L 1
g m1
V n, in, 1 f
KF1
K F 3 I 3 L 1
= ------------------------------------ 1 + -----------------------
2
2
1 C ox W 1 L 1
K F 1 I 1 L 3
Where KF1 and KF2 are the flicker noise coefficient of the type of transistor of
which M1 and M3 are made.
The white contribution of the active load is reduced by choosing (W/L)input >>
(W/L)load
The 1/f noise contribution of the active load is reduced by choosing Linput <
Lload
If the above conditions are satisfied the input noise is dominated by the input
pair.
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Cascode scheme:
The noise is contributed by the input
pair and the current sources of the
cascode load
vn4
M4
M3
Out
M2
2
V n, in
= 2 V n1
g m4 2 2
+ ---------- V n4
g m1
vn1
M1
I1
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M1
M3
Out
M4
v
I1
n5
M5
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= 2
2
V n1
2
g m2 2
2 g m5
2
+ ---------- V n2 + ---------- V n5
g m1
g m1
69
Cc
Rz
Out
+
v
v
m 1 i1
n1
v
r1
C1
+
n2
g v
m 2 i2
C2
The noise is modelled with two input referred noise sources: one
at the input of the first stage and the other at the input of the
second stage.
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[dB] p
out
v
n1
out
v
n2
2
log(f)
[dB] p
2
log(f)
1/|Av1|
71
Frequency response:
The input referred noise generator is transmitted to the output as a
conventional input signal
The feedback network around the op-amp must be taken into account.
Out
+
g v
m i
r
0
C0
p1 = -gm/C0
[dB]
v
out
v
n
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1
log(f)
72
df
4 kT
df
8
8
1 dx
1
2
2
V n0 = V n ---------------------------2- = 2 --- kT ---------- ------------------------------------------------2- = 2 --- kT -------------- --------------2- = --- ------3 C0
3
3 2C 0 0 1 + x
g m1 1 + ( 2 fC g )
1
+
s
p
0
0
1
0
m1
Two stages amplifier: we consider only the white term contributed by the
noise source of the second stage.
8 kT
2
V n2 = 2' --- ----------
3 g m2
V n0 =
df
2
--------------------------V
0 n2
2
1 + s p2
g m2
p = -------------------C1 + C2
2
4
kT
2
V n0 = --- ' ------------------------3 ( C1 + C2 )
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LAYOUT
Rules:
Use poly connection only for signal, never for current because the offset
RI 15 mV.
Minimize the line length, especially for lines connecting high impedance
nodes (if they are not the dominant node).
Use matched structure. If necessary common centroid arrangement.
Respect symmetries (even respect power devices).
Only straight-line transistors.
Separate (or shield) the input from the output line, to avoid feedback.
Shielding of high impedance nodes to avoid noise injection from the
power supply and the substrate.
Regular shape and use a layout oriented design.
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Stacked layout:
C sb = C db = C jb W ( d + 2x j )
Source
L
Drain
Structure A:
d
C sb
1
W
= --- C db = C jb ----- ( d + 2x j )
2
2
w
Drain
Source
Structure B:
w/2
2W
C sb = C db = C jb --------- ( d + 2x j )
3
w/3
Drain
Drain
Source
Source
Drain
Drain
Source
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Drain
Drain
Source
Source
Drain
Drain
Source
Source
Drain
76
Example:
1
200
150
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4
3
150
200
5
4
77
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2
M10
M9
VB1
10
10
11
13
13
13
13
13
13
12
M2
M1
4
M3
VB2
4
M4
Out
Out
M6
VB3
2
M5
VB4
VB5
M13
6
2
M8
2
M7
M11
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M12
79
VDD
VB1
VB2
V+
V_
VB4
VB5
VB3
VSS
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