1.

A ripple counter's speed is limited by the propagation delay of:

A. each flip-flop
B. all flip-flops and gates
C. the flip-flops only with gates
D. only circuit gates


2. To operate correctly, starting a ring counter requires:
A. clearing all the flip-flops
B. presetting one flip-flop and clearing all the others
C. clearing one flip-flop and presetting all the others
D. presetting all the flip-flops

3. What type of register would shift a complete binary number in one bit at a time and shift all the stored
bits out one bit at a time?
A. PIPO B. SISO
C. SIPO D. PISO

4.
Synchronous counters eliminate the delay problems encountered with asynchronous (ripple) counters
because the:
A. input clock pulses are applied only to the first and last stages
B. input clock pulses are applied only to the last stage
C. input clock pulses are not used to activate any of the counter stages
D.
input clock pulses are applied simultaneously to each stage


5. One of the major drawbacks to the use of asynchronous counters is that:
A. low-frequency applications are limited because of internal propagation delays
B. high-frequency applications are limited because of internal propagation delays
C.
Asynchronous counters do not have major drawbacks and are suitable for use in high- and
low-frequency counting applications.
D.
Asynchronous counters do not have propagation delays, which limits their use in high-
frequency applications.

6.
When the output of a tri-state shift register is disabled, the output level is placed in a:
A. float state


B. LOW state
C. high impedance state
D. float state and a high impedance state

7.
A comparison between ring and johnson counters indicates that:
A. a ring counter has fewer flip-flops but requires more decoding circuitry
B. a ring counter has an inverted feedback path
C. a johnson counter has more flip-flops but less decoding circuitry
D. a johnson counter has an inverted feedback path

8. A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?
A. shift register sequencer
B. clock
C. johnson
D. binary

9. What is meant by parallel-loading the register?
A. Shifting the data in all flip-flops simultaneously
B. Loading data in two of the flip-flops
C. Loading data in all four flip-flops at the same time
D. Momentarily disabling the synchronous SET and RESET inputs

10. Mod-6 and mod-12 counters are most commonly used in:
A. frequency counters
B. multiplexed displays
C. digital clocks
D. power consumption meters

1. Give two ways of converting a two input NAND gate to an inverter
2. Given a circuit, draw its exact timing response. (I was given a Pseudo Random Signal Generator; you can expect any
sequential ckt)


3. What are set up time & hold time constraints? What do they signify? Which one is critical for estimating maximum
clock frequency of a circuit?
4. Give a circuit to divide frequency of clock cycle by two
5. Design a divide-by-3 sequential circuit with 50% duty circle. (Hint: Double the Clock)
6. Suppose you have a combinational circuit between two registers driven by a clock. What will you do if the delay of
the combinational circuit is greater than your clock signal? (You cant resize the combinational circuit transistors)
The answer to the above question is breaking the combinational circuit and pipelining it. What will be affected if
you do this?
7. What are the different Adder circuits you studied?
8. Give the truth table for a Half Adder. Give a gate level implementation of the same.
9. Draw a Transmission Gate-based D-Latch.
10. Design a Transmission Gate based XOR. Now, how do you convert it to XNOR? (Without inverting the output)
11. How do you detect if two 8-bit signals are same?
12. How do you detect a sequence of "1101" arriving serially from a signal line?
13. Explain the working of a binary counter.