1.what is a flip flop?

Introduction to Flip
Flops: D and T
Introduction

The basic building blocks of combinational logic circuits are gates. In particular, AND,
OR, and NOT gates (however, there are also, XOR, NAND, NOR, XNOR gates too).
The basic building blocks of sequential logic circuits are flip flops. Flip flops are devices
that use a clock. Each flip flop can store one bit.
Here's how a flip flop looks:

Basically, a flip flop has two inputs. One input is a control input. For a D flip flop, the
control input is labelled D. For a T flip flop, the control input is labelled T.
The other input is the clock. You can read about clock from the class notes on clock.
The clock input is usually drawn with a triangular input. These flip-flops are positive
edge-triggered flip flops. This means that the flip flops can only change output values
when the clock is at a positive edge. There are also negative edge triggered flip flops,
which change on a negative edge, and level-triggered flip flops, that change only when
the value is 1. We consider only positive edge-triggered flip flops.
When the clock is not at a positive edge, then the output value is held. That is, it does not
change.
A flip flop also has two outputs, Q and Q'. The output is really the bit that's stored. Thus,
the flip flop is always outputting the one bit of information.
But you might wonder "Doesn't it have two bits of information? Q and Q'?". If you have
two bits, you have four possible values. However, Q' is the negation of Q which means
you only have two possible outputs: Q = 0, Q' = 1, Q = 1, Q' = 0. Since the second
output is always negated from the first, you don't get any additional storage.
You might wonder why flip flops have two outputs, Q and Q'. It turns out you can design
flip flops with NOR gates or NAND gates, with cycles (which is not allowed for
combinational circuits). The design gives you Q' basically for free, so that's why flip
flops have both the regular output and the negated output.
Although I rarely draw it, flip flops often have one additional input called asynchronous
clear. It's drawn at the top of the flip flop. This is an active low asynchronous clear.
"Asynchronous" means "without a clock" (usually). Active low, means you need to set
the value to 0, to make it active.
Thus, if you set the asynchronous clear to 0, it causes Q to be automatically set to 0. It
does this, even if the clock has not reached a positive edge. That is, it sets Q to zero as
fast as it can. The asynchronous clear is often used to reset flip flops to some initial value.
Often, you see active low inputs because it consumes less power.
The flip flops have additional inputs you don't see (so do logic gates for that matter). Flip
flops and logic gates are powered devices. They need an input for ground and usually 5
volts (although there are low voltage versions of the flip flops). However, they're not
drawn because they don't affect how the flip flop behaves.
Characteristic Tables
The behavior of a flip flops can be described by a characteristic table which is basically a
truth table.

D Flip Flop Characteristic Table

Here's the characteristic table for a D flip flop.

D Q Q+ Operation
0 0 0 Reset
0 1 0 Reset
1 0 1 Set
1 1 1 Set
The D flip flop characteristic table has 3 columns. The first column is the value of D, a
control input. The second column is the current state, that is the current value being
output by Q. The third column is the next state, that is, the value of Q at the next positive
edge. It's labelled with Q and the superscript, + (the plus sign).
Sometimes, the current state is written as Q(t) which means the value of Q at the current
time, t, and the next state is written as Q(t + 1) which means the value of Q at the next
clock edge. However, I'll usually write it as Q+.
The characteristic table is unusual, because the second column isn't really an input, it's an
output. The third column is really the same output, but just the output at a future time.
The D flip flop has two possible values. When D = 0, the flip flop does a reset. A reset
means that the output, Q is set to 0. When D = 1, the flip flop does a set, which means the
output Q is set to 1.
This is how you can picture the flip flop working. When the clock is not at a positive
edge, the flip flop ignores D. However, at the positive edge, it reads in the value, D, and
based on D, it updates the value of Q (and of course, Q').
There is some small amount of delay while it reads in the control input (from D) and the
output.
In fact, the "D" in D flip flop stands for "delay". It basically means that the "D" value is
not read immediately, but only at the next positive clock edge.
T Flip Flop Characteristic Table
Here's the characteristic table for a T flip flop.

T Q Q+ Operation
0 0 0 Hold
0 1 1 Hold
1 0 1 Toggle
1 1 0 Toggle
The T flip flop characteristic table has 3 columns. The first column is the value of T, a
control input. The second column is the current state, that is the current value being
output by Q. The third column is the next state, that is, the value of Q at the next positive
edge. It's labelled with Q and the superscript, + (the plus sign).
The T flip flop has two possible values. When T = 0, the flip flop does a hold. A hold
means that the output, Q is kept the same as it was before the clock edge. When T = 1,
the flip flop does a toggle, which means the output Q is negated after the clock edge,
compared to the value before the clock edge.
Thus, in a T flip flop, you can either maintain the current state's value for another cycle,
or you can toggle the value (negate it) at the next clock edge.
Why isn't it XOR?
If you look carefully at a T flip flop characteristic table, it looks a lot like XOR. Why isn't
it XOR?
Several reasons. First, XOR has two inputs, and one output. A T flip flop essentially has a
control input and a control output. Second, the second column and the third column are
really the same output, but at different points in time.
Finally, the flip flop uses a clock, and can only modify the output at positive clock edges.
A gate updates the output as soon as it can (based on the gate's delay).
JK Flip Flop Characteristic Table
Here's the characteristic table for a JK flip flop.

J K Q Q+ Operation
0 0 0 0 Hold
 0 0 1 1 Hold
0 1 0 0 Reset
0 1 1 0 Reset
1 0 0 1 Set
1 0 1 1 Set
1 1 0 1 Toggle
1 1 1 0 Toggle
Basically, a JK flip flop is a combination of a D and T flip flop (or more accurately, a D
and T flip flop are a simplification of a JK flip flop).
A JK flip flop has two control inputs, J and K. When JK = 00, the flip flop holds. When
JK = 01, the flip flop resets. When JK = 10, the flip flop sets. When JK = 11, the flip
flop toggles.
Why have all four possible operations? Often, when you study computer hardware,
especially in an electrical engineering class, you learn how to minimize the circuit, using
Karnaugh maps or the Quine-McCluskey algorithm. You can do more minimization if
you use JK flip flops instead of D or T flip flops.
However, for the most part, we'll ignore JK flip flops, because we don't intend to do
much minimization. Thus, JK flip flops are only mentioned for completeness (i.e., just so
you know they exist).
Storing Information
The biggest difference between a flip flop and a gate is that a flip flop can hold its value.
Although the D (or T) input can change all it wants, the output doesn't change, except at
positive edges.
Even though holding a value is something very simple, it makes it different from logic
gates, and allows us to design circuits that have cycles in them (i.e., feedback).
Summary
A flip flop is a device that can store 1 bit of information. There are three kinds of flip
flops: D, T, and JK. We have ignored the JK flip flop, mostly because they're somewhat
complicated. However, they are mentioned because they do exist.
A flip flop is a clocked device, which can change its value only at positive clock edges.
When the clock is not at a positive edge, the flip flop maintains (holds) its value.
Flip flops allow sequential circuits to have state (i.e., memory), which is something that
combinational logic circuits do not have.
Flip flops and Latches
In the same way that gates are the building blocks of combinatorial circuits, latches and
flip-flops are the building blocks of sequential circuits.
While gates had to be built directly from transistors, latches can be built from gates, and
flip-flops can be built from latches. This fact will make it somewhat easier to understand
latches and flip-flops.
Both latches and flip-flops are circuit elements whose output depends not only on the
current inputs, but also on previous inputs and outputs. The difference between a latch
and a flip-flop is that a latch does not have a clock signal, whereas a flip-flop always
does.
Latches
How can we make a circuit out of gates that is not combinatorial? The answer is feed-
back, which means that we create loops in the circuit diagrams so that output values
depend, indirectly, on themselves. If such feed-back is positive then the circuit tends to
have stable states, and if it is negative the circuit will tend to oscillate.
A latch has positive feedback. Here is an example of a simple latch:

This latch is called SR-latch, which stands for set and reset.
It is not practical to use the methods that we have used to describe combinatorial circuits
to describe the behavior of the SR-latch. Later, we will show a method for describing
flip-flops and clocked sequential circuits. For now, we just rely on our intuition to
describe how latches work.
The SR-latch is meant to have at most one of its inputs equal to 1 at any time. When both
of its inputs are 0 it has two different stable states possible. Either x is 0, in which case
we have the following signal values:

or else x is 1, in which case we have the following signal values:

The actual value depends on the history of input values as we will show next.
Now suppose that s is 1 (and therefore r is 0 since we allow at most one input to be 1 at
any time). We get the following signal values:

The 1 on the s input makes sure the output of the upper nor-gate is 0, and the two 0s on
the input of the lower nor-gate make sure the x output is 1.
Now suppose the s input goes from 1 to 0, while the r input remains at 0. The second
input of the upper nor-gate is 1, so the transition from 1 to 0 of the s input, does not
make any difference. The x output remains at 1. In this case, if the s and r inputs are
both 0, there is only one possible stable state, the one that gives x the value 1.
Conversely, suppose that r is 1 (and therefore s is 0 since we allow at most one input to
be 1 at any time). We get the following signal values:

The 1 on the r input makes sure the x output is 0, and the two 0s on the input of the
upper nor-gate make sure the output of the upper nor-gate is 0.
Now suppose the r input goes from 1 to 0, while the s input remains at 0. The second
input of the lower nor-gate is 1, so the transition from 1 to 0 of the r input, does not
make any difference. The output of the upper nor-gate remains at 1. In this case, if the s
and r inputs are both 0, there is only one possible stable state, the one that gives x the
value 0.
From the discussion above, we conclude that the SR-latch is able to remember the last
state of the inputs, in the sense that it remembers which of the two inputs, s or r, last had
the value of 1.
When we need to draw an SR-latch, we use the following symbol:

Flip-flops
Latches are asynchronous, which means that the output changes very soon after the input
changes. Most computers today, on the other hand, are synchronous, which means that
the outputs of all the sequential circuits change simultaneously to the rhythm of a global
clock signal.
A flip-flop is a synchronous version of the latch. To complicate the situation even more,
there are several fundamental types of flip-flops. Here, we shall only consider a type
called master-slave flip-flop.
In addition to the fundamental types of flip-flops, there are minor variations depending on
the number of inputs and how they control the state of the flip-flop. Here, we shall only
consider a very simple type of flip-flop called a D-flip-flop. A master-slave D-flip-flop is
built from two SR-latches and some gates. Here is the circuit diagram:

The leftmost SR-latch is called the master and the rightmost is called the slave.
Let us first consider what happens when the clock signal is 1. In this case, the two and-
gates in front of the input of the master are open, i.e., they let the value of the D-input
through to the s input of the master, and the inverse of the D input to the r input of the
master. Thus, the value of the D input will go straight trough the master to the x output of
the master. But the two and-gates of the slave re closed, i.e., their outputs are always 0,
so the slave keeps its old value.
When instead the clock signal is 0, the reverse is true, i.e., the and-gates at the input of
the master are closed, whereas the ones at the input of the slave are open. In this case, the
flip-flop is completely insensitive to changes in input.
Now, let us consider what happens when the clock goes from 1 to 0. For this to work, we
have to assume that the input remains the same during a brief period from right before to
right after the clock signal changes. The first thing that happens is that the and-gates at
the input of the master turn off, i.e., they become insensitive to further changes in input.
The value of the x output of the master is now the value of the D input right before the
clock started changing. A brief moment later, the clock signal transition has traversed the
inverter and reaches the and-gates of the slave. These gates open, allowing the x output
of the master to be propagated to the x value of the slave. The x value of the slave, and
therefore that of the entire flip-flop now contains the value of the D input right before the
clock started changing. We can say that the clock transition copied the input to the output
of the flip-flop. But at no point in time is there a direct path from input to output. The
output changes only as a result of clock transitions from 1 to 0.
Finally, let us see what happens when the clock goes from 0 to 1. First, the and-gates of
the master open, letting the value of the D input into the master. By the time the D value
reaches the master, the clock signal transition reaches the and-gates of the slave, and
turns them off before the possibly modified output of the master reaches the slave. Thus,
the slave keeps its old value. From the outside, nothing seems to happen, since the output
does not change. From now on, however, the master is open to changes in the input.
Here is the symbol we use for D-flip-flops:

The little triangle for the clock input indicates that this input is sensitive only to
transitions as opposed to levels as described in the previous paragraph. Sometimes we do
not draw the clock input at all when it is understood that it is there. Clock signals are
boring since they are all just connected to each other. There is therefore little use to draw
them all, and thereby clutter the diagram unnecessarily.

Summary
We have shown how to build a D-flip-flop. It copies its input to its output as a result of a
clock signal transition from 1 to 0. The value copied is the value the input has
immediately before the clock transition. Most of the clock period, the D-flip-flop is
insensitive to changes in the input.
We shall use this key characteristic of the D-flip-flop to build synchronous sequential
circuits.
2.What is emitter follower?
A grounded-collector transistor amplifier which provides less than unity voltage gain but
high input resistance and low output resistance, and which is similar to a cathode
follower in its operations.
A circuit that uses a common-collector transistor amplifier stage with unity voltage gain,
large input resistance Ri, and small output resistance Ro (see illustration). In its behavior,
the emitter follower is analogous and very similar to the source follower in metal-oxide-
semiconductor (MOS) circuits. Many electronic circuits have a relatively high output
resistances and cannot deliver adequate power to a low-resistance load, or do suffer
unacceptable voltage attenuation. In these cases, an emitter follower acts as a very simple
buffer. Widely used, it is often found as the last stage of multistage amplifier so that the
circuit is better able to drive a low-resistance load.

Schematic diagram of an emitter follower circuit.

Difference between Static RAM and Dynamic RAM?

A common type of computer memory that uses capacitors and transistors storing
electrical charges to represent memory states. These capacitors lose their electrical
charge, so they need to be refreshed every millisecond, during which time they cannot be
read by the processor. DRAM chips are small, simple, cheap, easy to make, and hold
approximately four times as much information as a static RAM (SRAM) chip of similar
complexity.
A form of semiconductor memory (RAM). Static RAM storage is based on the logic
circuit known as flip-flop, which retains the information stored in it as long as there is
enough power to run the device. A static RAM chip can store only about one-fourth as
much data as a dynamic RAM chip of the same complexity, but static RAM does not
require refreshing and is usually much faster than dynamic RAM. It is also more
expensive.
What is meant by machine cycle, instruction cycle, T-state?

Machine cycle- Machine cycle is defined as the time required to complete the one
operation. It includes of 3-6 T-states.
Instruction cycle- It is defined as the time required to complete the execution of an
instruction.8085 instruction cycle consist of 1-6 machine cycle.
T-state- It is defined as subdivision of d operation performed in One clock period.

What is the difference between oscillation and multivibrator?

 Oscillation refers to a periodic fluctuation of a variable, or a variation above and
below a mean value, e.g. a pendulum, a periodic flow, etc, and so oscillation
applies generically.

To oscillate means to swing backward and forward like a pendulum or swing, or

move or travel back and forth between two points, such as a maximum and
minimum.

A multivibrator is an electronic circuit used to implement a variety of simple two-state

systems such as oscillators, timers and flipflop. It is characterized by two amplifying
devices (transistors, electron tubes or other devices) cross-coupled by resistors and
capacitors. The most common form is the astable or oscillating type, which generates a
square —the high level of harmonics in its output is what gives the multivibrator its
common name.

There are three types of multivibrator circuit:

• astable, in which the circuit is not stable in either state—it continuously oscillates
from one state to the other.
• monostable, in which one of the states is stable, but the other is not—the circuit
will flip into the unstable state for a determined period, but will eventually return
to the stable state. Such a circuit is useful for creating a timing period of fixed
duration in response to some external event. This circuit is also known as a one
shot. A common application is in eliminating switch bounce.
• bistable, in which the circuit will remain in either state indefinitely. The circuit
can be flipped from one state to the other by an external event or trigger. Such a
circuit is important as the fundamental building block of register of memory
device. This circuit is also known as flip-flop.

What is the internal organization of memory chips?

• It stores 128 bits.

• Requires 14 external connections for address,data and control lines
• And two lines for power supply and ground connections.
• Total of 16 connections.
 the internal organization of memory chips?

FF FF

Address
decoder

Sense/Write Sense/Write Sense/Write

circuit circuit circuit

What is bluetooth and WAP?

Bluetooth is wireless protocol for exchanging data over short distances from fixed and
mobile devices, creating personal area network (PANs). It was originally conceived as a
wireless alternative toRS232 data cables. It can connect several devices, overcoming
problems of synchronization.

Wireless Application Protocol (commonly referred to as WAP) is an open international

standard for application layer network communications in wireless communication
environment. Its main use is to enable access to the Internet (HTTP) from mobile phone
orPDA.

AWAP browser provides all of the basic services of a computer based web browser but
simplified to operate within the restrictions of a mobile phone, such as its smaller view
screen. WAP sites are websites written in, or dynamically converted to, WML (Wireless
Markup Language) and accessed via the WAP browser.