ECEN 2350 Digital Logic Fall 2013

10-26-13 P. Mathys
Project: Binary to BCD to 7-Segment Conversion
The goal of this project is to write parametrized (and scalable) Verilog code for the conversion
of an NB-bit binary number to a ND-digit BCD number that is displayed using 7-segment
displays. For NB=10 and ND=4 the code will be tested using the DE0 board.
The owchart of an algorithm for binary to BCD (binary coded decimal) conversion is shown
on the next page. The algorithm assumes that the input is a binary number Bin with NB
bits and the outputs are ND BCD digits of 4 bits each. An array QQ with 4*ND bits is
used to store intermediate results from stage to stage. The k-th BCD digit is stored in
QQ[4*k+3:4*k] (MSB is leftmost bit). The BCD digit corresponding to k = 0 is the least
signicant BCD digit. Here is an example of how the algorithm works for converting Bin =
(6A)
16
= (1101010)
2
to BCD with ND=3 and NB=7.
i k=2 k=1 k=0 Bin[i]
QQ[11:8] QQ[7:4] QQ[3:0]
0000 0000 0000
6 0000 0000 0001 1
5 0000 0000 0011 1
4 0000 0000 0110 0
3 +11
3 0000 0000 1001
3 0000 0001 0011 1
2 0000 0010 0110 0
1 +11
1 0000 0010 1001
1 0000 0101 0011 1
0 +11
0 0000 1000 0011
0 0001 0000 0110 0

(1)
10
(0)
10
(6)
10
Thus, (1101010)
2
converts to (106)
10
in BCD representation. The basis of the algorithm is
that
V (Bin) = (((((Bin[6] 2+Bin[5])2+Bin[4])2+Bin[3])2+Bin[2])2+Bin[1])2+Bin[0] .
If the multiplication by 2 of the partial results and adding Bin[i] is done using BCD arith-
metic, then the resulting V (Bin) will be in BCD form.
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Binary to BCD Conversion
ND: Number of BCD digits, NB: Number of bits
Initialize
QQ = zeros(1,4*ND)
i = NB-1
k = 0
QQ[4*k+3:4*k] > 4 ?
N
Y
QQ[4*k+3:4*k] =
= QQ[4*k+3:4*k] + 4b0011
k = k+1
k < ND ?
Y
N
{C,QQ} = {QQ,Bin[i]}1
C is discarded
1 means shift left by 1
i = i1
i 0 ?
Y
N
Display QQ[4*k+3:4*k]
for k = ND-1,ND-2,. . . ,1,0
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A parallel implementation of the binary to BCD conversion using a rectangular array struc-
ture is shown for NB=6 and ND=2 on the next page. Below is the Verilog code that
implements this example using two-dimensional wiring arrays and generate constructs.
Note how the QQ and CC wire arrays are declared. wire [7:0] QQ [6:0] declares QQ as
having 8 bits (the rst [7:0] argument) per row and a total of 7 rows (the second [6:0]
argument. The element in the i-th row and j-th column is addressed as Q[i][j], i=0. . .6,
and j=0. . .7. The same construction works for registered values as well.
Your Tasks:
Task 1. Implement the bin2BCD_SS_004 module in Quartus II and compile it together with
the BCDx2plusC and the bin2SS modules whose headers are shown below.
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Binary to BCD Conversion Array Example
ND=2: Number of BCD digits, NB=6: Number of bits
BCDx2plusC BCDx2plusC
BCDx2plusC BCDx2plusC
BCDx2plusC BCDx2plusC
BCDx2plusC BCDx2plusC
BCDx2plusC BCDx2plusC
BCDx2plusC BCDx2plusC
QQ[6][7:4] QQ[6][3:0]
QQ[5][7:4] QQ[5][3:0]
QQ[4][7:4] QQ[4][3:0]
QQ[3][7:4] QQ[3][3:0]
QQ[2][7:4] QQ[2][3:0]
QQ[1][7:4] QQ[1][3:0]
QQ[0][7:4] QQ[0][3:0]
CC[5][2] CC[5][1]
CC[4][2] CC[4][1]
CC[3][2] CC[3][1]
CC[2][2] CC[2][1]
CC[1][2] CC[1][1]
CC[0][2] CC[0][1]
Bin[5]
Bin[4]
Bin[3]
Bin[2]
Bin[1]
Bin[0]
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Task 1 (contd.) In the Quartus II Flow Summary window, check how many chip re-
sources (logic elements, registers, pins, etc) the bin2BCD_SS_004 module uses. Program the
DE0 board with the bin2BCD_SS_004 code and verify that module works correctly. Assign
switches SW[5] to SW[0] to Bin[5:0] and use the HEX1 and HEX0 7-segment displays for
HEX_SS1 and HEX_SS0.
Task 2. Some of the BCDx2plusC modules in the rectangular binary to BCD conversion array
are redundant because all of their inputs (and therefore their outputs) are zero. Identify
these modules in the ND=2, NB=6 example. Write another version of the bin2BCD_SS top-
level module, e.g., called bin2BCD_SS_005, that omits the redundant BCDx2plusC modules.
Compile this new top-level module. Test that it works correctly on the DE0 board. Then
record again how many chip resources (logic elements, registers, pins, etc) are used by this
new module. Compare with the resources used by the bin2BCD_SS_004 module in task 1
and draw conclusions from the comparison.
Task 3. Implement a scalable and parametrized version of the binary to BCD converter
with 7-segment display in Verilog with the following top-level module header.
Your bin2BCD_SS module has to compile correctly for the cases {ND=2,NB=6}, {ND=3,NB=8},
and {ND=4,NB=10} by changing only the parameter values of ND and NB and noth-
ing else. Unused 7-segment displays when ND is less than 4 should be turned o. Test your
module for the three cases on the DE0 board and check that the binary to BCD conversion
yields correct results.
Task 4. The last task is to add a feature that allows you to display the value of the binary
number in Bin either in BCD or in hexadecimal format. Use BUTTON2 on the DE0 board
to toggle between BCD and hexadecimal mode. Indicate hexadecimal mode by turning on
LEDG0. The header for this augmented version of bin2BCD_SS is shown below.
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Test again that this works correctly on the DE0 board for the three ND,NB combinations
specied in task 3.
Deliverables. You need to write and turn in a short report that consists of a separate
paragraph for each task and the Verilog code you wrote for the nal bin2BCD_SS module
(including the code for all submodules). The paragraphs have to address the questions asked
(if any) for a given task and any insights, diculties, and successes that you encountered.
You also need to assess to which degree your completion of each task was successful. The
nal bin2BCD_SS.sof le (the one that is used to program the DE0 board) and the nal
Verilog module les need to be delivered electronically and separately from the report so
that the functioning of your code can be veried by the TA.
Peer Grading. Demonstrate all requirements of this project, including the project report,
to a classmate and have them send you an e-mail with their assessment (see project grading
criteria) of your project. You then have to turn in this e-mail in addition to your report and
your Verilog code.
c 20122013, P. Mathys. Last revised: 10-29-13, PM.
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