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Registers and memories

Ismail MAJDOUB
majdoub.ismail@gmail.com
Digital Signal Processor 2

A register lives within the microrocessor and stores small


!uantities o" data "or immediate use.

A register is just a collection o" "li#"los. A "li#"lo can onl$


store one bit so to handle %& bits at a time we would need
%& "li#"los and would re"er to this as a %&#bit register.

'he register has two distinct grous o" connections( the


data bits and the control signals.
Register
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)hi"t registers
*+emle( )ending data seriall$
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'he bene"it o" using a rotate rather than a shi"t register is


that the data is not destro$ed.
Rotate register
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It is an -#bit register but it is unusual in that each bit stored


is !uite indeendent o" all the others.

A status register or "lag register is li.e a window to see into


the wor.ings o" the microrocessor.

'imer "lag

)ign "lag( A negative number has a / in bit 0 and a


ositive number has a 1 in bit 0

2ero "lag( sends all its time watching "or a result o"
3ero.
4lag register
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'he memor$ comes in an integrated circuit loo.ing li.e a


small microrocessor and is usuall$ called a memor$ chi.

Inside5 there are a large number o" registers5 hundreds5


thousands5 millions deending on the si3e o" the memor$.

Incidentall$5 when we are re"erring to memories5 we use


the word 6cell7 instead o" register even though the$ are the
same thing.
Memories
Digital Signal Processor 7
Memories
Read 8rite Memor$
9olatile Memor$ :on#volatile memor$
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'he letters RAM stands "or Random Access Memor$

In rehistoric comuting da$s5 the memor$ would be


loaded in order rather li.e a shi"t register. ;se!uential
access memor$ <or serial access memor$=5 abbreviated to
)AM >

'o overcome this roblem5 we develoed a wa$ to access


an$ memor$ location ??@ Random Access Memor$
RAM
Digital Signal Processor 9

)tatic RAM( constructed o" "li#"los

D$namic RAM( store the in"ormation in caacitors

:eed 6re"reshing7 at intervals o" about & ms b$ a DRAM


control circuit.
'wo t$es o" RAM
Digital Signal Processor 10

ROMs are used to store in"ormation on ermanent basis.

In the most cases5 ROM are used to store "irmware <Boot=.

*+amle( Aeriherals initiali3ation5 memor$ test5 load in


RAM a art or all the oerating s$tem.
ROM
Digital Signal Processor 11

Mas.ed ROM( is manu"actured to our seci"ication and


cannot be changed.

Arogrammable ROM <AROM=( the setting o" each bit is


loc.ed b$ a "use.<the rogramming is alied a"ter the
device is constructed=

*rasable rogrammable ROM <*AROM=( U9 # *lectrical


'hree t$es o" ROM
Digital Signal Processor 12

*ach location in a memor$ is given a number5 called an address.

'he /B locations o" memor$ would be numbered "rom 1 to /C5 or in


binar$ 1111D////
Accessing Memor$
generall$ &En ? number o" locations where n is the number o" bits in the address.
Digital Signal Processor 13

'he memor$ organi3ation is alwa$s !uoted as <number o"


locations= + bits stored in each.

*+amle(

/B F - </B cellsG cell ? -bits=


Memor$ organi3ation
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'he rocessor5 along with the so"tware5 treats memor$ as


one large one#dimensional arra$5 called a memor$ ma

'he s$stem designer decide in what wa$ the available


memor$ is to be used.
Memor$ mas
Digital Signal Processor 15

'he rocessor5 along with the so"tware5 treats memor$ as


one large one#dimensional arra$5 called a memor$ ma

'he s$stem designer decide in what wa$ the available


memor$ is to be used.
Memor$ mas
Digital Signal Processor 16

Huestions(

Iow man$ .ilob$tes o" User RAM<see memor$ ma


e+amle G celul ? /b$te ? - bits= J

I" a /& .b$tes bloc. o" ROM started at the address


-111I5 what is the highest address in the ROMJ
Memor$ mas
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A microrocessor#based
s$stem
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'he most basic microrocessor based s$stem
Instructions
Internal or e+ternal
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Buses connect the microrocessor inernall$ and to the rest


o" the s$stem.

A bus is there"ore a collection o" conductors roviding a


similar "unction.

*+amle(

an -#bit microrocessor normall$ uses - connectors


to carr$ the data between the microrocessor and
the memor$.
Buses
Digital Signal Processor 20

In a microrocessor#based s$stem we have three main


buses(

Data bus( is a two#wa$ bus5 In"ormation going into the


microrocessor and results coming out.

Address bus( carries addresses and is a one#wa$ bus


"rom the microrocessor to the memor$ or other
devices

Kontrol bus( carries commands "rom the KAU and


return status signals "rom the devices

*+amle( chi select5 readGwrite ...


Buses
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An IGO subs$stem can be as simle as a basic electronic


circuit that connects the rocessor directl$ to an IGO device
<such as a rocessor7s IGO ort to a cloc. or L*Ds located
on the board= to more comle+ IGO subs$stem circuitr$ that
includes several units.
InutGoutut circuits
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InutGoutut circuits
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8e need to modi"$ some data in"ormation into the memor$


??@ some RAM must be added.

'he microrocessor is now controlling the oeration o"


three chis( ROM5 RAM and IGO ??@ it needs to send chi
select and readGwrite in"ormation along the control bus.
A ractical microrocessor s$stem
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A ractical microrocessor s$stem
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*+amle( )end the number &CI which is in the ROM and


store it in the RAM at address &C11I.

/# 'he microrocessor has to collect the instruction


"rom an address in ROM. It does this b$ utting the
address onto the address bus.

&# 'he address is alied to the ROM and the RAM as


well as the address decoder. 'his will not cause an$
roblems because all the chi selects will be switched
o"" at the moment. 8hen the logic gates within the
address decoder resonds to the inut "rom the
address bus the result will be that the ROM is switched
on and the other two are .et o"".
A ractical microrocessor s$stem
Digital Signal Processor 26

*+amle( )end the number &CI which is in the ROM and


store it in the RAM at address &C11I.

%# )witching on the ROM will mean that it ta.es in the


address "rom the address bus. Inside the ROM chi5 the
row and column decoders activate one o" the memor$
locations and the binar$ number stored at that location
is laced on the data bus b$ switching on the tri#state
bu""ers. As soon as the in"ormation is read5the chi
select will switch the ROM chi o"".

M# 'he in"ormation which is now on the data bus is read


b$ the microrocessor. It is an instruction which can be
interreted as 6go to address 4B11I and read the
number that is stored in that address7.
A ractical microrocessor s$stem
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*+amle( )end the number &CI which is in the ROM and


store it in the RAM at address &C11I.

C# In resonse to this instruction5 the microrocessor


uts the address 4B11I onto the address bus.

B# 'he address decoder alies this number to its logic


gates and this results in the chi select o" the ROM chi
being switched on again. 'he ROM chi accets the
address 4B11I into its row and column decoders and
then uts the number &CI onto the data bus.
A ractical microrocessor s$stem
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*+amle( )end the number &CI which is in the ROM and


store it in the RAM at address &C11I.

0# 'his number is stored temoraril$ in the


microrocessor.

-# 'he microrocessor then uts the number &C11I


onto the address bus and the address decoder uts a
signal on the chi select o" the RAM chi to switch it on.
It then sends a logic / on the readGwrite line. 'he RAM
is switched on and it is told to read the data on the data
bus. 'he readGwrite line goes to the IGO chi as well but
again5this causes no roblem because its chi select
line is .eeing it switched o"".
A ractical microrocessor s$stem

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