Application Device Power Output Input Voltage Output Voltage Topology

LCD Monitor TOP258PN 35 W 90-265 VAC 5 V, 12 V Flyback

DI-142 Design Idea
TOPSwitch-HX
www.powerint.com September 2007
35 W LCD Monitor Power Supply

Design Highlights
Low component count, high efciency
>82% full load efciency (Meets CEC/ENERGY STAR 2008 re-
quirements of 81%)
Delivers 35 W at 50 C ambient without requiring an external
heat sink
Low no-load and standby power consumption
0.55 W standby output power for <1 W input
No-load power consumption <300 mW at 265 VAC
Integrated safety and reliability features:
Accurate, auto-recovering, hysteretic thermal shutdown func-
tion maintains safe PCB temperatures under all conditions
Auto-restart protects against output short circuits and open
feedback loops
Output overvoltage protection congurable for latching or self
recovery
Meets EN55022 and CISPR-22 Class B conducted EMI with
>10 dBV margin

Figure 1. Universal Input, 35 W Output, LCD Power Supply, Using a TOP258PN Device.
Operation
The power supply shown in Figure 1 is a universal input, 35 W out-
put, yback power supply using the TOP258PN device. A typical
application would include LCD monitors, but the design is suitable
for any applicable needing a highly energy efcient dual output
power supply.
The AC input is rectied (D1D4) and ltered (C4) and connected
across the primary side power components (T1 and U1). EMI lter-
ing is provided by components, C4, L1, C7 and C11. Thermistor
RT1 limits the inrush current when the AC input is applied.
Resistors R3 and R4 program the nominal undervoltage (UV) lock-
out and overvoltage (OV) shutdown limits to 103 V and 450 V re-
spectively. UV lockout protects the supply from overheating at low
line and eliminates power-up and power down glitches. OV shut-
down protects the power supply from line surges.
Zener diode VR2 and resistor R5 form an optional latching output
D
S
C
M
CONTROL
PI-4747-091407
R11
33
R12
33
R3
2.0 M
R16
10 k
R17
10 k
R21
10 k
1%
R18
196 k
1%
R19
10
R14
22
R13
330
R15
1 k
R20
12.4 k
1%
D9
1N4148
U3
TL431
2%
VR3
BZX55B8V2
8.2 V
2%
R7
20
1/2 W
VR2
1N5250B
20 V
VR1
P6KE200A
D5
FR106
R4
2.0 M
R5
5.1 k
R1
1 M
R2
1 M
R8
6.8
R10
4.7
R6
22 k
2 W
U2B
PS2501-
1-H-A
U2A
PS2501-
1-H-A
L2
3.3 H
L1
6.8 mH
L3
3.3 H
U1
TOP258PN
C9
47 F
16 V C20
10 F
50 V
C21
220 nF
50 V
C19
1.0 F
50 V
C10
10 F
50 V
C11
2.2 nF
250 VAC
D6
FR106
D8
SB530
D7
SB560
C8
100 nF
50 V
D1
1N4937
D2
1N4007
D3
1N4937
D4
1N4007
C13
680 F
25 V
C14
680 F
25 V
C15
220 F
25 V
C18
220 F
10 V
C17
2200 F
10 V
C12
470 pF
100 V
C16
470 pF
100 V
2
T1
EER28
7
11
9
3
6
5
4
C4
100 F
400 V
C6
3.9 nF
1 kV
C7
2.2 nF
250 VAC
C3
220 nF
275 VAC
RT1
10
F1
3.15 A
TOPSwitch-HX
L
E
N
+12 V,
2 A
RTN
+5 V,
2.2 A
RTN
t
O
90 - 265
VAC
Power Integrations
5245 Hellyer Avenue
San Jose, CA 95138, USA.
Main: +1 408-414-9200
Customer Service
Phone: +1-408-414-9665
Fax: +1-408-414-9765
Email: usasales@powerint.com
On the Web
www.powerint.com
A
09/07
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power
Integrations does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS
MAKES NO WARRANTY HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
The products and applications illustrated herein (transformer construction and circuits external to the products) may be covered by
one or more U.S. and foreign patents or potentially by pending U.S. and foreign patent applications assigned to Power Integrations.
A complete list of Power Integrations' patents may be found at www.powerint.com. Power Integrations grants its customers a license
under certain patent rights as set forth at http://www.powerint.com/ip.htm.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, DPA-Switch, PeakSwitch, EcoSmart, Clampless, E-Shield, Filterfuse, StackFET,
PI Expert and PI FACTS are trademarks of Power Integrations, Inc. Other trademarks are property of their respective companies.
2007, Power Integrations, Inc.
DI-142
overvoltage protection (OVP) circuit. Increased voltage at the out-
put will also result in an increased voltage at the output of the bias
winding across C10. Zener VR2 will breakdown and current will
ow into the Multifunction (M) pin of IC U1, thus initiating a hyster-
etic OV shutdown. The value of R5 determines if the shut down is
latching or non-latching.
For extremely low power levels, U1 operates in the multi-cycle
modulation mode for excellent efciency that extends down to no-
load and standby power levels.
Due to the 700 V BV
DSS
rating of U1 the transformer turns ratio (V
OR
)
can be selected to allow a low cost 60 V schottky diode (D7) to be
used for the 12 V output.
Output voltage feedback is derived from both outputs for better
cross-regulation. Capacitor C19 and resistor R14 form a phase
boost network that provides additional phase margin to ensure
stable operation and improve transient response. The feedback
current is fed via U2 into the CONTROL pin of U1. This determines
the duty cycle thereby providing output regulation.
Key Design Points
Diodes D1 and D3 are selected as fast diodes for better EMI
performance.
If latching OVP is desired the value of R5 should be reduced to
20 .
Design the RCD clamp (R6, R7, C6 and D5) for normal operation
thereby maximizing efciency at light load. Zener diode VR1 pro-
vides a dened maximum clamp voltage and typically only con-
ducts during load transients or during an overload condition.
The secondary side snubber (R11, C12, R12 and C16) reduce
high frequency secondary diode ringing and improve high fre-
quency conducted EMI.
Post-lters (L2/C15 and L3/C18) reduce output noise and ripple
to <1% of the respective output voltage.
In a three wire system, placing Y capacitors (C1, C2) between
line/neutral and earth reduces common mode EMI.
Soft nish capacitor C20 ensures no output overshoot at start-
up. Diode D9 isolates this capacitor from the feedback loop after
start-up. Resistor R16 allows a path for this capacitor to dis-
charge into the 5 V load.
Resistor R19 and VR3 improve cross regulation when the 5 V
output is loaded while 12 V output is unloaded.

Transformer Parameters
Core Material
EER28 NC-2H or equivalent, gapped for ALG of
213 nH/t
2
Bobbin EER28, 12 pin, horizontal
Winding Details
3mm margins on both sides of bobbin to meet
safety
Primary: 24T 1 AWG 27, tape
Bias: 7T 2, AWG 26, 3 layers, tape
5 V: 3T, foil 2 mils thick
12 V: 4T 4, AWG 26, 3 layers tape
Primary: 46T 1, AWG 27, tape
Winding Order
Primary (4-3), Bias (6-5), 5 V (11-9), 12 V (7-11),
Primary (3-2)
Primary Inductance 1038 H, 5%
Resonant
Frequency
1000 kHz (minimum)
Leakage
Inductance
20 H (maximum)
Table 1. Transformer Parameters.
(AWG = American Wire Gauge, TIW = Triple Insulated Wire,
NC = No Connection).
Figure 2. Worst Case Conducted EMI (230 VAC) With Output Grounded
(EN55022B limits shown).
P
I
-
4
7
6
6
-
0
6
2
1
0
7
1.0 0.15 10.0 100.0
-20
-10
0
10
20
30
40
50
60
80
70
MHz
d
B

V
QP
AV