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LED2 Data

Amb (LED2) Data


LED1 Data
Amb (LED1) Data
AFE
SPI
(LED2 t Amb) Data
(LED1 t Amb) Data
+
Buffer ADC
+
TIA
+
Stage 2
Gain
Photodiode
CPD
D
ig
it
a
l F
ilt
e
r
Rx
SPI Interface
Diagnostic
PD Open or Short
Cable Off
LED Open or Short
LED
Driver
LED Current
Control
DAC
Timing
Controller
OSC
8 MHz
D
ia
g
n
o
s
t
ic
S
ig
n
a
ls
AFE
LED
5-V Supply
Tx Driver
Supply
2.2-V Supply
LED2
AMBLED2
LED1
AMBLED1
F
ilte
r
A F E 4 4 9 0
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I n te g r a te d A n a l og F r on t- E n d f or P u l s e O x ime te r s
Che ck f or Sa mpl e s : A F E 4 4 9 0
1F E A TURE S
23 F u l l y- I n te g r a te d A n a l og F r on t- E n d f or
P u l s e O x ime te r A ppl ica tion s : P a cka g e : Compa ct QF N- 4 0 (6 mm 6 mm)
F l e x ibl e P u l s e Se qu e n cin g a n d Spe cif ie d Te mpe r a tu r e Ra n g e : 4 0 C to +85C
Timin g Con tr ol
A P P LI CA TI O NS
Tr a n s mit:
Me d ica l P u l s e O x ime te r A ppl ica tion s I n te g r a te d LE D Dr ive r
(H- Br id g e or P u s h/P u l l )
I n d u s tr ia l P hotome tr y A ppl ica tion s
110 - d B Dyn a mic Ra n g e A cr os s F u l l Ra n g e
DE SCRI P TI O N (E n a bl e s Low Nois e a t Low LE D Cu r r e n t)
The AFE4490 is a fully-integrated analog front-end
LE D Cu r r e n t:
(AFE) that is ideally suited for pulse-oximeter
P r og r a mma bl e Ra n g e s of 50 mA , 75 mA ,
applications. The device consists of a low-noise
10 0 mA , 150 mA , a n d 20 0 mA ,
receiver channel with a 22-bit analog-to-digital
E a ch with 8- Bit Cu r r e n t Re s ol u tion
converter (ADC), an LED transmit section, and
Low P owe r : diagnostics for sensor and LED fault detection. The
AFE4490 is a very configurable timing controller. This
10 0 A + A ve r a g e LE D Cu r r e n t
flexibility enables the user to have complete control of
LE D O n - Time P r og r a mma bil ity f r om
the device timing characteristics. To ease clocking
(50 s + Se ttl e Time ) to 4 ms
requirements and provide a low-jitter clock to the
I n d e pe n d e n t LE D2 a n d LE D1 Cu r r e n t AFE4490, an oscillator is also integrated that
functions from an external crystal. The device Re f e r e n ce
communicates to an external microcontroller or host
Re ce ive Cha n n e l with Hig h Dyn a mic Ra n g e :
processor using an SPI interface.
I n pu t- Re f e r r e d Nois e :
The AFE4490 is a complete AFE solution packaged
13 pA
RMS
(0 .1- Hz to 5- Hz Ba n d wid th)
in a single, compact QFN-40 package (6 mm
13.5 Nois e - F r e e Bits (0 .1 Hz to 5 Hz)
6 mm) and is specified over the operating
A n a l og A mbie n t Ca n ce l l a tion Sche me with
temperature range of 40C to +85C.
Se l e cta bl e 1- A to 10 - A A mbie n t Cu r r e n t
Low P owe r : < 2.3 mA a t 3.0 - V Su ppl y
Rx Sa mpl e Time : 50 s to 250 s
I - V A mpl if ie r with Se ve n Se pa r a te LE D2 a n d
LE D1 P r og r a mma bl e F e e d ba ck R a n d C
Se ttin g s
I n te g r a te d Dig ita l A mbie n t E s tima tion a n d
Su btr a ction
I n te g r a te d F a u l t Dia g n os tics :
P hotod iod e a n d LE D O pe n a n d
Shor t De te ction
Ca bl e O n /O f f De te ction
Su ppl ie s :
Rx = 2.0 V to 3.6 V
Tx = 3.0 V or 5.25 V
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2SPI is a trademark of Motorola.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright 20122013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
F A MI LY A ND O RDE RI NG I NF O RMA TI O N
O P E RA TI NG
LE D DRI VE LE D DRI VE CURRE NT P O WE R SUP P LY TE MP E RA TURE
P RO DUCT P A CKA GE - LE A D CO NF I GURA TI O N (mA , ma x ) (V) RA NGE
AFE4490 QFN-40 Bridge, push-pull 50, 75, 100, 150, and 200 3 to 5.25 40C to +85C
AFE4400 QFN-40 Bridge, push-pull 50 3 to 3.6 0C to +70C
A BSO LUTE MA XI MUM RA TI NGS
(1)
Over operating free-air temperature range, unless otherwise noted.
VA LUE UNI T
AVDD to AVSS 0.3 to +7 V
DVDD to DGND 0.3 to +7 V
AGND to DGND 0.3 to +0.3 V
Analog input to AVSS AVSS 0.3 to AVDD + 0.3 V
Digital input to DVDD DVSS 0.3 to DVDD + 0.3 V
Input current to any pin except supply pins
(2)
7 mA
Momentary 50 mA
Input current
Continuous 7 mA
Operating temperature range 40 to +85 C
Storage temperature range, T
stg
60 to +150 C
Maximum junction temperature, T
J
+125 C
Human body model (HBM)
1000 V
JEDEC standard 22, test method A114-C.01, all pins
Electrostatic discharge
(ESD) ratings
Charged device model (CDM)
500 V
JEDEC standard 22, test method C101, all pins
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input terminals are diode-clamped to the power-supply rails. Input signals that can swing beyond the supply rails must be current-limited
to 10 mA or less.
THE RMA L I NF O RMA TI O N
A F E 4 4 9 0
THE RMA L ME TRI C
(1)
RHA (QF N) UNI TS
4 0 P I NS

JA
Junction-to-ambient thermal resistance 35

JCtop
Junction-to-case (top) thermal resistance 31

JB
Junction-to-board thermal resistance 26
C/W

JT
Junction-to-top characterization parameter 0.1

JB
Junction-to-board characterization parameter N/A

JCbot
Junction-to-case (bottom) thermal resistance N/A
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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RE CO MME NDE D O P E RA TI NG CO NDI TI O NS
Over operating free-air temperature range, unless otherwise noted.
P A RA ME TE R VA LUE UNI T
SUP P LI E S
RX_ANA_SUP AFE analog supply 2.0 to 3.6 V
RX_DIG_SUP AFE digital supply 2.0 to 3.6 V
TX_CTRL_SUP Transmit controller supply 3.0 to 5.25 V
[3.0 or (1.4 + V
LED
+ V
CABLE
)
(1) (2)
,
H-bridge configuration V
whichever is greater] to 5.25
LED_DRV_SUP Transmit LED driver supply
Common anode [3.0 or (1.3 + V
LED
+ V
CABLE
)
(1) (2)
,
V
configuration whichever is greater] to 5.25
Difference between LED_DRV_SUP and TX_CTRL_SUP 0.3 to +0.3 V
TE MP E RA TURE
Specified temperature range 40 to +85 C
Storage temperature range 60 to +150 C
(1) V
LED
refers to the voltage drop across the external LED connected between the TXP and TXM pins (in H-bridge mode) and from the
TXP and TXM pins to LED_DRV_SUP (in the common anode configuration).
(2) V
CABLE
refers to voltage drop across any cable, connector, or any other component in series with the LED.
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 3
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N = log 2
FB
I
PD
6.6 I
NOISE
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E LE CTRI CA L CHA RA CTE RI STI CS
Minimum and maximum specifications are at T
A
= 40C to +85C. Typical specifications are at +25C.
All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and f
CLK
= 8 MHz,
unless otherwise noted.
P A RA ME TE R TE ST CO NDI TI O NS MI N TYP MA X UNI T
P E RF O RMA NCE (F u l l - Sig n a l Cha in )
R
F
= 10 k 50 A
R
F
= 25 k 20 A
R
F
= 50 k 10 A
I
IN_FS
Full-scale input current R
F
= 100 k 5 A
R
F
= 250 k 2 A
R
F
= 500 k 1 A
R
F
= 1 M 0.5 A
PRF Pulse repetition frequency 61 5000 SPS
DC
PRF
PRF duty cycle 25%
R
F
= 10 k 50 A
I
IN_FS
Full-scale input current
R
F
= 1 M 0.5 A
PSRR
LED
PSRR, transmit LED driver With respect to ripple on LED_DRV_SUP 75 dB
PSRR
Tx
PSRR, transmit control With respect to ripple on TX_CTRL_SUP 60 dB
With respect to ripple on RX_ANA_SUP and
PSRR
Rx
PSRR, receiver 60 dB
RX_DIG_SUP
Total integrated noise current, input-referred R
F
= 100 k, PRF = 625 Hz, duty cycle = 5% 36 pA
RMS
(receiver with transmitter loop back,
R
F
= 500 k, PRF = 625 Hz, duty cycle = 5% 13 pA
RMS 0.1-Hz to 5-Hz bandwidth)
R
F
= 100 k, PRF = 625 Hz, duty cycle = 5% 14.3 Bits
Noise-free bits (receiver with transmitter loop
N
FB
back, 0.1-Hz to 5-Hz bandwidth)
(1)
R
F
= 500 k, PRF = 625 Hz, duty cycle = 5% 13.5 Bits
RE CE I VE R F UNCTI O NA L BLO CK LE VE L SP E CI F I CA TI O N
R
F
= 500 k, ambient cancellation enabled,
stage 2 gain = 4, PRF = 1300 Hz, 1.4 pA
RMS
LED duty cycle = 25%
Total integrated noise current, input-referred
(receiver alone) over 0.1-Hz to 5-Hz bandwidth
R
F
= 500 k, ambient cancellation enabled,
stage 2 gain = 4, PRF = 1300 Hz, 5 pA
RMS
LED duty cycle = 5%
I - V TRA NSI MP E DA NCE A MP LI F I E R
See the Receiver Channel section
G Gain R
F
= 10 k to R
F
= 1 M V/A
for details
Gain accuracy 7%
10k, 25k, 50k, 100k, 250k,
Feedback resistance R
F

500k, and 1M
Feedback resistor tolerance R
F
7%
Feedback capacitance C
F
5, 10, 25, 50, 100, and 250 pF
Feedback capacitor tolerance C
F
20%
V
OD(fs)
Full-scale differential output voltage 1 V
Common-mode voltage on input pins Set internally 0.9 V
Includes equivalent capacitance of
External differential input capacitance 10 1000 pF
photodiode, cables, EMI filter, and so forth
With a 1-k series resistor and a 10-nF
V
O(shield)
Shield output voltage, V
CM
0.9 V
decoupling capacitor to ground
(1) Noise-free bits (N
FB
) are defined as:
Where:
I
PD
is the photodiode current, and I
NOISE
is the input-referred RMS noise current.
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E LE CTRI CA L CHA RA CTE RI STI CS (con tin u e d )
Minimum and maximum specifications are at T
A
= 40C to +85C. Typical specifications are at +25C.
All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and f
CLK
= 8 MHz,
unless otherwise noted.
P A RA ME TE R TE ST CO NDI TI O NS MI N TYP MA X UNI T
A MBI E NT CA NCE LLA TI O N STA GE
G Gain 1, 1.5, 2, 3, and 4 V/V
Current DAC range 0 10 A
Current DAC step size 1 A
LO W- P A SS F I LTE R
Low-pass corner frequency 3-dB attenuation 0.5 and 1 kHz
Duty cycle = 25% 0.004 dB
Pass-band attenuation, 2 Hz to 10 Hz
Duty cycle = 10% 0.041 dB
A NA LO G- TO - DI GI TA L CO NVE RTE R
Resolution 22 Bits
See the ADC Operation and Averaging
Sample rate 4 PRF SPS
Module section
ADC full-scale voltage 1.2 V
See the ADC Operation and Averaging
ADC conversion time 50 PRF / 4 s
Module section
ADC reset time 2 t
CLK
TRA NSMI TTE R
0, 50, 75, 100, 150, and 200
Output current range (see the LEDCNTRL: LED Control mA
Register for details)
LED current DAC error 5%
Output current resolution 8 Bits
At 25-mA output current 110 dB
Transmitter noise dynamic range,
over 0.1-Hz to 5-Hz bandwidth
At 100-mA output current 110 dB
Minimum sample time of LED1 and LED2
50 s
pulses
LED_ON = 0 1 A
LED current DAC leakage current
LED_ON = 1 50 A
LED current DAC linearity Percent of full-scale current 0.5%
From zero current to 150 mA 7 s
Output current settling time
(with resistive load)
From 150 mA to zero current 7 s
DI A GNO STI CS
EN_SLOW_DIAG = 0
Start of diagnostics after the DIAG_EN
register bit is set. 8 ms
End of diagnostic indicated by DIAG_END
going high.
Duration of diagnostics state machine
EN_SLOW_DIAG = 1
Start of diagnostics after the DIAG_EN
register bit is set. 16 ms
End of diagnostic indicated by DIAG_END
going high.
Open fault resistance > 100 k
Short fault resistance < 10 k
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E LE CTRI CA L CHA RA CTE RI STI CS (con tin u e d )
Minimum and maximum specifications are at T
A
= 40C to +85C. Typical specifications are at +25C.
All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and f
CLK
= 8 MHz,
unless otherwise noted.
P A RA ME TE R TE ST CO NDI TI O NS MI N TYP MA X UNI T
I NTE RNA L O SCI LLA TO R
With an 8-MHz crystal connected to the XIN
f
CLKOUT
CLKOUT frequency 4 MHz
and XOUT pins
DC
CLKOUT
CLKOUT duty cycle 50%
With an 8-MHz crystal connected to the XIN
Crystal oscillator start-up time 200 s
and XOUT pins
E XTE RNA L CLO CK
Maximum allowable external clock jitter 50 ps
TI MI NG
Wake-up time from complete power-down 1000 ms
t
RESET
Active low RESET pulse duration 1 s
DIAG_END pulse duration at diagnostics CLKOUT
t
DIAGEND
4
completion cycles
CLKOUT
t
ADCRDY
ADC_RDY pulse duration 1
cycles
DI GI TA L SI GNA L CHA RA CTE RI STI CS
AFE_PDN, SPI CLK, SPI SIMO, SPI STE,
V
IH
Logic high input voltage 0.75 RX_DIG_SUP V
RESET
AFE_PDN, SPI CLK, SPI SIMO, SPI STE,
V
IL
Logic low input voltage 0.25 RX_DIG_SUP V
RESET
I
IN
Logic input current Digital inputs at V
IH
or V
IL
0.1 A
DIAG_END, LED_ALM, PD_ALM, SPI SOMI,
V
OH
Logic high output voltage RX_DIG_SUP 0.1 V
ADC_RDY, CLKOUT
DIAG_END, LED_ALM, PD_ALM, SPI SOMI,
V
OL
Logic low output voltage 0.1 V
ADC_RDY, CLKOUT
SUP P LY CURRE NT
RX_ANA_SUP = 3.0 V, with 8-MHz clock
0.6 mA
running, Rx stage 2 disabled
Receiver analog supply current
RX_ANA_SUP = 3.0 V, with 8-MHz clock
0.7 mA
running, Rx stage 2 enabled
Receiver digital supply current RX_DIG_SUP = 3.0 V 0.27 mA
LED_DRV
LED driver supply current With zero LED current setting 55 A
_SUP
TX_CTRL
Transmitter control supply current 15 A
_SUP
Receiver current only
5 A
(RX_ANA_SUP + RX_DIG_SUP)
Complete power-down
(using the AFE_PDN pin)
Transmitter current only
2 A
(LED_DRV_SUP + TX_CTRL_SUP)
Receiver current only
Power-down Rx alone 220 A
(RX_ANA_SUP + RX_DIG_SUP)
Transmitter current only
Power-down Tx alone 2 A
(LED_DRV_SUP + TX_CTRL_SUP)
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E LE CTRI CA L CHA RA CTE RI STI CS (con tin u e d )
Minimum and maximum specifications are at T
A
= 40C to +85C. Typical specifications are at +25C.
All specifications are at RX_ANA_SUP = RX_DIG_SUP = 3 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and f
CLK
= 8 MHz,
unless otherwise noted.
P A RA ME TE R TE ST CO NDI TI O NS MI N TYP MA X UNI T
P O WE R DI SSI P A TI O N
Normal operation (excluding LEDs) 1.54 mW
P
D(q)
Quiescent power dissipation
Power-down 0.1 W
LED_DRV_SUP current value.
LED_DRV_SUP 1 A
Does not include LED current.
Power-down with the
TX_CTRL_SUP 1 A
AFE_PDN pin
RX_ANA_SUP 5 A
RX_DIG_SUP 0.1 A
LED_DRV_SUP current value.
LED_DRV_SUP 1 A
Does not include LED current.
Power-down with the
TX_CTRL_SUP 1 A
PDNAFE register bit
RX_ANA_SUP 15 A
RX_DIG_SUP 20 A
LED_DRV_SUP current value.
LED_DRV_SUP 50 A
Does not include LED current.
TX_CTRL_SUP 15 A
Power-down Rx
RX_ANA_SUP 220 A
RX_DIG_SUP 220 A
LED_DRV_SUP current value.
LED_DRV_SUP 2 A
Does not include LED current.
TX_CTRL_SUP 2 A
Power-down Tx
RX_ANA_SUP 600 A
RX_DIG_SUP 230 A
LED_DRV_SUP current value.
LED_DRV_SUP 50 A
Does not include LED current.
After reset, with 8-MHz
TX_CTRL_SUP 15 A
clock running
RX_ANA_SUP 600 A
RX_DIG_SUP 230 A
LED_DRV_SUP current value.
LED_DRV_SUP 0.28 A
Does not include LED current.
With stage 2 mode
TX_CTRL_SUP 0.1 A
enabled and 8-MHz clock
running
RX_ANA_SUP 700 A
RX_DIG_SUP 0.8 A
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: AFE4490
A7 A6 A1 A0
SPISTE
SPISIMO
SCLK
Don't care, can be high or low.
D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0
SPISOMI
~~~~~~
CLK
tCLK
tDATA
tSCLK
tDECODE
tDOHD
A F E 4 4 9 0
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P A RA ME TRI C ME A SURE ME NT I NF O RMA TI O N
SE RI A L I NTE RF A CE TI MI NG
(1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE.
(2) Specify the register address whose contents must be read back on A[7:0].
(3) The AFE outputs the contents of the specified register on the SOMI pin.
F ig u r e 1. Se r ia l I n te r f a ce Timin g Dia g r a m
(1)(2)(3)
Ta bl e 1. Timin g Re qu ir e me n ts f or F ig u r e 1
2.0 V RX_DI G_SUP 3.6 V
P A RA ME TE R UNI T
MI N TYP MA X
f
SPICLK
SPI CLK frequency 8 MHz
t
SPI_SU
SPISIMO input data setup time with respect to SCLK rising edge 62.5 ns
t
SPI_HO
SPISIMO input data hold time with respect to SCLK rising edge 62.5 ns
t
SOMI_VAL
SPISOMI output data setup time t
SPICLK
/ 4 ns
t
SOMI_HO
SPISOMI output data hold time t
SPICLK
/ 2 ns
t
RISE
Rise time from 20% to 80% 5 ns
t
FALL
Fall time from 80% to 20% 5 ns
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INN
INP
RX_ANA_GND
VCM
DNC
(1)
DNC
BG
VSS
TX_REF
DNC
CLKOUT
RESET
ADC_RDY
SPISTE
SPISIMO
SPISOMI
SCLK
PD_ALM/ADC Reset
LED_ALM
DIAD_END
1
2
3
4
5
6
7
8
9
10
30
29
28
27
26
25
24
23
22
21
T
X
_
C
T
R
L
_
S
U
P
11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31
R
X
_
A
N
A
_
G
N
D
L
E
D
_
D
R
V
_
G
N
D
R
X
_
A
N
A
_
S
U
P
L
E
D
_
D
R
V
_
G
N
D
X
I
N
T
X
N
X
O
U
T
T
X
P
R
X
_
A
N
A
_
G
N
D
L
E
D
_
D
R
V
_
G
N
D
R
X
O
U
T
P
L
E
D
_
D
R
V
_
S
U
P
R
X
O
U
T
N
L
E
D
_
D
R
V
_
S
U
P
R
X
_
A
N
A
_
S
U
P
R
X
_
D
I
G
_
G
N
D
R
X
_
D
I
G
_
G
N
D
A
F
E
_
P
D
N
R
X
_
D
I
G
_
G
N
D
A F E 4 4 9 0
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P I N CO NF I GURA TI O N
RHA P A CKA GE
QF N- 4 0
(Top Vie w)
(4) DNC = Do not connect.
P I N DE SCRI P TI O NS
NA ME NO . F UNCTI O N DE SCRI P TI O N
Output signal that indicates ADC conversion completion.
ADC_RDY 28 Digital
Can be connected to the interrupt input pin of an external microcontroller.
AFE-only power-down input; active low.
AFE_PDN 20 Digital
Can be connected to the port pin of an external microcontroller.
Decoupling capacitor for internal band-gap voltage to ground.
BG 7 Reference
(2.2-F decoupling capacitor to ground, expected voltage = 1.0 V.)
Buffered 4-MHz output clock output.
CLKOUT 30 Digital
Can be connected to the clock input pin of an external microcontroller.
Output signal that indicates completion of diagnostics.
DIAG_END 21 Digital
Can be connected to the port pin of an external microcontroller.
DNC
(1)
5, 6, 10 Do not connect these pins. Leave as open-circuit.
INN 1 Analog Receiver input pin. Connect to photodiode anode.
INP 2 Analog Receiver input pin. Connect to photodiode cathode.
LED_DRV_GND 12, 13, 16 Supply LED driver ground pin, H-bridge. Connect to common board ground.
LED driver supply pin, H-bridge. Connect to an external power supply capable of supplying the
LED_DRV_SUP 17, 18 Supply
large LED current, which is drawn by this supply pin.
Output signal that indicates an LED cable fault.
LED_ALM 22 Digital
Can be connected to the port pin of an external microcontroller.
(1) Leave pins as open circuit. Do not connect.
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Product Folder Links: AFE4490
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
P I N DE SCRI P TI O NS (con tin u e d )
NA ME NO . F UNCTI O N DE SCRI P TI O N
Output signal that indicates a PD sensor or cable fault.
PD_ALM/ADC Reset 23 Digital Can be connected to the port pin of an external microcontroller.
In ADC bypass mode, the PD_ALM pin can be used to bring out the ADC reset signal.
AFE-only reset input, active low.
RESET 29 Digital
Can be connected to the port pin of an external microcontroller.
RX_ANA_GND 3, 36, 40 Supply Rx analog ground pin. Connect to common board ground.
RX_ANA_SUP 33, 39 Supply Rx analog supply pin (2.0 V to 3.6 V); 0.1-F decoupling capacitor to ground
RX_DIG_GND 19, 32 Supply Rx digital ground pin. Connect to common board ground.
RX_DIG_SUP 31 Supply Rx digital supply pin (2.0 V to 3.6 V); 0.1-F decoupling capacitor to ground
RXOUTN 34 Analog External ADC negative input when in ADC bypass mode
RXOUTP 35 Analog External ADC positive input when in ADC bypass mode
SCLK 24 SPI SPI clock pin
SPISIMO 26 SPI SPI serial in master out
SPISOMI 25 SPI SPI serial out master in
SPISTE 27 SPI SPI serial interface enable
TX_CTRL_SUP 11 Supply Transmit control supply pin, 5 V (0.1-F decoupling capacitor to ground)
TX_REF 9 Reference Tx reference voltage
TXN 14 Analog LED driver out B, H-bridge output. Connect to LED.
TXP 15 Analog LED driver out B, H-bridge output. Connect to LED.
Input common-mode voltage output.
Connect a series resistor (1 k) and a decoupling capacitor (10 nF) to ground.
VCM 4 Reference
The voltage across the capacitor can be used to shield (guard) the INP, INM traces.
Expected voltage = 0.9 V.
VSS 8 Supply Substrate ground. Connect to common board ground.
Crystal oscillator pins.
XOUT 37 Digital Connect an external 8-MHz crystal between these pins with the correct load capacitor
(as specified by vendor) to ground.
Crystal oscillator pins.
XIN 38 Digital Connect an external 8-MHz crystal between these pins with the correct load capacitor
(as specified by vendor) to ground.
10 Submit Documentation Feedback Copyright 20122013, Texas Instruments Incorporated
Product Folder Links: AFE4490
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Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C005
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 5Hz B/W.
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Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C006
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA.)
Noise is calculated in 5Hz band.
46.0
46.2
46.4
46.6
46.8
47.0
47.2
47.4
47.6
47.8
48.0
3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0
L
E
D
_
D
R
V
_
S
U
P

C
u
r
r
e
n
t

(

A
)

LED_DRV_SUP Voltage (V) C003
With LED Current = 0mA
0
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400
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600
0 10 20 30 40 50
I
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h

Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C004
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 5Hz B/W.
400
500
600
700
800
900
2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
R
X

A
n
a
l
o
g

C
u
r
r
e
n
t

(

A
)

RX Supply Voltage (V)
Stage 2 & Amb Cancel Disabled
Stage 2 & Amb Cancel Enabled
C001
PRF = 600Hz
Stage 2 Gain = 4
RX_ANA_SUP = Rx_DIG_SUP
14.65
14.70
14.75
14.80
14.85
14.90
14.95
15.00
3.0 3.5 4.0 4.5 5.0
T
X
_
C
T
R
L
_
S
U
P

C
u
r
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e
n
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(

A
)

TX_CTRL_SUP Voltage (V) C002
PRF = 600Hz
A F E 4 4 9 0
www.ti.com SBAS602B DECEMBER 2012REVISED FEBRUARY 2013
TYP I CA L CHA RA CTE RI STI CS
At T
A
= +25C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and f
CLK
= 8 MHz, unless
otherwise noted.
F ig u r e 2. TO TA L Rx CURRE NT vs VO LTA GE F ig u r e 3. TX_CTRL_SUP CURRE NT vs VO LTA GE
F ig u r e 4 . LE D_DRV_SUP CURRE NT vs VO LTA GE F ig u r e 5. I NP UT- RE F E RRE D NO I SE CURRE NT vs
P LE TH CURRE NT (P RF = 10 0 Hz)
(1)
F ig u r e 6. I NP UT- RE F E RRE D NO I SE CURRE NT vs F ig u r e 7. I NP UT- RE F E RRE D NO I SE CURRE NT vs
P LE TH CURRE NT (P RF = 30 0 Hz) P LE TH CURRE NT (P RF = 60 0 Hz)
(1) Data at PRF = 625 Hz, 5% duty cycle.
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: AFE4490
10
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h

Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C011
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise.
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h

Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C012
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise.
10
11
12
13
14
15
16
0 10 20 30 40 50
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h

Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C009
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise.
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h

Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C010
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low pleth currents (0.125uA, 0.25uA & 0.5uA.)
RMS noise is calculated in 5Hz B/W & NFB is calculated using 6.6 u RMS noise.
0
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0 10 20 30 40 50
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h

Pleth Current ( A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C007
For each RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for Low
Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 5Hz band.
0
200
400
600
800
1000
1200
1400
0 10 20 30 40 50
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a
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h

Pleth Current ( A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C008
For each setting RF adjusted for Full-Scale Output.
Amb Cancellation & stage 2 Gain = 4 used for
Low Pleth currents (0.125uA, 0.25uA & 0.5uA).
Noise is calculated in 5Hz band.
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
TYP I CA L CHA RA CTE RI STI CS (con tin u e d )
At T
A
= +25C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and f
CLK
= 8 MHz, unless
otherwise noted.
F ig u r e 8. I NP UT- RE F E RRE D NO I SE CURRE NT vs F ig u r e 9 . I NP UT- RE F E RRE D NO I SE CURRE NT vs
P LE TH CURRE NT (P RF = 120 0 Hz) P LE TH CURRE NT (P RF = 250 0 Hz)
F ig u r e 10 . NO I SE - F RE E BI TS vs F ig u r e 11. NO I SE - F RE E BI TS vs
P LE TH CURRE NT (P RF = 10 0 Hz) P LE TH CURRE NT (P RF = 30 0 Hz)
F ig u r e 12. NO I SE - F RE E BI TS vs F ig u r e 13. NO I SE - F RE E BI TS vs
P LE TH CURRE NT (P RF = 120 0 Hz)
P LE TH CURRE NT (P RF = 60 0 Hz)
(2)
(2) Data at PRF = 625 Hz, 5% duty cycle.
12 Submit Documentation Feedback Copyright 20122013, Texas Instruments Incorporated
Product Folder Links: AFE4490
500
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200
100
0
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0 50 100 150 200 250
D
A
C

S
t
e
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E
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o
r

(
u
A
)

TX LED DAC Setting
C017
TX_REF = 0.5V
0
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60
80
100
0 50 100 150 200 250
T
X

C
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n
t

(
m
A
)

TX LED DAC Setting
Expected + 1%
Expected 1%
Actual DAC Current
C018
TX Reference Voltage = 0.5V
500
400
300
200
100
0
100
200
300
400
500
0 50 100 150 200 250
D
A
C

S
t
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p

E
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r

(
u
A
)

TX LED DAC Setting C015
TX_REF = 0.5V
500
400
300
200
100
0
100
200
300
400
500
0 50 100 150 200 250
D
A
C

S
t
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p

E
r
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o
r

(
u
A
)

TX LED DAC Setting C016
TX_REF = 0.5V
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h

Pleth Current (A)
Duty Cycle = 1%
Duty Cycle = 5%
Duty Cycle = 10%
Duty Cycle = 15%
Duty Cycle = 20%
Duty Cycle = 25%
C013
For each setting RF adjusted for Full-
Scale Output.
Amb Cancellation & stage 2 Gain = 4
used for Low Pleth currents (0.125uA,
0.25uA & 0.5uA).
RMS noise is calculated in 5Hz B/W &
NFB is calculated using 6.6 u RMS noise.
50
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80
90
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110
120
0 20 40 60 80 100
T
X

D
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a
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R
a
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e

(
d
B
)

% of Full-Scale LED Current
100mA Range
150mA Range
200mA Range
C014
A F E 4 4 9 0
www.ti.com SBAS602B DECEMBER 2012REVISED FEBRUARY 2013
TYP I CA L CHA RA CTE RI STI CS (con tin u e d )
At T
A
= +25C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and f
CLK
= 8 MHz, unless
otherwise noted.
F ig u r e 14 . NO I SE - F RE E BI TS vs F ig u r e 15. Tx DYNA MI C RA NGE
P LE TH CURRE NT (P RF = 250 0 Hz)
F ig u r e 16. DA C CURRE NT STE P vs F ig u r e 17. DA C CURRE NT STE P vs
Tx LE D SE TTI NG (Tx Ra n g e = 20 0 mA ) Tx LE D SE TTI NG (Tx Ra n g e = 150 mA )
F ig u r e 18. DA C CURRE NT STE P vs F ig u r e 19 . Tx CURRE NT LI NE A RI TY (10 0 - mA Ra n g e )
Tx LE D SE TTI NG (Tx Ra n g e = 10 0 mA )
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: AFE4490
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3

6
4

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8

6
9

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0

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1

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2

7
3

7
4

7
5

7
6

7
7

N
u
m
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r

o
f

O
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s

LED Current (mA)
C023
TX_RANGE = 150mA,
Data from 7737 devices
0
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1200
1
3
5

1
3
7

1
3
9

1
4
1

1
4
3

1
4
5

1
4
7

1
4
9

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5
1

1
5
3

1
5
5

1
5
7

1
5
9

1
6
1

1
6
3

1
6
5

N
u
m
b
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r

o
f

O
c
c
u
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n
c
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s

LED Current (mA)
C024
TX_RANGE = 150mA,
Data from 7737 devices
0
200
400
600
800
8

8
.
4

8
.
8

9
.
2

9
.
6

1
0

1
0
.
4

1
0
.
8

1
1
.
2

1
1
.
6

1
2

N
u
m
b
e
r

o
f

O
c
c
u
r
e
n
c
e
s

LED Current (mA)
C021
TX_RANGE = 150mA,
Data from 2326 devices
0
200
400
600
800
1000
1200
1400
1600
1800
2000
2200
3
0

3
1

3
2

3
3

3
4

3
5

3
6

3
7

3
8

3
9

4
0

N
u
m
b
e
r

o
f

O
c
c
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n
c
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s

LED Current (mA)
C022
TX_RANGE = 150mA,
Data from 7737 devices
0
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40
60
80
100
120
140
160
0 50 100 150 200 250
T
X

C
u
r
r
e
n
t

(
m
A
)

TX LED DAC Setting
Expected + 1%
Expected 1%
Actual DAC Current
C019
TX Reference Voltage = 0.75V
0
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40
60
80
100
120
140
160
180
200
0 50 100 150 200 250
T
X

C
u
r
r
e
n
t

(
m
A
)

TX LED DAC Setting
Expected + 1%
Expected 1%
Actual DAC Current
C020
TX Reference Voltage = 1.0V
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
TYP I CA L CHA RA CTE RI STI CS (con tin u e d )
At T
A
= +25C, RX_ANA_SUP = RX_DIG_SUP = 3.0 V, TX_CTRL_SUP = LED_DRV_SUP = 5 V, and f
CLK
= 8 MHz, unless
otherwise noted.
F ig u r e 20 . Tx CURRE NT LI NE A RI TY (150 - mA Ra n g e ) F ig u r e 21. Tx CURRE NT LI NE A RI TY (20 0 - mA Ra n g e )
F ig u r e 22. LE D CURRE NT WI TH F ig u r e 23. LE D CURRE NT WI TH
Tx DA C SE TTI NG = 17 (10 mA ) Tx DA C SE TTI NG = 60 (35 mA )
F ig u r e 24 . LE D CURRE NT WI TH F ig u r e 25. LE D CURRE NT WI TH
Tx DA C SE TTI NG = 120 (70 mA ) Tx DA C SE TTI NG = 255 (150 mA )
14 Submit Documentation Feedback Copyright 20122013, Texas Instruments Incorporated
Product Folder Links: AFE4490
Device
Digital
Filter
SPI
+
Buffer 4G ADC
+
TIA
+
Stage 2
Gain
Photodiode
CPD
Filter
S
P
I

I
n
t
e
r
f
a
c
e
Diagnostics
Timing
Controller
OSC
8 MHz
Diagnostic
Signals
INN
INP
R
X
_
A
N
A
_
G
N
D
VCM
DNC
(1)
DNC
(1)
B
G
V
S
S
T
X
_
R
E
F
T
X
_
C
T
R
L
_
S
U
P
L
E
D
_
D
R
V
_
G
N
D
L
E
D
_
D
R
V
_
G
N
D
TXN
TXP
L
E
D
_
D
R
V
_
G
N
D
L
E
D
_
D
R
V
_
S
U
P
L
E
D
_
D
R
V
_
S
U
P
R
X
_
D
I
G
_
G
N
D
AFE_PDN
DIAG_END
LED_ALM
PD_ALM/ADC Reset
SPICLK
SPISOMI
SPISIMO
SPISTE
ADC_RDY
RESET
C
L
K
O
U
T
R
X
_
D
I
G
_
S
U
P
R
X
_
D
I
G
_
G
N
D
R
X
_
A
N
A
_
S
U
P
R
X
O
U
T
N
R
X
O
U
T
P
R
X
_
A
N
A
_
G
N
D
X
O
U
T
X
I
N
R
X
_
A
N
A
_
S
U
P
R
X
_
A
N
A
_
G
N
D
DNC
(1)
Control
Reference
CF
CF
RF
RF
LED
Driver
LED Current
Control DAC
LED
CF
A F E 4 4 9 0
www.ti.com SBAS602B DECEMBER 2012REVISED FEBRUARY 2013
O VE RVI E W
The AFE4490 is a complete analog front-end (AFE) solution targeted for pulse-oximeter applications. The device
consists of a low-noise receiver channel, an LED transmit section, and diagnostics for sensor and LED fault
detection. To ease clocking requirements and provide the low-jitter clock to the AFE, an oscillator is also
integrated that functions from an external crystal. The device communicates to an external microcontroller or host
processor using an SPI interface. Figure 26 shows a detailed block diagram for the AFE4490. The blocks are
described in more detail in the following sections.
F ig u r e 26. De ta il e d Bl ock Dia g r a m
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: AFE4490
R C
F

F
Rx Sample Time
10
LED2
SLED2 CONVLED2
Amb
Amb
SLED1_amb
SLED1
SLED2_amb
CONVLED1
CONVLED2_amb
CONVLED1_amb
LED1
Rx
Ambient-cancellation current can be set digitally using SPI interface.
CF
CF
RF
RF
CPD
+
TIA
+
Stage 2
Gain
RF
RF
+
Buffer ADC
ADC
ADC Clock
ADC Convert
ADC Output Rate
PRF Sa/sec
I-V Amplifier Amb cancellation DAC Buffer Filter ADC
Ambient
DAC
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
RE CE I VE R CHA NNE L
This section describes the receiver channel functionality.
Re ce ive r F r on t- E n d
The receiver consists of a differential current-to-voltage (I-V) transimpedance amplifier that converts the input
photodiode current into an appropriate voltage, as shown in Figure 27. The feedback resistor of the amplifier (R
F
)
is programmable to support a wide range of photodiode currents. Available R
F
values include: 1 M, 500 k,
250 k, 100 k, 50 k, 25 k, and 10 k.
F ig u r e 27. Re ce ive r F r on t- E n d
The R
F
amplifier and the feedback capacitor (C
F
) form a low-pass filter for the input signal current. Always ensure
that the low-pass filter has sufficiently high bandwidth (as shown by Equation 1) because the input current
consists of pulses. For this reason, the feedback capacitor is also programmable. Available C
F
values include:
5 pF, 10 pF, 25 pF, 50 pF, 100 pF, and 250 pF. Any combination of these capacitors can also be used.
(1)
The output voltage of the I-V amplifier includes the pleth component (the desired signal) and a component
resulting from the ambient light leakage. The I-V amplifier is followed by the second stage, which consists of a
current digital-to-analog converter (DAC) that sources the cancellation current and an amplifier that gains up the
pleth component alone. The amplifier has five programmable gain settings: 1, 1.5, 2, 3, and 4. The gained-up
pleth signal is then low-pass filtered (500-Hz bandwidth) and buffered before driving a 22-bit ADC. The current
DAC has a cancellation current range of 10 A with 10 steps (1 A each). The DAC value can be digitally
specified with the SPI interface.
The output of the ambient cancellation amplifier is separated into LED2 and LED1 channels. When LED2 is on,
the amplifier output is filtered and sampled on capacitor C
R
. Similarly, the LED1 signal is sampled on the C
LED1
capacitor when LED1 is ON. In between the LED2 and LED1 pulses, the idle amplifier output is sampled to
estimate the ambient signal on capacitors C
LED2_amb
and C
LED1_amb
.
The sampling duration is termed the Rx sample time and is programmable for each signal, independently.
Sampling can start after the I-V amplifier output is stable (to account for LED and cable settling times). The Rx
sample time is used for all dynamic range calculations; the minimum time supported is 50 s.
16 Submit Documentation Feedback Copyright 20122013, Texas Instruments Incorporated
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Device
Digital Control for Ambient-Cancellation DAC
Rx
Digital
LED2 Data
ADC Output Rate
PRF Samples per Second
Ambient (LED2)
Data
LED1 Data
Ambient (LED1)
Data
SPI
Block
SPI
Interface
Host Processor
Ambient Estimation Block
Ambient information is available in the host
processor.
The processor can:
* Read ambient data
* Estimate ambient value to
be cancelled
* Set the value to be used by the ambient
cancellation DAC using the SPI of AFE
Front End
(LED2 Ambient)
Data
(LED1 Ambient)
Data
ADC
A F E 4 4 9 0
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A single, 22-bit ADC converts the sampled LED2, LED1, and ambient signals sequentially. Each conversion
takes a maximum of 25% of the pulse repetition period (PRP) and provides a single digital code at the ADC
output. As discussed in the Receiver Timing section, the conversions are staggered so that the LED2 conversion
starts after the end of the LED2 sample phase, and so on. This configuration also means that the Rx sample
time for each signal is no greater than 25% of the pulse repetition period.
Note that four data streams are available at the ADC output (LED2, LED1, ambient LED2, and ambient LED1) at
the same rate as the pulse repetition frequency. The ADC is followed by a digital ambient subtraction block that
additionally outputs the (LED2 ambient LED2) and (LED1 ambient LED1) data values.
A mbie n t Ca n ce l l a tion Sche me
The receiver provides digital samples corresponding to ambient duration. The host processor (external to the
AFE) can use these ambient values to estimate the amount of ambient light leakage. The processor must then
set the value of the ambient cancellation DAC using the SPI, as shown in Figure 28.
F ig u r e 28. A mbie n t Ca n ce l l a tion Loop (Cl os e d by the Hos t P r oce s s or )
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 17
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V = 2
DIFF
I
PLETH

R
F
R
I
+ I
AMB

R
F
R
I
- I
CANCEL
R
G
Rf
Cf
Rf
Cf
Rx
V
DIFF
Ri
Ri
Rg
Rg
I
PLETH
+ I
AMB
I
CANCEL
Value of I
CANCEL
set using
the SPI interface.
I
CANCEL
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
Using the set value, the ambient cancellation stage subtracts the ambient component and gains up only the pleth
component of the received signal, as shown in Figure 29.
The amplifier gain is programmable to 1, 1.5, 2, 3, and 4.
F ig u r e 29 . F r on t- E n d (I - V A mpl if ie r a n d Ca n ce l l a tion Sta g e )
The differential output of the second stage is V
DIFF
, as given by Equation 2:
Where:
R
I
= 100 k,
I
PLETH
= photodiode current pleth component,
I
AMB
= photodiode current ambient component, and
I
CANCEL
= the cancellation current DAC value (as estimated by the host processor). (2)
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Re ce ive r Con tr ol Sig n a l s
LE D2 s a mpl e pha s e (S
LE D2
): When this signal is high, the amplifier output corresponds to the LED2 on-time.
The amplifier output is filtered and sampled into capacitor C
LED2
. To avoid settling effects resulting from the LED
or cable, program S
LED2
to start after the LED turns on. This settling delay is programmable.
A mbie n t s a mpl e pha s e (S
LE D2_a mb
): When this signal is high, the amplifier output corresponds to the LED2 off-
time and can be used to estimate the ambient signal (for the LED2 phase). The amplifier output is filtered and
sampled into capacitor C
LED2_amb
.
LE D1 s a mpl e pha s e (S
LE D1
): When this signal is high, the amplifier output corresponds to the LED1 on-time.
The amplifier output is filtered and sampled into capacitor C
LED1
. To avoid settling effects resulting from the LED
or cable, program S
LED1
to start after the LED turns on. This settling delay is programmable.
A mbie n t s a mpl e pha s e (S
LE D1_a mb
): When this signal is high, the amplifier output corresponds to the LED1 off-
time and can be used to estimate the ambient signal (for the LED1 phase). The amplifier output is filtered and
sampled into capacitor C
LED1_amb
.
LE D2 con ve r t pha s e (CO NV
LE D2
): When this signal is high, the voltage sampled on C
LED2
is buffered and
applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At
the end of the conversion, the ADC provides a single digital code corresponding to the LED2 sample.
A mbie n t con ve r t pha s e s (CO NV
LE D2_a mb
, CO NV
LE D1_a mb
): When this signal is high, the voltage sampled on
C
LED2_amb
(or C
LED1_amb
) is buffered and applied to the ADC for conversion. The conversion time duration is
always 25% of the pulse repetition period. At the end of the conversion, the ADC provides a single digital code
corresponding to the ambient sample.
LE D1 con ve r t pha s e (CO NV
LE D1
): When this signal is high, the voltage sampled on C
LED1
is buffered and
applied to the ADC for conversion. The conversion time duration is always 25% of the pulse repetition period. At
the end of the conversion, the ADC provides a single digital code corresponding to the LED1 sample.
Re ce ive r Timin g
See Figure 30 for a timing diagram detailing the control signals related to the LED on-time, Rx sample time, and
the ADC conversion times for each channel.
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 19
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Photodiode Current
Or
I-V Output
Ambient Level
(Dark Level)
S
R
,
Sample RED
S
R_amb
,
Sample Ambient
(RED Phase)
CONV
R
,
RED ADC Converts
(RED Ambient)
S
IR
,
Sample IR
S
IR_amb
,
Sample Ambient
(IR Phase)
CONV
IR
,
IR ADC Converts
(IR Ambient)
Plethysmograph Signal
ADCLK
R
,
Red ADC
Sample Clock
ADCLK
IR
,
IR ADC
Sample Clock
RED

N
RED

N+1
RED ADC
Output Data
IR

N-1
IR

N
N
N+2
N+1
N
N+1
IR ADC
Output Data
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
NOTE: Relationship to the AFE4490EVM is: LED1 = IR and LED2 = RED.
F ig u r e 30 . Rx Timin g Dia g r a m
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8-MHz Crystal
Timer
Module
Diagnostics
Module
ADC
Oscillator
Divide-
by-2
CLKOUT
4 MHz
XIN XOUT
A F E 4 4 9 0
www.ti.com SBAS602B DECEMBER 2012REVISED FEBRUARY 2013
CLO CKI NG A ND TI MI NG SI GNA L GE NE RA TI O N
The crystal oscillator generates a master clock signal using an external 8-MHz crystal. A divide-by-2 block
converts the 8-MHz clock to 4 MHz, which is used by the AFE to operate the timer modules, ADC, and
diagnostics. The 4-MHz clock is buffered and output from the AFE in order to clock an external microcontroller.
The clocking functionality is shown in Figure 31.
F ig u r e 31. A F E Cl ockin g
TI ME R MO DULE
See Figure 32 for a timing diagram detailing the various timing edges that are programmable using the timer
module. The rising and falling edge positions of 11 signals can be controlled. The module uses a single 16-bit
counter (running off of the 4-MHz clock) to set the time-base.
All timing signals are set with reference to the pulse repetition period (PRP). Therefore, a dedicated compare
register compares the 16-bit counter value with the reference value specified in the PRF register. Every time that
the 16-bit counter value is equal to the reference value in the PRF register, the counter is reset to '0'.
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 21
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LED1 (IR LED)
On Signal
LED2 (RED LED)
On Signal
t
LED
LED on-time
d 0.25 T.
Rx sample time = t
LED
settle time.
0

T
0
.
2
5

T
0
.
5
0

T
0
.
7
5

T
1
.
0

T
ADC Conversion
Pulse Repetition Period
T = 1 / PRF
ADC Reset
ADC_RDY Pin
CONV
LED1_amb
,
Convert Ambient Sample
[LED1 (IR) Phase]
CONV
LED1
,
Convert LED1 (IR) Sample
CONV
LED2_amb
,
Convert Ambient Sample
[LED2 (RED) Phase]
CONV
LED2
,
Convert LED2 (RED) Sample
SLED2,
Sample LED2 (RED)
SLED2_amb,
Sample Ambient
[LED2 (RED) Phase]
SLED1,
Sample LED1 (IR)
SLED1_amb,
Sample Ambient
[LED1 (IR) Phase]
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
NOTE: Programmable edges are shown in blue and red.
F ig u r e 32. A F E Con tr ol Sig n a l s
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Timer Compare
16-Bit Register 11
16-Bit Counter
Timer Compare
16-Bit Register 1
Start
Stop
Timer Compare
16-Bit Register 2
Start
Stop
Timer Compare
16-Bit Register 3
Start
Stop
Timer Compare
16-Bit Register 4
Start
Stop
Timer Compare
16-Bit Register 5
Start
Stop
Timer Compare
16-Bit Register 6
Start
Stop
Timer Compare
16-Bit PRF Register
PRF
Pulse
Timer Compare
16-Bit Register 7
Start
Stop
Timer Compare
16-Bit Register 8
Start
Stop
Timer Compare
16-Bit Register 9
Start
Stop
Timer Compare
16-Bit Register 10
Start
Stop
START-A
STOP-A
START-B
STOP-B
START-C
STOP-D
START-D
STOP-D
RED LED
S
R
IR LED
S
R
SR
Sample RED
S
R
S
R
S
R
S
R
S
R
S
R
S
R
S
R
Reset
Counter
Reset
SIR
Sample IR
SR_amb,
Sample Ambient
(red phase)
SIR_amb,
Sample Ambient
(IR phase)
CONVR,
Convert RED Sample
CONVIR,
Convert IR Sample
CONVIR_amb,
Convert Ambient Sample
(IR Phase)
CONVR_amb,
Convert Ambient Sample
(RED Phase)
ADC
Conversion
Timer Module
Enable
En
En
En
En
En
En
En
En
En
En
En
En
CLKIN
R
e
s
e
t
E
n
a
b
l
e
START
STOP
Set
Reset
Enable
Timer Compare Register
Start Reference Register
Stop Reference Register
Counter
Input
Output
Signal
A F E 4 4 9 0
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For the 11 signals in Figure 30, the start and stop edge positions are programmable with respect to the PRF
period. Each signal uses a separate timer compare module that compares the counter value with
preprogrammed reference values for the start and stop edges. All reference values can be set using the SPI
interface.
When the counter value equals the start reference value, the output signal is set. When the counter value equals
the stop reference value, the output signal is reset. Figure 33 shows a diagram of the timer compare register.
With a 4-MHz clock, the edge placement resolution is 0.25 s. The ADC conversion signal requires four pulses in
each PRF clock period. The 11th timer compare register uses four sets of start and stop registers to control the
ADC conversion signal.
F ig u r e 33. Compa r e Re g is te r
The ADC conversion signal requires four pulses in each PRF clock period. Timer compare register 11 uses four
sets of start and stop registers to control the ADC conversion signal, as shown in Figure 34.
F ig u r e 34 . Time r Mod u l e
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Us in g the Time r Mod u l e
The timer module registers can be used to program the start and end instants in units of 4-MHz clock cycles.
These timing instants and the corresponding registers are listed in Table 2.
Note that the device does not restrict the values in these registers; thus, the start and end edges can be
positioned anywhere within the pulse repetition period. Care must be taken by the user to program suitable
values in these registers to avoid overlapping the signals and to make sure none of the edges exceed the value
programmed in the PRP register. Writing the same value in the start and end registers results in a pulse duration
of one clock cycle. The following steps describe the timer sequencing configuration:
1. With respect to the start of the PRP period (indicated by timing instant t
0
in Figure 35), the sequence of
conversions must be followed in order: convert LED2 LED2 ambient LED1 LED1 ambient.
2. Also, starting from t
0
, the sequence of sampling instants must be staggered with respect to the respective
conversions as follows: sample LED2 ambient LED1 LED1 ambient LED2.
3. Finally, align the edges for the two LED pulses with the respective sampling instants.
Ta bl e 2. Cl ock E d g e Ma ppin g to SP I Re g is te r s
TI ME I NSTA NT
(Se e F ig u r e 35 a n d E XA MP LE
F ig u r e 36) DE SCRI P TI O N CO RRE SP O NDI NG RE GI STE R A DDRE SS A ND RE GI STE R BI TS (De cima l )
t
0
Start of pulse repetition period No register control
t
1
Start of sample LED2 pulse Sample LED2 start count (bits 15-0 of register 01h) 4800
t
2
End of sample LED2 pulse Sample LED2 end count (bits 15-0 of register 02h) 6399
t
3
Start of LED2 pulse LED2 start count (bits 15-0 of register 03h) 4800
t
4
End of LED2 pulse LED2 end count (bits 15-0 of register 04h) 6399
t
5
Start of sample LED2 ambient pulse Sample ambient LED2 start count (bits 15-0 of register 05h) 0
t
6
End of sample LED2 ambient pulse Sample ambient LED2 end count (bits 15-0 of register 06h) 1599
t
7
Start of sample LED1 pulse Sample LED1 start count (bits 15-0 of register 07h) 1600
t
8
End of sample LED1 pulse Sample LED1 end count (bits 15-0 of register 08h) 3199
t
9
Start of LED1 pulse LED1 start count (bits 15-0 of register 09h) 1600
t
10
End of LED1 pulse LED1 end count (bits 15-0 of register 0Ah) 3199
t
11
Start of sample LED1 ambient pulse Sample ambient LED1 start count (bits 15-0 of register 0Bh) 3200
t
12
End of sample LED1 ambient pulse Sample ambient LED1 end count (bits 15-0 of register 0Ch) 4700
t
13
Start of convert LED2 pulse LED2 convert start count (bits 15-0 of register 0Dh) 0
t
14
End of convert LED2 pulse LED2 convert end count (bits 15-0 of register 0Eh) 1599
t
15
Start of convert LED2 ambient pulse LED2 ambient convert start count (bits 15-0 of register 0Fh) 1600
t
16
End of convert LED2 ambient pulse LED2 ambient convert end count (bits 15-0 of register 10h) 3199
t
17
Start of convert LED1 pulse LED1 convert start count (bits 15-0 of register 11h) 3200
t
18
End of convert LED1 pulse LED1 convert end count (bits 15-0 of register 12h) 4799
t
19
Start of convert LED1 ambient pulse LED1 ambient convert start count (bits 15-0 of register 13h) 4800
t
20
End of convert LED1 ambient pulse LED1 ambient convert end count (bits 15-0 of register 14h) 6399
t
21
Start of first ADC conversion reset pulse ADC reset 0 start count (bits 15-0 of register 15h) 0
t
22
End of first ADC conversion reset pulse ADC reset 0 end count (bits 15-0 of register 16h) 0
t
23
Start of second ADC conversion reset pulse ADC reset 1 start count (bits 15-0 of register 17h) 1600
t
24
End of second ADC conversion reset pulse ADC reset 0 end count (bits 15-0 of register 18h) 1600
t
25
Start of third ADC conversion reset pulse ADC reset 2 start count (bits 15-0 of register 19h) 3200
t
26
End of third ADC conversion reset pulse ADC reset 0 end count (bits 15-0 of register 1Ah) 3200
t
27
Start of fourth ADC conversion reset pulse ADC reset 3 start count (bits 15-0 of register 1Bh) 4800
t
28
End of fourth ADC conversion reset pulse ADC reset 0 end count (bits 15-0 of register 1Ch) 4800
t
29
End of pulse repetition period Pulse repetition period count (bits 15-0 of register 1Dh) 6399
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LED1 (IR LED)
On Signal
LED2 (RED LED)
On Signal
t
0
ADC Conversion
Pulse Repetition Period,
One Cycle
ADC Reset
CONV
LED1_amb
,
Convert Ambient Sample
[LED1 (IR) Phase]
CONV
LED1
,
Convert LED1 (IR) Sample
CONV
LED2_amb
,
Convert Ambient Sample
[LED2 (RED) Phase]
CONV
LED2
,
Convert LED2 (RED) Sample
S
LED2
,
Sample LED2 (RED)
S
LED2_amb
,
Sample Ambient
[LED2 (RED) Phase]
S
LED1
,
Sample LED1 (IR)
S
LED1_amb
,
Sample Ambient
[LED1 (IR) Phase]
t
29
t
3
t
4
t
10
t
9
t
5
t
6
t
7
t
8
t
11 t
12
t
2
t
1
t
13 t
14
t
15
t
16
t
17 t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
A F E 4 4 9 0
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(1) RED = LED2, IR = LED1.
F ig u r e 35. P r og r a mma bl e Cl ock E d g e s
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 25
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t
0 t
29
ADC Conversion
Pulse Repetition Period,
One Cycle
t
14
t
15
t
16
t
13
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
ADC Reset
CONV
LED1_amb
,
Convert Ambient Sample
[LED1 (IR) Phase]
CONV
LED1
,
Convert LED1 (IR) Sample
CONV
LED2_amb
,
Convert Ambient Sample
[LED2 (RED) Phase]
CONV
LED2
,
Convert LED2 (RED) Sample
One 4-MHz
Clock Cycle
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
(1) RED = LED2, IR = LED1.
F ig u r e 36. Re l a tion s hip Be twe e n the A DC Re s e t a n d A DC Con ve r s ion Sig n a l s
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ADC Clock
ADC Convert
LED2 Data
ADC Output Rate
PRF Samples per Second
ADC
ADC
Ambient
(LED2) Data
LED1 Data
Ambient
(LED1) Data
Rx Digital
Averager
Register
30
Number of Averages
22-Bits
Register
42
LED2 Data
Register
43
LED2_Ambient Data
Register
44
LED1 Data
Register
45
LED1_Ambient Data
ADC Reset
ADC Reset
A F E 4 4 9 0
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A DC O P E RA TI O N A ND A VE RA GI NG MO DULE
The ADC reset signal must be positioned at 25% intervals of the pulse repetition period (that is, 0%, 25%, 50%,
and 75%). After the falling edge of the ADC reset signal, the ADC conversion phase starts. Each ADC
conversion takes 50 s.
There are two modes of operation: without averaging and with averaging. The averaging mode can average
multiple ADC samples and reduce noise to improve dynamic range because the ADC conversion time is usually
shorter than 25% of the pulse repetition period. Figure 37 shows a diagram of the averaging module.
F ig u r e 37. A ve r a g in g Mod u l e
O pe r a tion Withou t A ve r a g in g
In this mode, the ADC outputs a digital sample one time for every 50 s. At the next rising edge of the ADC reset
signal, the first 22-bit conversion value is written into the result registers sequentially as follows (see Figure 38):
At the 25% reset signal, the first 22-bit ADC sample is written to register 2Ah.
At the 50% reset signal, the first 22-bit ADC sample is written to register 2Bh.
At the 75% reset signal, the first 22-bit ADC sample is written to register 2Ch.
At the next 0% reset signal, the first 22-bit ADC sample is written to register 2Dh. The contents of registers
2Ah and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register
2Fh.
At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.
O pe r a tion With A ve r a g in g
In this mode, all ADC digital samples are accumulated and averaged after every 50 s. At the next rising edge of
the ADC reset signal, the average value (22-bit) is written into the output registers sequentially as follows (see
Figure 39):
At the 25% reset signal, the averaged 22-bit word is written to register 2Ah.
At the 50% reset signal, the averaged 22-bit word is written to register 2Bh.
At the 75% reset signal, the averaged 22-bit word is written to register 2Ch.
At the next 0% reset signal, the averaged 22-bit word is written to register 2Dh. The contents of registers 2Ah
and 2Bh are written to register 2Eh and the contents of registers 2Ch and 2Dh are written to register 2Fh.
At the rising edge of the ADC_RDY signal, the contents of all six result registers can be read out.
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 27
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ADC Conversion
Pulse Repetition Period
T = 1 / PRF
ADC Reset
ADC RDY Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0% 25% 50% 75%
ADC Data
ADC data 1 are
written into
register 42.
ADC data 5 are
written into
register 43.
ADC data 9 are
written into
register 44.
ADC data 13 are written into
register 45.
Register 42 and register 43
are written into register 46.
Register 44 and register 45
are written into register 47.
0%
17 18 19 20
0 T 1.0 T
NUMAV[7:0] + 1 =
0.25 Pulse Repetition Period
50 s m
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
The number of samples to be used per conversion phase is specified in the CONTROL1 register (NUMAV[7:0]).
The user must specify the correct value for the number of averages, as described in Equation 3:
(3)
When the number of averages is '0', the averaging is disabled and only one ADC sample is written to the result
registers.
Note that he number of average conversions is limited by 25% of the PRF. For example, eight samples can be
averaged with PRF = 625 Hz, and four samples can be averaged with PRF = 1250 Hz.
F ig u r e 38. A DC Da ta Withou t A ve r a g in g (Whe n Nu mbe r of A ve r a g e s = 0 )
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ADC Conversion
Pulse repetition period
T = 1/PRF
ADC Reset
ADC_RDY Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
0% 25% 50% 75%
ADC Data
Average of
ADC data 1 to 3 are
written into
register 42.
Average of
ADC data 5 to 7
are written into
register 43.
Average of
ADC data 9 to 11 are
written into
register 44.
Average of
ADC data 13 to 15 are written
into register 45.
Register 42 and register 43
are written into register 46.
Register 44 and register 45
are written into register 47.
0%
17 18 19 20
0 T 1.0 T
A F E 4 4 9 0
www.ti.com SBAS602B DECEMBER 2012REVISED FEBRUARY 2013
NOTE: Example is with three averages. The value of the NUMAVG[7:0] register bits = 2.
F ig u r e 39 . A DC Da ta with A ve r a g in g E n a bl e d
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Links: AFE4490
Clocking
Internal
ADC
+
TIA
RXOUTP
+
Stage 2
Gain
RXOUTN
INP
INN
Device
E
x
t
e
r
n
a
l


A
D
C
PD_ALM
ADC_RDY
Use the ADC_Reset
signal on the PD_ALM pin
to clock the external ADC.
Use ADC_RDY to
sync the external
ADC with the AFE.
ADC
+
TIA
RXOUTP
+
Stage 2
Gain
RXOUTN
INP
INN
Device
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
A F E A NA LO G O UTP UT MO DE (A DC Bypa s s Mod e )
The ADC bypass mode brings out the analog output voltage of the receiver front-end on two pins (RXOUTP,
RXOUTN), around a common-mode voltage of approximately 0.9 V. In this mode, the internal ADC of the
AFE4490 is disabled. Figure 40 shows a block diagram of this mode.
F ig u r e 4 0 . A F E 4 4 9 0 Se t to A DC Bypa s s Mod e
In ADC bypass mode, one of the internal clocks (ADC_Reset) can be brought out on the PD_ALM pin, as shown
in Figure 41. This signal can be used to convert each of the four phases (within every pulse repetition period).
Additionally, the ADC_RDY signal can be used to synchronize the external ADC with the AFE. See Figure 42 for
the timing of this mode.
F ig u r e 4 1. A F E 4 4 9 0 in A DC Bypa s s Mod e with A DC_Re s e t to P D_A LM P in
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LED1 (IR LED)
On Signal
LED2 (Red LED)
On Signal
t
0
ADC_RDY
(Pin 28)
Pulse Repetition Period,
One Cycle
ADC Reset
(Pin 23)
S
LED2
,
Sample LED2 (RED)
S
LED2_amb
,
Sample Ambient
[LED2 (RED) Phase]
S
LED1
,
Sample LED1 (IR)
S
LED1_amb
,
Sample Ambient
[LED1 (IR) Phase]
t
29
t
3
t
4
t
10
t
9
t
5
t
6
t
7
t
8
t
11 t
12
t
2
t
1
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
A F E 4 4 9 0
www.ti.com SBAS602B DECEMBER 2012REVISED FEBRUARY 2013
NOTE: RED = LED2, IR = LED1.
F ig u r e 4 2. A F E 4 4 9 0 A n a l og O u tpu t Mod e (A DC Bypa s s ) Timin g Dia g r a m
In ADC bypass mode, the ADC reset signal can be used to start conversions with the external ADC. Use
registers 15h through 1Ch to position the ADC reset signal edges appropriately. Also, use the EN_RSTCLK on
the PD_ALM pin register bit to bring out the ADC reset signal to the PD_ALM pin. ADC_RDY can be used to
indicate the start of the pulse repetition period to the external ADC.
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Links: AFE4490
RX_ANA_SUP
(2.0 V to 3.6 V)
I/O
Pins
Device
1.8 V
1.8 V
RX_DIG_SUP
(2.0 V to 3.6 V)
RX_ANA_SUP to
1.8-V Regulator
Rx Analog Modules
RX_DIG_SUP to
1.8-V Regulator
Rx Digital
Rx I/O
Block
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
RE CE I VE R SUBSYSTE M P O WE R P A TH
The block diagram in Figure 43 shows the AFE4490 Rx subsystem power routing.
F ig u r e 4 3. Re ce ive Su bs ys te m P owe r Rou tin g
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LED
Current
Control
8-Bit Resolution
LED2 Current
Reference
LED1 Current
Reference
H-Bridge
Driver
H-Bridge
LED2_ON
LED1_ON
LED2_ON
Or
LED1_ON
Register LED2 Current Reference
Register LED1 Current Reference
5-V Supply
Tx
I
LED
C
BULK
H-Bridge Supply
External
Supply
A F E 4 4 9 0
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TRA NSMI T SE CTI O N
The transmit section integrates the LED driver and the LED current control section with 8-bit resolution. This
integration is designed to meet the specified dynamic range (based on a 1-sigma LED current noise).
The LED2 and LED1 reference currents can be independently set. The current source (I
LED
) locally regulates and
ensures that the actual LED current tracks the specified reference.
Two LED driver schemes are supported:
An H-bridge drive for a two-terminal back-to-back LED package, as shown in Figure 44. The minimum H-
bridge supply voltage must be 2.5 V + (maximum voltage drop across the LED).
A push-pull drive for a three-terminal LED package; see Figure 45. The minimum external supply voltage =
2.0 V + (maximum voltage drop across the LED). This value is the nominal value and depends on the registry
LED current settings (refer to the LED_RANGE[1:0] bits in the LEDCNTRL register).
F ig u r e 4 4 . Tr a n s mit: H- Br id g e Dr ive
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Product Folder Links: AFE4490
LED
Current
Control
8-Bit Resolution
LED2 Current
Reference
LED1 Current
Reference
H-Bridge
Driver
LED2_ON
LED1_ON
LED2_ON
Or
LED1_ON
Register RED Current Reference
Register IR Current Reference
Tx
I
LED
C
BULK
External
Supply
5-V Supply
H-Bridge Supply
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
F ig u r e 4 5. Tr a n s mit: P u s h- P u l l LE D Dr ive f or Common A n od e LE D Con f ig u r a tion
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50uA
0 mA to 200 mA
(See the LEDRANGE bits
in the LEDCNTRL register.)
LED_ON
1 PA
TX_CTRL_SUP_5V
LED_DRV_SUP_5V
Device
Tx LED
Bridge
LED
Current
Control
DAC
Tx Reference
and Control
A F E 4 4 9 0
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Tr a n s mitte r P owe r P a th
The block diagram in Figure 46 shows the AFE4490 Tx subsystem power routing.
F ig u r e 4 6. Tr a n s mit Su bs ys te m P owe r Rou tin g
LE D P owe r Re d u ction Du r in g P e r iod s of I n a ctivity
The diagram in Figure 47 shows how LED bias current passes 50 A whenever LED_ON occurs. In order to
minimize power consumption in periods of inactivity, the LED_ON control must be turned off.
F ig u r e 4 7. LE D Bia s Cu r r e n t
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 35
Product Folder Links: AFE4490
To Rx Front-End
INM
INP
Cable
Internal
LED_DRV_SUP
Internal
LED_DRV_SUP
10 k: 10 k:
10 k: 10 k:
1 PA
Rx On/Off
Rx On/Off
GND Wires
PD Wires
LED Wires
Cable Legend
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
DI A GNO STI CS
The device includes diagnostics to detect open or short conditions of the LED and photosensor, LED current
profile feedback, and cable on or off detection.
P hotod iod e - Sid e F a u l t De te ction
Figure 48 shows the diagnostic for the photodiode-side fault detection.
F ig u r e 4 8. P hotod iod e Dia g n os tic
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C
D
S
W
1
S
W
4
S
W
3
S
W
2
Cable
GND Wires
PD Wires
LED Wires
Internal
LED_DRV_SUP
TX_OUTP
TX_OUTM
10 k: 10 k:
L
E
D

1
L
E
D

2
Cable Legend
A F E 4 4 9 0
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Tr a n s mitte r - Sid e F a u l t De te ction
Figure 49 shows the diagnostic for the transmitter-side fault detection.
F ig u r e 4 9 . Tr a n s mitte r Dia g n os tic
Copyright 20122013, Texas Instruments Incorporated Submit Documentation Feedback 37
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Diagnostic State Machine
t
WIDTH
= Four 4-MHz
Clock Cycles
Diagnostic State
Machine
DIAG_END Pin
DIAG_EN Register Bit = 1
Diagnostic Ends
t
DIAG
Diagnostic Starts
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
Dia g n os tics Mod u l e
The diagnostics module, when enabled, checks for nine types of faults sequentially. The results of all faults are
latched in 11 separate flags. At the end of the sequence, the state of the 11 flags are combined to generate two
interrupt signals: PD_ALM for photodiode-related faults and LED_ALM for transmit-related faults. The status of all
flags can also be read using the SPI interface. Table 3 details each fault and flag used. Note that the diagnostics
module requires all AFE blocks to be enabled in order to function reliably.
Ta bl e 3. F a u l t a n d F l a g Dia g n os tics
(1)
MO DULE SE Q. F A ULT F LA G1 F LA G2 F LA G3 F LA G4 F LA G5 F LA G6 F LA G7 F LA G8 F LA G9 F LA G10 F LA G11
No fault 0 0 0 0 0 0 0 0 0 0 0
Rx INP cable
1 1
shorted to LED cable
Rx INM cable
2 1
shorted to LED cable
Rx INP cable
PD 3 shorted to GND 1
cable
Rx INM cable
4 shorted to GND 1
cable
5 PD open or shorted 1 1
Tx OUTM line
6 shorted to GND 1
cable
Tx OUTP line
LED
7 shorted to GND 1
cable
8 LED open or shorted 1 1
9 LED open or shorted 1
(1) Resistances below 10 k are considered to be shorted.
Figure 50 shows the timing for the diagnostic function.
F ig u r e 50 . Dia g n os tic Timin g Dia g r a m
By default, the diagnostic function takes t
DIAG
= 8 ms to complete after the DIAG_EN register bit is enabled. By
setting the EN_SLOW_DIAG register bit (CONTROL2 register, bit D8) the diagnostic time can be increased to 16
ms.
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A7 A6 A1 A0 D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0
SPISTE
SPISIMO
SCLK
Don't care, can be high or low.
A F E 4 4 9 0
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SE RI A L P RO GRA MMI NG I NTE RF A CE
The SPI-compatible serial interface consists of four signals: SCLK (serial clock), SPISOMI (serial interface data
output), SPISIMO (serial interface data input), and SPISTE (serial interface enable).
The serial clock (SCLK) is the serial peripheral interface (SPI) serial clock. SCLK shifts in commands and shifts
out data from the device. SCLK features a Schmitt-triggered input and clocks data out on SPISOMI. Data are
clocked in on the SPISIMO pin. Even though the input has hysteresis, TI recommends keeping SCLK as clean
as possible to prevent glitches from accidentally shifting the data. When the serial interface is idle, hold SCLK
low.
The SPISOMI (SPI serial out master in) pin is used with SCLK to clock out the AFE4490 data. The SPISIMO
(SPI serial in master out) pin is used with SCLK to clock in data to the AFE4490. The SPISTE (SPI serial
interface enable) pin enables the serial interface to clock data on the SPISIMO pin in to the device.
RE A DI NG A ND WRI TI NG DA TA
The device has a set of internal registers that can be accessed by the serial programming interface formed by
the SPISTE, SCLK, SPISIMO, and SPISOMI pins.
Wr itin g Da ta
When SPISTE is low,
Serially shifting bits into the device is enabled.
Serial data (on the SPISIMO pin) are latched at every SCLK rising edge.
The serial data are loaded into the register at every 32nd SCLK rising edge.
In case the word length exceeds a multiple of 32 bits, the excess bits are ignored. Data can be loaded in
multiples of 32-bit words within a single active SPISTE pulse. The first eight bits form the register address and
the remaining 24 bits form the register data. Figure 51 shows a diagram of the write timing.
F ig u r e 51. A F E SP I Wr ite Timin g Dia g r a m
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A7 A6 A1 A0
SPISTE
SPISIMO
SCLK
Don't care, can be high or low.
D23 D22 D17 D16 D15 D14 D9 D8 D7 D6 D1 D0 SPISOMI
A F E 4 4 9 0
SBAS602B DECEMBER 2012REVISED FEBRUARY 2013 www.ti.com
Re a d in g Da ta
The AFE4490 includes a mode where the contents of the internal registers can be read back on the SPISOMI
pin. This mode may be useful as a diagnostic check to verify the serial interface communication between the
external controller and the AFE. To enable this mode, first set the SPI_READ register bit using the SPI write
command, as described in the Writing Data section. In the next command, specify the SPI register address with
the desired content to be read. Within the same SPI command sequence, the AFE outputs the contents of the
specified register on the SPISOMI pin. Figure 52 shows a timing diagram for the SPI read operation.
(1) The SPI_READ register bit must be enabled before attempting a serial readout from the AFE.
(2) Specify the register address of the content that must be readback on bits A[7:0].
(3) The AFE outputs the contents of the specified register on the SPISOMI pin.
F ig u r e 52. A F E SP I Re a d Timin g Dia g r a m
(1)(2)(3)
Re g is te r I n itia l iza tion
After power-up, the internal registers must be initialized to the default values. This initialization can be done in
one of two ways:
Through a hardware reset by applying a low-going pulse on the RESET pin, or
By applying a software reset. Using the serial interface, set SW_RESET (bit D3 in register 00h) high. This
setting initializes the internal registers to the default values and then self-resets to '0'. In this case, the RESET
pin is kept high (inactive).
A F E SP I I n te r f a ce De s ig n Con s id e r a tion s
Note that when the AFE4490 is deselected, the SPISOMI, CLKOUT, ADC_RDY, PD_ALM, LED_ALM, and
DIAG_END digital output pins do not enter a 3-state mode. This condition, therefore, must be taken into account
when connecting multiple devices to the SPI port and for power-management considerations.
A F E RE GI STE R MA P
The AFE consists of a set of registers that can be used to configure it, such as receiver timings, I-V amplifier
settings, transmit LED currents, and so forth. The registers and their contents are listed in Table 4. These
registers can be accessed using the AFE SPI interface.
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A F E 4 4 9 0
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Ta bl e 4 . A F E Re g is te r Ma p
A DDRE SS RE GI STE R DA TA
NA ME
He x De c D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CONTROL0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
S
W
_
R
S
T
D
I
A
G
_
E
N
S
P
I
_
R
E
A
D
T
I
M
_
C
O
U
N
T
_
R
S
T
LED2STC 01 1 0 0 0 0 0 0 0 0 LED2STC[15:0]
LED2ENDC 02 2 0 0 0 0 0 0 0 0 LED2ENDC[15:0]
LED2LEDSTC 03 3 0 0 0 0 0 0 0 0 LED2LEDSTC[15:0]
LED2LEDENDC 04 4 0 0 0 0 0 0 0 0 LED2LEDENDC[15:0]
ALED2STC 05 5 0 0 0 0 0 0 0 0 ALED2STC[15:0]
ALED2ENDC 06 6 0 0 0 0 0 0 0 0 ALED2ENDC[15:0]
LED1STC 07 7 0 0 0 0 0 0 0 0 LED1STC[15:0]
LED1ENDC 08 8 0 0 0 0 0 0 0 0 LED1ENDC[15:0]
LED1LEDSTC 09 9 0 0 0 0 0 0 0 0 LED1LEDSTC[15:0]
LED1LEDENDC 0A 10 0 0 0 0 0 0 0 0 LED1LEDENDC[15:0]
ALED1STC 0B 11 0 0 0 0 0 0 0 0 ALED1STC[15:0]
ALED1ENDC 0C 12 0 0 0 0 0 0 0 0 ALED1ENDC[15:0]
LED2CONVST 0D 13 0 0 0 0 0 0 0 0 LED2CONVST[15:0]
LED2CONVST 0E 14 0 0 0 0 0 0 0 0 LED2CONVEND[15:0]
ALED2CONVST 0F 15 0 0 0 0 0 0 0 0 ALED2CONVST[15:0]
ALED2CONVEND 10 16 0 0 0 0 0 0 0 0 ALED2CONVEND[15:0]
LED1CONVST 11 17 0 0 0 0 0 0 0 0 LED1CONVST[15:0]
LED1CONVEND 12 18 0 0 0 0 0 0 0 0 LED1CONVEND[15:0]
ALED1CONVST 13 19 0 0 0 0 0 0 0 0 ALED1CONVST[15:0]
ALED1CONVEND 14 20 0 0 0 0 0 0 0 0 ALED1CONVEND[15:0]
ADCRSTCNT0 15 21 0 0 0 0 0 0 0 0 ADCRSTCT0[15:0]
ADCRSTENDCT0 16 22 0 0 0 0 0 0 0 0 ADCRENDCT0[15:0]
ADCRSTSTCT1 17 23 0 0 0 0 0 0 0 0 ADCRSTCT1[15:0]
ADCRSTENDCT1 18 24 0 0 0 0 0 0 0 0 ADCRENDCT1[15:0]
ADCRSTSTCT2 19 25 0 0 0 0 0 0 0 0 ADCRSTCT2[15:0]
ADCRSTENDCT2 1A 26 0 0 0 0 0 0 0 0 ADCRENDCT2[15:0]
ADCRSTSTCT3 1B 27 0 0 0 0 0 0 0 0 ADCRSTCT3[15:0]
ADCRSTENDCT3 1C 28 0 0 0 0 0 0 0 0 ADCRENDCT3[15:0]
PRPCOUNT 1D 29 0 0 0 0 0 0 0 0 PRPCT[15:0]
CONTROL1 1E 30 0 0 0 0 0 0 0 0 0 0 0 0 CLKALMPIN[2:0] NUMAV[7:0]
T
I
M
E
R
E
N
SPARE1 1F 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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Product Folder Links: AFE4490
A F E 4 4 9 0
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Ta bl e 4 . A F E Re g is te r Ma p (con tin u e d )
A DDRE SS RE GI STE R DA TA
NA ME
He x De c D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TIAGAIN 20 32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CF_LED1[4:0] RF_LED1[2:0]
E
N
S
E
P
G
A
N
TIA_AMB_GAIN 21 33 0 0 0 0 AMBDAC[3:0] 0 0 0 STG2GAIN[2:0] CF_LED2[4:0] RF_LED2[2:0]
S
T
A
G
E
2
E
N
F
L
T
R
C
N
R
S
E
L
LED
LEDCNTRL 22 34 0 0 0 0 0 0 LED1[7:0] LED2[7:0]
RANGE[1:0]
CONTROL2 23 35 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
P
D
N
T
X
P
D
N
R
X
P
D
N
A
F
E
X
T
A
L
D
I
S
T
X
_
R
E
F
1
T
X
_
R
E
F
0
T
X
B
R
G
M
O
D
E
N
_
A
D
C
_
B
Y
P
E
N
_
S
L
O
W
_
D
I
A
G
SPARE2 24 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPARE3 25 37 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SPARE4 26 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED1 27 39 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
RESERVED2 28 40 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ALARM 29 41 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
A
L
M
P
I
N
C
L
K
E
N
LED2VAL 2A 42 LED2VAL[23:0]
ALED2VAL 2B 43 ALED2VAL[23:0]
LED1VAL 2C 44 LED1VAL[23:0]
ALED1VAL 2D 45 ALED1VAL[23:0]
LED2-ALED2VAL 2E 46 LED2-ALED2VAL[23:0]
LED1-ALED1VAL 2F 47 LED1-ALED1VAL[23:0]
DIAG 30 48 0 0 0 0 0 0 0 0 0 0 0
P
D
O
C
P
D
S
C
L
E
D
S
C
P
D
_
A
L
M
L
E
D
_
A
L
M
I
N
P
S
C
L
E
D
I
N
N
S
C
L
E
D
I
N
P
S
C
G
N
D
I
N
N
S
C
G
N
D
L
E
D
1
O
P
E
N
L
E
D
2
O
P
E
N
O
U
T
P
S
H
G
N
D
O
U
T
N
S
H
G
N
D
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A F E RE GI STE R DE SCRI P TI O N
CO NTRO L0 : Con tr ol Re g is te r 0 (A d d r e s s = 0 0 h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 0 0 0 0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
TIM_
SPI_
0 0 0 0 0 0 0 0 SW_RST DIAG_EN COUNT_
READ
RST
This register is used for AFE software and count timer reset, diagnostics enable, and SPI read functions.
Bits D[23:4 ] Mu s t be '0 '
Bit D3 SW_RST: Sof twa r e r e s e t
0 = No action (default after reset)
1 = Software reset applied; resets all internal registers to the default values and self-clears
to '0'
Bit D2 DI A G_E N: Dia g n os tic e n a bl e
0 = No Action (default after reset)
1 = Diagnostic mode is enabled and the diagnostics sequence starts when this bit is set.
At the end of the sequence, all fault statuses are stored in the DIAG: Diagnostics Flag
Register. Afterwards, the DIAG_EN register bit self-clears to '0'.
Bit D1 TI M_CNT_RST: Time r cou n te r r e s e t
0 = Disables timer counter reset, required for normal timer operation (default after reset)
1 = Timer counters are in reset state
Bit D0 SP I RE A D: SP I r e a d
0 = SPI read is disabled (default after reset)
1 = SPI read is enabled
LE D2STC: Sa mpl e LE D2 Sta r t Cou n t Re g is te r (A d d r e s s = 0 1h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2STC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2STC[15:0]
This register sets the start timing value for the LED2 signal sample.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] LE D2STC[15:0 ]: Sa mpl e LE D2 s ta r t cou n t
The contents of this register can be used to position the start of the sample LED2 signal with
respect to the pulse repetition period (PRP), as specified in the PRPCOUNT register. The
count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer
Module section for details.
0 = 0000h
1 = PRP value
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LE D2E NDC: Sa mpl e LE D2 E n d Cou n t Re g is te r (A d d r e s s = 0 2h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2ENDC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2ENDC[15:0]
This register sets the end timing value for the LED2 signal sample.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] LE D2E NDC[15:0 ]: Sa mpl e LE D2 e n d cou n t
The contents of this register can be used to position the end of the sample LED2 signal with
respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the
number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
LE D2LE DSTC: LE D2 LE D Sta r t Cou n t Re g is te r (A d d r e s s = 0 3h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2LEDSTC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2LEDSTC[15:0]
This register sets the start timing value for when the LED2 signal turns on.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] LE D2LE DSTC[15:0 ]: LE D2 s ta r t cou n t
The contents of this register can be used to position the start of the LED2 with respect to the
PRP, as specified in the PRPCOUNT register. The count is specified as the number of 4-
MHz clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
LE D2LE DE NDC: LE D2 LE D E n d Cou n t Re g is te r (A d d r e s s = 0 4 h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2LEDENDC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2LEDENDC[15:0]
This register sets the end timing value for when the LED2 signal turns off.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] LE D2LE DE NDC[15:0 ]: LE D2 e n d cou n t
The contents of this register can be used to position the end of the LED2 signal with respect
to the PRP, as specified in the PRPCOUNT register. The count is specified as the number
of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
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A LE D2STC: Sa mpl e A mbie n t LE D2 Sta r t Cou n t Re g is te r (A d d r e s s = 0 5h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED2STC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED2STC[15:0]
This register sets the start timing value for the ambient LED2 signal sample.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A LE D2STC[15:0 ]: Sa mpl e a mbie n t LE D2 s ta r t cou n t
The contents of this register can be used to position the start of the sample ambient LED2
signal with respect to the PRP, as specified in the PRPCOUNT register. The count is
specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section
for details.
0 = 0000h
1 = PRP value
A LE D2E NDC: Sa mpl e A mbie n t LE D2 E n d Cou n t Re g is te r (A d d r e s s = 0 6h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED2ENDC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED2ENDC[15:0]
This register sets the end timing value for the ambient LED2 signal sample.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A LE D2E NDC[15:0 ]: Sa mpl e a mbie n t LE D2 e n d cou n t
The contents of this register can be used to position the end of the sample ambient LED2
signal with respect to the PRP, as specified in the PRPCOUNT register. The count is
specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section
for details.
0 = 0000h
1 = PRP value
LE D1STC: Sa mpl e LE D1 Sta r t Cou n t Re g is te r (A d d r e s s = 0 7h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1STC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1STC[15:0]
This register sets the start timing value for the LED1 signal sample.
Bits D[23:17] Mu s t be '0 '
Bits D[16:0 ] LE D1STC[15:0 ]: Sa mpl e LE D1 s ta r t cou n t
The contents of this register can be used to position the start of the sample LED1 signal with
respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the
number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
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LE D1E NDC: Sa mpl e LE D1 E n d Cou n t (A d d r e s s = 0 8h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1ENDC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1ENDC[15:0]
This register sets the end timing value for the LED1 signal sample.
Bits D[23:17] Mu s t be '0 '
Bits D[16:0 ] LE D1E NDC[15:0 ]: Sa mpl e LE D1 e n d cou n t
The contents of this register can be used to position the end of the sample LED1 signal with
respect to the PRP, as specified in the PRPCOUNT register. The count is specified as the
number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
LE D1LE DSTC: LE D1 LE D Sta r t Cou n t Re g is te r (A d d r e s s = 0 9 h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1LEDSTC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1LEDSTC[15:0]
This register sets the start timing value for when the LED1 signal turns on.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] LE D1LE DSTC[15:0 ]: LE D1 s ta r t cou n t
The contents of this register can be used to position the start of the LED1 signal with respect
to the PRP, as specified in the PRPCOUNT register. The count is specified as the number
of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
LE D1LE DE NDC: LE D1 LE D E n d Cou n t Re g is te r (A d d r e s s = 0 A h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1LEDENDC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1LEDENDC[15:0]
This register sets the end timing value for when the LED1 signal turns off.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] LE D1LE DE NDC[15:0 ]: LE D1 e n d cou n t
The contents of this register can be used to position the end of the LED1 signal with respect
to the PRP, as specified in the PRPCOUNT register. The count is specified as the number
of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
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A LE D1STC: Sa mpl e A mbie n t LE D1 Sta r t Cou n t Re g is te r (A d d r e s s = 0 Bh, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED1STC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED1STC[15:0]
This register sets the start timing value for the ambient LED1 signal sample.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A LE D1STC[15:0 ]: Sa mpl e a mbie n t LE D1 s ta r t cou n t
The contents of this register can be used to position the start of the sample ambient LED1
signal with respect to the PRP, as specified in the PRPCOUNT register. The count is
specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section
for details.
0 = 0000h
1 = PRP value
A LE D1E NDC: Sa mpl e A mbie n t LE D1 E n d Cou n t Re g is te r (A d d r e s s = 0 Ch, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED1ENDC[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED1ENDC[15:0]
This register sets the end timing value for the ambient LED1 signal sample.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A LE D1E NDC[15:0 ]: Sa mpl e a mbie n t LE D1 e n d cou n t
The contents of this register can be used to position the end of the sample ambient LED1
signal with respect to the PRP, as specified in the PRPCOUNT register. The count is
specified as the number of 4-MHz clock cycles. Refer to the Using the Timer Module section
for details.
0 = 0000h
1 = PRP value
LE D2CO NVST: LE D2 Con ve r t Sta r t Cou n t Re g is te r (A d d r e s s = 0 Dh, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2CONVST[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2CONVST[15:0]
This register sets the start timing value for the LED2 conversion.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] LE D2CO NVST[15:0 ]: LE D2 con ve r t s ta r t cou n t
The contents of this register can be used to position the start of the LED2 conversion signal
with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as
the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
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LE D2CO NVST: LE D2 Con ve r t E n d Cou n t Re g is te r (A d d r e s s = 0 E h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED2CONVST[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2CONVST[15:0]
This register sets the end timing value for the LED2 conversion.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] LE D2CO NVST[15:0 ]: LE D2 con ve r t e n d cou n t
The contents of this register can be used to position the end of the LED2 conversion signal
with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as
the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
A LE D2CO NVST: LE D2 A mbie n t Con ve r t Sta r t Cou n t Re g is te r (A d d r e s s = 0 F h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED2CONVST[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED2CONVST[15:0]
This register sets the start timing value for the ambient LED2 conversion.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A LE D2CO NVST[15:0 ]: LE D2 a mbie n t con ve r t s ta r t cou n t
The contents of this register can be used to position the start of the LED2 ambient
conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The
count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer
Module section for details.
0 = 0000h
1 = PRP value
A LE D2CO NVE ND: LE D2 A mbie n t Con ve r t E n d Cou n t Re g is te r (A d d r e s s = 10 h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED2CONVEND[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED2CONVEND[15:0]
This register sets the end timing value for the ambient LED2 conversion.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A LE D2CO NVE ND[15:0 ]: LE D2 a mbie n t con ve r t e n d cou n t
The contents of this register can be used to position the end of the LED2 ambient
conversion signal with respect to the PRP. The count is specified as the number of 4-MHz
clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
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LE D1CO NVST: LE D1 Con ve r t Sta r t Cou n t Re g is te r (A d d r e s s = 11h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1CONVST[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1CONVST[15:0]
This register sets the start timing value for the LED1 conversion.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] LE D1CO NVST[15:0 ]: LE D1 con ve r t s ta r t cou n t
The contents of this register can be used to position the start of the LED1 conversion signal
with respect to the PRP, as specified in the PRPCOUNT register. The count is specified as
the number of 4-MHz clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
LE D1CO NVE ND: LE D1 Con ve r t E n d Cou n t Re g is te r (A d d r e s s = 12h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 LED1CONVEND[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1CONVEND[15:0]
This register sets the end timing value for the LED1 conversion.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] LE D1CO NVE ND[15:0 ]: LE D1 con ve r t e n d cou n t
The contents of this register can be used to position the end of the LED1 conversion signal
with respect to the PRP. The count is specified as the number of 4-MHz clock cycles. Refer
to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
A LE D1CO NVST: LE D1 A mbie n t Con ve r t Sta r t Cou n t Re g is te r (A d d r e s s = 13h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED1CONVST[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED1CONVST[15:0]
This register sets the start timing value for the ambient LED1 conversion.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A LE D1CO NVST[15:0 ]: LE D1 a mbie n t con ve r t s ta r t cou n t
The contents of this register can be used to position the start of the LED1 ambient
conversion signal with respect to the PRP, as specified in the PRPCOUNT register. The
count is specified as the number of 4-MHz clock cycles. Refer to the Using the Timer
Module section for details.
0 = 0000h
1 = PRP value
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A LE D1CO NVE ND: LE D1 A mbie n t Con ve r t E n d Cou n t Re g is te r (A d d r e s s = 14 h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ALED1CONVEND[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED1CONVEND[15:0]
This register sets the end timing value for the ambient LED1 conversion.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A LE D1CO NVE ND[15:0 ]: LE D1 a mbie n t con ve r t e n d cou n t
The contents of this register can be used to position the end of the LED1 ambient
conversion signal with respect to the PRP. The count is specified as the number of 4-MHz
clock cycles. Refer to the Using the Timer Module section for details.
0 = 0000h
1 = PRP value
A DCRSTCNT0 : A DC Re s e t 0 Sta r t Cou n t Re g is te r (A d d r e s s = 15h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTCNT0[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTCNT0[15:0]
This register sets the start position of the ADC0 reset conversion signal.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A DCRSTCNT0 [15:0 ]: A DC RE SE T 0 s ta r t cou n t
The contents of this register can be used to position the start of the ADC reset conversion
signal (default value after reset is 0000h). Refer to the Using the Timer Module section for
details.
A DCRSTE NDCT0 : A DC Re s e t 0 E n d Cou n t Re g is te r (A d d r e s s = 16h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTENDCT0[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTENDCT0[15:0]
This register sets the end position of the ADC0 reset conversion signal.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A DCRSTE NDCT0 [15:0 ]: A DC RE SE T 0 e n d cou n t
The contents of this register can be used to position the end of the ADC reset conversion
signal (default value after reset is 0000h). Refer to the Using the Timer Module section for
details.
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A DCRSTSTCT1: A DC Re s e t 1 Sta r t Cou n t Re g is te r (A d d r e s s = 17h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTSTCT1[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTSTCT1[15:0]
This register sets the start position of the ADC1 reset conversion signal.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A DCRSTSTCT1[15:0 ]: A DC RE SE T 1 s ta r t cou n t
The contents of this register can be used to position the start of the ADC reset conversion.
Refer to the Using the Timer Module section for details.
A DCRSTE NDCT1: A DC Re s e t 1 E n d Cou n t Re g is te r (A d d r e s s = 18h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTENDCT1[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTENDCT1[15:0]
This register sets the end position of the ADC1 reset conversion signal.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A DCRSTE NDCT1[15:0 ]: A DC RE SE T 1 e n d cou n t
The contents of this register can be used to position the end of the ADC reset conversion.
Refer to the Using the Timer Module section for details.
A DCRSTSTCT2: A DC Re s e t 2 Sta r t Cou n t Re g is te r (A d d r e s s = 19 h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTSTCT2[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTSTCT2[15:0]
This register sets the start position of the ADC2 reset conversion signal.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A DCRSTSTCT2[15:0 ]: A DC RE SE T 2 s ta r t cou n t
The contents of this register can be used to position the start of the ADC reset conversion.
Refer to the Using the Timer Module section for details.
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A DCRSTE NDCT2: A DC Re s e t 2 E n d Cou n t Re g is te r (A d d r e s s = 1A h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTENDCT2[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTENDCT2[15:0]
This register sets the end position of the ADC2 reset conversion signal.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A DCRSTE NDCT2[15:0 ]: A DC RE SE T 2 e n d cou n t
The contents of this register can be used to position the end of the ADC reset conversion.
Refer to the Using the Timer Module section for details.
A DCRSTSTCT3: A DC Re s e t 3 Sta r t Cou n t Re g is te r (A d d r e s s = 1Bh, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTSTCT3[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTSTCT3[15:0]
This register sets the start position of the ADC3 reset conversion signal.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A DCRSTSTCT3[15:0 ]: A DC RE SE T 3 s ta r t cou n t
The contents of this register can be used to position the start of the ADC reset conversion.
Refer to the Using the Timer Module section for details.
A DCRSTE NDCT3: A DC Re s e t 3 E n d Cou n t Re g is te r (A d d r e s s = 1Ch, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 ADCRSTENDCT3[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ADCRSTENDCT3[15:0]
This register sets the end position of the ADC3 reset conversion signal.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] A DCRSTE NDCT3[15:0 ]: A DC RE SE T 3 e n d cou n t
The contents of this register can be used to position the end of the ADC reset conversion
signal (default value after reset is 0000h). Refer to the Using the Timer Module section for
details.
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P RP CO UNT: P u l s e Re pe tition P e r iod Cou n t Re g is te r (A d d r e s s = 1Dh, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 PRPCOUNT[15:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PRPCOUNT[15:0]
This register sets the device pulse repetition period count.
Bits D[23:16] Mu s t be '0 '
Bits D[15:0 ] P RP CO UNT[15:0 ]: P u l s e r e pe tition pe r iod cou n t
The contents of this register can be used to set the pulse repetition period (in number of
clock cycles of the 4-MHz clock).
CO NTRO L1: Con tr ol Re g is te r 1 (A d d r e s s = 1E h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 0 0 0 0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CLKALMPIN[2:0] TIMEREN NUMAV[7:0]
This register configures the clock alarm pin, timer, and number of averages.
Bits D[23:12] Mu s t be '0 '
Bits D[11:9 ] CLKA LMP I N[2:0 ]: Cl ocks on A LM pin s
Internal clocks can be brought to the PD_ALM and LED_ALM pins for monitoring.
Note that the CLKALMPIN[2:0] register bits must be set before using this register bit.
Table 5 defines the settings for the two alarm pins.
Bit D8 TI ME RE N: Time r e n a bl e
0 = Timer module is disabled and all internal clocks are off (default after reset)
1 = Timer module is enabled
Bits D[7:0 ] NUMA V[7:0 ]: Nu mbe r of a ve r a g e s
Specify an 8-bit value corresponding to the number of ADC samples to be averaged 1.
For example, to average four ADC samples, set NUMAV[7:0] equal to 3.
Ta bl e 5. P D_A LM a n d LE D_A LM P in Se ttin g s
CLKA LMP I N[2:0 ] P D_A LM P I N SI GNA L LE D_A LM P I N SI GNA L
000 Sample LED2 Sample LED1
001 LED2 pulse LED1 pulse
010 Sample LED2 Sample LED1 pulse
011 LED2 convert LED1 convert
100 LED2 ambient LED1 ambient
101 No output No output
110 No output No output
111 No output No output
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SP A RE 1: SP A RE 1 Re g is te r F or F u tu r e Us e (A d d r e s s = 1F h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 0 0 0 0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 0 0
This register is a spare register and is reserved for future use.
Bits D[23:0 ] Mu s t be '0 '
TI A GA I N: Tr a n s impe d a n ce A mpl if ie r Ga in Se ttin g Re g is te r (A d d r e s s = 20 h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
ENSEP
0 0 0 0 0 0 0 0 0 0 0
GAIN
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 CF_LED1[4:0] RF_LED1[2:0]
This register sets the device transimpedance amplifier gain mode and feedback resistor and capacitor values.
Bits D[23:16] Mu s t be '0 '
Bit D15 E NSE P GA I N: E n a bl e s e pa r a te g a in mod e
0 = The R
F
and C
F
values are the same for both LED2 and LED1 signals; the value specified
by the RF_LED2[2:0] register bits is used (default after reset)
1 = The R
F
value is different for the LED2 and LED1 signals; the values are specified by the
RF_LED1[2:0] and RF_LED2[2:0] register bits
Bits D[14 :8] Mu s t be '0 '
Bits D[7:3] CF _LE D1[4 :0 ]: P r og r a m C
F
f or LE D1
00000 = 5 pF (default after reset) 00100 = 25 pF + 5 pF
00001 = 5 pF + 5 pF 01000 = 50 pF + 5 pF
00010 = 15 pF + 5 pF 10000 = 150 pF + 5 pF
Note that any combination of these C
F
settings is also supported by setting multiple bits to
'1'. For example, to obtain C
F
= 100 pF, set D[7:3] = 01111.
Bits D[2:0 ] RF _LE D1[2:0 ]: P r og r a m R
F
f or LE D1
000 = 500 k (default after reset) 100 = 25 k
001 = 250 k 101 = 10 k
010 = 100 k 110 = 1 M
011 = 50 k 111 = None
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TI A _A MB_GA I N: Tr a n s impe d a n ce A mpl if ie r a n d A mbie n t Ca n ce l l a tion Sta g e Ga in Re g is te r
(A d d r e s s = 21h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
FLTR STAGE2
0 0 0 0 AMBDAC[3:0] 0 0
CNRSEL EN
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 STG2GAIN[2:0] CF_LED2[4:0] RF_LED2[2:0]
This register configures the ambient light cancellation amplifier gain, cancellation current, and filter corner
frequency.
Bits D[23:20 ] Mu s t be '0 '
Bits D[19 :16] A MBDA C[3:0 ]: A mbie n t DA C va l u e
These bits set the value of the cancellation current.
0000 = 0 A (default after reset) 1000 = 8 A
0001 = 1 A 1001 = 9 A
0010 = 2 A 1010 = 10 A
0011 = 3 A 1011 = Do not use
0100 = 4 A 1100 = Do not use
0101 = 5 A 1101 = Do not use
0110 = 6 A 1110 = Do not use
0111 = 7 A 1111 = Do not use
Bit D15 F LTRCNRSE L: F il te r cor n e r s e l e ction
0 = 500-Hz filter corner (default after reset)
1 = 1000-Hz filter corner
Bit D14 STA GE 2E N: Sta g e 2 e n a bl e
0 = Stage 2 is bypassed (default after reset)
1 = Stage 2 is enabled with the gain value specified by the STG2GAIN[2:0] bits
Bits D[13:11] Mu s t be '0 '
Bits D[10 :8] STG2GA I N[2:0 ]: Sta g e 2 g a in s e ttin g
000 = 0 dB, or linear gain of 1 (default after 100 = 12 dB, or linear gain of 4
reset) 101 = Do not use
001 = 3 dB, or linear gain of 1.414 110 = Do not use
010 = 6 dB, or linear gain of 2 111 = Do not use
011 = 9 dB, or linear gain of 2.818
Bits D[7:3] CF _LE D2[4 :0 ]: P r og r a m C
F
f or LE D2
00000 = 5 pF (default after reset) 00100 = 25 pF + 5 pF
00001 = 5 pF + 5 pF 01000 = 50 pF + 5 pF
00010 = 15 pF + 5 pF 10000 = 150 pF + 5 pF
Note that any combination of these C
F
settings is also supported by setting multiple bits to
'1'. For example, to obtain C
F
= 100 pF, set D[7:3] = 01111.
Bits D[2:0 ] RF _LE D2[2:0 ]: P r og r a m R
F
f or LE D2
000 = 500 k 100 = 25 k
001 = 250 k 101 = 10 k
010 = 100 k 110 = 1 M
011 = 50 k 111 = None
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Full-Scale Current
LED2[7:0]
256
Full-Scale Current
LED1[7:0]
256
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LE DCNTRL: LE D Con tr ol Re g is te r (A d d r e s s = 22h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 LED_RANGE[1:0] LED1[7:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1[7:0] LED2[7:0]
This register sets the LED current range and the LED1 and LED2 drive current.
Bits D[23:18] Mu s t be '0 '
Bits D[17:16] LE D_RA NGE [1:0 ]: LE D r a n g e
These bits program the full-scale LED current range for Tx. Table 6 details the settings.
Bits D[15:8] LE D1[7:0 ]: P r og r a m LE D cu r r e n t f or LE D1 s ig n a l
Use these register bits to specify the LED current setting for LED1 (default after reset is
00h).
The nominal value of the LED current is given by Equation 4,
where the full-scale LED current is either 0 mA, 50 mA, 75 mA, 100 mA, 150 mA, or 200 mA
(as specified by the LED_RANGE[1:0] register bits).
Bits D[7:0 ] LE D2[7:0 ]: P r og r a m LE D cu r r e n t f or LE D2 s ig n a l
Use these register bits to specify the LED current setting for LED2 (default after reset is
00h).
The nominal value of LED current is given by Equation 5,
where the full-scale LED current is either 0 mA, 50 mA, 75 mA, 100 mA, 150 mA, or 200 mA
(as specified by the LED_RANGE[1:0] register bits).
Ta bl e 6. F u l l - Sca l e LE D Cu r r e n t a cr os s Tx Re f e r e n ce Vol ta g e Se ttin g s
LE D CURRE NT RA NGE F O R Tx RE F E RE NCE VO LTA GE
LE D_RA NGE [1:0 ]
0 .75 V (TX_RE F [1:0 ] = 0 0 ) 0 .5 V (TX_RE F [1:0 ] = 0 1) 1.0 V (TX_RE F [1:0 ] = 10 )
00 (default after reset) 150 mA 100 mA 200 mA
01 75 mA 50 mA 100 mA
10 150 mA 100 mA 200 mA
11 Tx is off Tx is off Tx is off
(4)
(5)
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CO NTRO L2: Con tr ol Re g is te r 2 (A d d r e s s = 23h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
TX_SUP_ EN_ADC
0 0 0 0 0 0 0 0 0 0
3V _BYP
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EN_
TXBRG XTAL
0 SLOW_ 0 0 0 0 0 PDNTX PDNRX PDNAFE
MOD DIS
DIAG
This register controls the LED transmitter, crystal, and the AFE, transmitter, and receiver power modes.
Bits D[23:19 ] Mu s t be '0 '
Bits D[18:17] TX_RE F [1:0 ]: Tx r e f e r e n ce vol ta g e
These bits set the transmitter reference voltage. This Tx reference voltage is available on
the device TX_REF pin.
00 = 0.75-V Tx reference voltage (default value after reset)
01 = 0.5-V Tx reference voltage
10 = 1.0-V Tx reference voltage
11 = 0.75-V Tx reference voltage
Bit D16 Mu s t be '0 '
Bit D15 E N_A DC_BYP : A DC bypa s s mod e e n a bl e
0 = Normal mode, the internal ADC is active (default after reset)
1 = ADC bypass mode, the analog signal is output to the ADC_BYPP and ADC_BYPN pins
Bits D[14 :12] Mu s t be '0 '
Bit D11 TXBRGMO D: Tx br id g e mod e
0 = LED driver is configured as an H-bridge (default after reset)
1 = LED driver is configured as a push-pull
Bit D10 Mu s t be '0 '
Bit D9 XTA LDI S: Cr ys ta l d is a bl e mod e
0 = The crystal module is enabled; the 8-MHz crystal must be connected to the XIN and
XOUT pins
1 = The crystal module is disabled; an external 8-MHz clock must be applied to the XIN pin
Bit D8 E N_SLO W_DI A G: F a s t d ia g n os tics mod e e n a bl e
0 = Fast diagnostics mode, 8 ms (default value after reset)
1 = Slow diagnostics mode, 16 ms
Bits D[7:3] Mu s t be '0 '
Bit D2 P DN_TX: Tx powe r - d own
0 = The Tx is powered up (default after reset)
1 = Only the Tx module is powered down
Bit D1 P DN_RX: Rx powe r - d own
0 = The Rx is powered up (default after reset)
1 = Only the Rx module is powered down
Bit D0 P DN_A F E : A F E powe r - d own
0 = The AFE is powered up (default after reset)
1 = The entire AFE is powered down (including the Tx, Rx, and diagnostics blocks)
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SP A RE 2: SP A RE 2 Re g is te r F or F u tu r e Us e (A d d r e s s = 24 h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 0 0 0 0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 0 0
This register is a spare register and is reserved for future use.
Bits D[23:0 ] Mu s t be '0 '
SP A RE 3: SP A RE 3 Re g is te r F or F u tu r e Us e (A d d r e s s = 25h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 0 0 0 0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 0 0
This register is a spare register and is reserved for future use.
Bits D[23:0 ] Mu s t be '0 '
SP A RE 4 : SP A RE 4 Re g is te r F or F u tu r e Us e (A d d r e s s = 26h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 0 0 0 0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 0 0
This register is a spare register and is reserved for future use.
Bits D[23:0 ] Mu s t be '0 '
RE SE RVE D1: RE SE RVE D1 Re g is te r F or F a ctor y Us e O n l y (A d d r e s s = 27h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 0 0 0 0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 0 0
This register is reserved for factory use. Readback values vary between devices.
Bits D[23:0 ] Mu s t be '0 '
RE SE RVE D2: RE SE RVE D2 Re g is te r F or F a ctor y Us e O n l y (A d d r e s s = 28h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 0 0 0 0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 0 0
This register is reserved for factory use. Readback values vary between devices.
Bits D[23:0 ] Mu s t be '0 '
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A LA RM: A l a r m Re g is te r (A d d r e s s = 29 h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 0 0 0 0
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALMPIN
0 0 0 0 0 0 0 0 0 0 0
CLKEN
This register controls the Alarm pin functionality.
Bits D[23:8] Mu s t be '0 '
Bit D7 A LMP I NCLKE N: A l a r m pin cl ock e n a bl e
0 = Disables the monitoring of internal clocks; the PD_ALM and LED_ALM pins function as
diagnostic fault alarm output pins (default after reset)
1 = Enables the monitoring of internal clocks; these clocks can be brought out on PD_ALM
and LED_ALM selectively (depending on the value of the CLKALMPIN[2:0] register bits).
Bits D[6:0 ] Mu s t be '0 '
LE D2VA L: LE D2 Dig ita l Sa mpl e Va l u e Re g is te r (A d d r e s s = 2A h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
LED2VAL[23:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2VAL[23:0]
This register contains the digital value of the latest LED2 sample converted by the ADC. The ADC_RDY signal
goes high each time that the contents of this register are updated. The host processor must readout this register
before the next sample is converted by the AFE.
Bits D[23:0 ] LE D2VA L[23:0 ]: LE D2 d ig ita l va l u e
This register contains the digital value of the latest LED2 sample converted by the ADC. The
ADC_RDY signal goes high each time that the contents of this register are updated. The
host processor must readout this register before the next sample is converted by the AFE.
A LE D2VA L: A mbie n t LE D2 Dig ita l Sa mpl e Va l u e Re g is te r (A d d r e s s = 2Bh, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
ALED2VAL[23:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED2VAL[23:0]
This register contains the digital value of the latest LED2 ambient sample converted by the ADC. The ADC_RDY
signal goes high each time that the contents of this register are updated. The host processor must readout this
register before the next sample is converted by the AFE.
Bits D[23:0 ] A LE D2VA L[23:0 ]: LE D2 a mbie n t d ig ita l va l u e
This register contains the digital value of the latest LED2 ambient sample converted by the
ADC. The ADC_RDY signal goes high each time that the contents of this register are
updated. The host processor must readout this register before the next sample is converted
by the AFE.
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LE D1VA L: LE D1 Dig ita l Sa mpl e Va l u e Re g is te r (A d d r e s s = 2Ch, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
LED1VAL[23:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1VAL[23:0]
This register contains the digital value of the latest LED1 sample converted by the ADC. The ADC_RDY signal
goes high each time that the contents of this register are updated. The host processor must readout this register
before the next sample is converted by the AFE.
Bits D[23:0 ] LE D1VA L[23:0 ]: LE D1 d ig ita l va l u e
This register contains the digital value of the latest LED1 sample converted by the ADC. The
ADC_RDY signal goes high each time that the contents of this register are updated. The
host processor must readout this register before the next sample is converted by the AFE.
A LE D1VA L: A mbie n t LE D1 Dig ita l Sa mpl e Va l u e Re g is te r (A d d r e s s = 2Dh, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
ALED1VAL[23:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
ALED1VAL[23:0]
This register contains the digital value of the latest LED1 ambient sample converted by the ADC. The ADC_RDY
signal goes high each time that the contents of this register are updated. The host processor must readout this
register before the next sample is converted by the AFE.
Bits D[23:0 ] A LE D1VA L[23:0 ]: LE D1 a mbie n t d ig ita l va l u e
This register contains the digital value of the latest LED1 ambient sample converted by the
ADC. The ADC_RDY signal goes high each time that the contents of this register are
updated. The host processor must readout this register before the next sample is converted
by the AFE.
LE D2- A LE D2VA L: LE D2- A mbie n t LE D2 Dig ita l Sa mpl e Va l u e Re g is te r
(A d d r e s s = 2E h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
LED2-ALED2VAL[23:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED2-ALED2VAL[23:0]
This register contains the digital value of the LED2 sample after the LED2 ambient is subtracted. The host
processor must readout this register before the next sample is converted by the AFE.
Bits D[23:0 ] LE D2- A LE D2VA L[23:0 ]: (LE D2 LE D2 a mbie n t) d ig ita l va l u e
This register contains the digital value of the LED2 sample after the LED2 ambient is
subtracted. The host processor must readout this register before the next sample is
converted by the AFE.
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LE D1- A LE D1VA L: LE D1- A mbie n t LE D1 Dig ita l Sa mpl e Va l u e Re g is te r
(A d d r e s s = 2F h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
LED1-ALED1VAL[23:0]
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED1-ALED1VAL[23:0]
This register contains the digital value of the LED1 sample after the LED1 ambient is subtracted. The host
processor must readout this register before the next sample is converted by the AFE.
Bits D[23:0 ] LE D1- A LE D1VA L[23:0 ]: (LE D1 LE D1 a mbie n t) d ig ita l va l u e
This register contains the digital value of the LED1 sample after the LED1 ambient is
subtracted from it. The host processor must readout this register before the next sample is
converted by the AFE.
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DI A G: Dia g n os tics F l a g Re g is te r (A d d r e s s = 30 h, Re s e t Va l u e = 0 0 0 0 h)
D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12
0 0 0 0 0 0 0 0 0 0 0 PD_ALM
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
LED_ LED1 LED2 OUTPSH OUTNSH INNSC INPSC INNSC INPSC
LEDSC PDOC PDSC
ALM OPEN OPEN GND GND GND GND LED LED
This register is read only. This register contains the status of all diagnostic flags at the end of the diagnostics
sequence. The end of the diagnostics sequence is indicated by the signal going high on DIAG_END pin.
Bits D[23:13] Re a d on l y
Bit D12 P D_A LM: P owe r - d own a l a r m s ta tu s d ia g n os tic f l a g
This bit indicates the status of PD_ALM (and the PD_ALM pin).
0 = No fault (default after reset)
1 = Fault present
Bit D11 LE D_A LM: LE D a l a r m s ta tu s d ia g n os tic f l a g
This bit indicates the status of LED_ALM (and the LED_ALM pin).
0 = No fault (default after reset)
1 = Fault present
Bit D10 LE D1O P E N: LE D1 ope n d ia g n os tic f l a g
This bit indicates that LED1 is open.
0 = No fault (default after reset)
1 = Fault present
Bit D9 LE D2O P E N: LE D2 ope n d ia g n os tic f l a g
This bit indicates that LED2 is open.
0 = No fault (default after reset)
1 = Fault present
Bit D8 LE DSC: LE D s hor t d ia g n os tic f l a g
This bit indicates an LED short.
0 = No fault (default after reset)
1 = Fault present
Bit D7 O UTP SHGND: O UTP to GND d ia g n os tic f l a g
This bit indicates that OUTP is shorted to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit D6 O UTNSHGND: O UTN to GND d ia g n os tic f l a g
This bit indicates that OUTN is shorted to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit D5 P DO C: P D ope n d ia g n os tic f l a g
This bit indicates that PD is open.
0 = No fault (default after reset)
1 = Fault present
Bit D4 P DSC: P D s hor t d ia g n os tic f l a g
This bit indicates a PD short.
0 = No fault (default after reset)
1 = Fault present
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Bit D3 I NNSCGND: I NN to GND d ia g n os tic f l a g
This bit indicates a short from the INN pin to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit D2 I NP SCGND: I NP to GND d ia g n os tic f l a g
This bit indicates a short from the INP pin to the GND cable.
0 = No fault (default after reset)
1 = Fault present
Bit D1 I NNSCLE D: I NN to LE D d ia g n os tic f l a g
This bit indicates a short from the INN pin to the LED cable.
0 = No fault (default after reset)
1 = Fault present
Bit D0 I NP SCLE D: I NP to LE D d ia g n os tic f l a g
This bit indicates a short from the INP pin to the LED cable.
0 = No fault (default after reset)
1 = Fault present
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PACKAGE OPTION ADDENDUM
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Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (C) Top-Side Markings
(4)
Samples
AFE4490RHAR ACTIVE VQFN RHA 40 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR 0 to 70
AFE4490RHAT ACTIVE VQFN RHA 40 250 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR 0 to 70

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Only one of markings shown within the brackets will appear on the physical device.

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