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Ethernet Over SONET/SDH tutorial

1
Day In the Life of an
Ethernet Over SONET/SDH Packet

 Goal is to understand how Ethernet, SONET and Virtual


Concatenation work together
 Ethernet Frame Processing
 Ethernet Encapsulation – GFP-F or LAPS
 Virtual Concatenation processing
 SONET/SDH framing

 Follow Ethernet Frame through each process step


Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper
SPI-4.2

SPI-4.2

FIFO Processor SDH


GMII

MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Framer

Copyright©2004 Vitesse Semiconductor Corporation 2


Ethernet MAC Receives a Packet
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
Inter VCAT Mapper
Packet
Gap
 Ethernet Frames Extracted From
Preamble
the Line Interface
SFD
 8B/10B Decoding For SerDes Interfaces
 Inter Packet Gap, Preamble and Start of
Ethernet Ethernet
Packet Packet
Frame Delimiter are Stripped

 At Completion of Packet
Ethernet Ethernet
FCS FCS Reception, Error Conditions are
Inter Checked and Statistics Updated
Packet
Gap  Packet Length Check
 FCS Check
Incoming Ethernet Extracted Ethernet
Packet Stream Packet  Packet and Byte Counters Updated
Copyright©2004 Vitesse Semiconductor Corporation 3
Ingress FIFO Buffers Packet
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

 Packet Buffered as it is Received Into the


Ingress FIFO
Previous
Packet  Errored Packets are Deleted from the
FIFO
Ethernet Ethernet  Store and Forward Mode Deletes the Packet
Packet Packet Entirely
 Cut Through Mode Deletes Any Remaining
Ethernet Ethernet Data
FCS FCS

Extracted Ethernet Packet Added to


Packet Ingress FIFO

Copyright©2004 Vitesse Semiconductor Corporation 4


Packet Sent Across SPI-4.2 Interface
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

Ctrl Word  Packets Sent Across SPI-4.2 Interface by


Begin
Previous
Ethernet
MAC
Packet
Packet
Ctrl Word
 SPI-4.2 Control Words Identify Data
Ethernet Another Transferred
Packet Channel’s
Ethernet  Port Address
Data
 Start of Packet, End of Packet, Aborted Packet
Ethernet Ctrl Word
FCS Remainder  Bursts are Scheduled between Ports on a
Of Ethernet
Next Packet Round Robin Basis
Packet With FCS
Ctrl Word

Packet in the Burst Interleaved


Ingress FIFO Across SPI-4.2
Copyright©2004 Vitesse Semiconductor Corporation 5
Packet Reassembled and Buffered
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

Ctrl Word
Begin
Previous
Ethernet
Packet
Packet
Ctrl Word  Packet Bursts Reassembled into Packets
Another Ethernet in the Tx Buffer
Channel’s Packet
Ethernet
Data
Ctrl Word Ethernet
Remainder FCS
Of Ethernet
Packet
With FCS
Ctrl Word

Burst Interleaved Packet in Tx


Across SPI-4.2 Buffer
Copyright©2004 Vitesse Semiconductor Corporation 6
Packet Encapsulation –
Generic Framing Protocol (GFP)
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

PLI 2 Bytes
cHEC
 Generic Framing Procedure (GFP) is One of Two
2 Bytes
Type Ethernet Encapsulation Choices
2 Bytes
tHEC 2 Bytes  PDU Length Indicator (PLI) Along with the Core
Extension
Header 2 Bytes Header Error Check (cHEC) form the Core Header
eHEC 2 Bytes  PLI is the number of Bytes in the Entire Encapsulated Packet
Excluding the Core Header Itself

Ethernet Ethernet
 Type Field describes encapsulated packet
Packet Packet  Control or Data Packet
 FCS Present Indicator
 Extension Header Indicator
Ethernet Ethernet
FCS FCS  Extension Header is Optionally Inserted
GFP FCS 4 Bytes
 GFP FCS
Incoming Resulting GFP  Optionally Inserted CRC
Ethernet Encapsulated
Packet Packet
Copyright©2004 Vitesse Semiconductor Corporation 7
Packet Encapsulation –
Link Access Procedure - SDH (LAPS)
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

 Link Access Procedure –SDH (LAPS) is


Flag 1 Byte
Address
One of Two Ethernet Encapsulation
1 Byte
Control 1 Byte
Choices
SAPI 2 Bytes  X.85 Defines IP over LAPS
 X.86 Defines Ethernet over LAPS
Ethernet Ethernet  One of Several HDLC Protocols
Packet Packet – Similar to Packet Over SONET (POS)

 Typical Field Values:


Ethernet Ethernet
FCS FCS  Flag – 0x7E
LAPS
FCS 4 Bytes  Address – 0x04
Incoming Resulting LAPS  Control – 0x03 (Unnumbered Information)
Ethernet Encapsulated  Service Access Point Identifier (SAPI) –
Packet Packet
0xFE01
Copyright©2004 Vitesse Semiconductor Corporation 8
Virtual Concatenation Mapping
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

 Each Port is Mapped to a VC Group


Byte 1
Byte 2
 Group Descriptor Table Denotes the Type of
Byte 3 STS-1 #5 Group and Number of Members
Byte 4
H4 STS-1 #12  Example: 3 Virtually Concatenated STS-1s (#5, 12,
H4 STS-1 #32 and 32)

H4  Data Fetched and Placed in the Channel


Buffer
Byte N
 Amount of Data Fetched Depends on the Size of the
Concatenated Channel
Bytes Interleaved  Bytes Interleaved Across the Members of the Channel
Encapsulated
Across Multiple
Packet
STS-1s
 H4 Bytes Generated and Passed to the Path
Overhead Processor

Copyright©2004 Vitesse Semiconductor Corporation 9


SONET/SDH Overhead Processing and
Transmission
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

 Path Overhead Generation for an STS-192


(STM-64) Signal

STS-1 #5  Line and Section Overhead Generation


H4 STS-1 #12
 Completed SONET/SDH Frame
STS-1 #32
H4 Transmitted to the Line
H4

Multiple STS-1s STS-192

Copyright©2004 Vitesse Semiconductor Corporation 10


SONET/SDH Reception and Overhead
Processing
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

 STS-192 (STM-64) Line Interface


 Section and Line Termination
 B1/B2 Error Monitoring
STS-1 #5
 Section and Line Overhead Monitoring
H4 STS-1 #12

H4 STS-1 #32
 Path Overhead Processing
H4  H4 Virtual Concatenation Byte and Payload
Extraction

STS-192 Multiple STS-1s

Copyright©2004 Vitesse Semiconductor Corporation 11


Virtual Concatenation Deinterleaving
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

 Data for each Received STS-1 is Buffered


Byte 1 in External DDR DRAM
Byte 2
STS-1 #5 Byte 3
Byte 4
 DDR RAM used for differential delay
H4 STS-1 #12 compensation
STS-1 #32
H4
 H4 Bytes are Processed
H4
 Determines the Differential Delay Between
Byte N Members
 Determines the Ordering of Members in the
Virtually Concatenated Group
Bytes Interleaved Encapsulated
Across Multiple Packet
STS-1s  Based on the H4 Bytes, the Data is
Extracted from DRAM and Deinterleaved
to Reconstruct Packets
Copyright©2004 Vitesse Semiconductor Corporation 12
Packet Extraction –
Generic Framing Protocol (GFP)
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

PLI 2 Bytes
cHEC 2 Bytes
 Generic Framing Procedure (GFP) is One of Two
Type 2 Bytes Ethernet Encapsulation Choices
tHEC 2 Bytes
Extension  Core Header is Processed to Delineate Frames
Header 2 Bytes
eHEC 2 Bytes  Type and Extension Headers are Optionally
Checked and Stripped
Ethernet Ethernet
Packet Packet  GFP FCS is Optionally Checked and Stripped

Ethernet Ethernet
FCS FCS
GFP FCS 4 Bytes
Incoming GFP Resulting
Encapsulated Ethernet
Packet Packet
Copyright©2004 Vitesse Semiconductor Corporation 13
Packet Extraction –
Link Access Procedure - SDH (LAPS)
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

Flag
 Link Access Procedure –SDH (LAPS) is
1 Byte
Address 1 Byte
One of Two Ethernet Encapsulation
Control 1 Byte Choices
SAPI 2 Bytes
 Flag Character is Used to Delineate
Ethernet Ethernet
Frames
Packet Packet
 All Fields are Optionally Checked and
Ethernet Ethernet
Stripped
FCS FCS
LAPS
FCS 4 Bytes

Incoming LAPS Resulting


Encapsulated Ethernet
Packet Packet

Copyright©2004 Vitesse Semiconductor Corporation 14


Receive FIFO Buffers Packet
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

Previous
Packet
 Extracted Ethernet Packets Placed in the
Rx FIFO for that Group

Ethernet Ethernet
Packet Packet

Ethernet Ethernet
FCS FCS

Extracted Ethernet Packet Added to


Packet Rx FIFO

Copyright©2004 Vitesse Semiconductor Corporation 15


Packet Sent Across SPI-4.2 Interface
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

Ctrl Word  Packets Sent Across SPI-4.2 Interface by


Begin
Previous
Ethernet
VCAT Mapper
Packet
Packet
Ctrl Word
 SPI-4.2 Control Words Identify Data
Ethernet Another Transferred
Packet Channel’s
Ethernet  Port Address
Data
 Start of Packet, End of Packet, Aborted Packet
Ethernet Ctrl Word
FCS Remainder  Burst are Scheduled between Ports on a
Of Ethernet
Next Packet Round Robin Basis
Packet With FCS
Ctrl Word

Packet in the Burst Interleaved


Receive FIFO Across SPI-4.2
Copyright©2004 Vitesse Semiconductor Corporation 16
Packet Reassembled and Buffered
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

Ctrl Word
Begin
Previous
Ethernet
Packet
Packet
Ctrl Word  Packet Bursts Reassembled into Packets
Another Ethernet in the Egress FIFO
Channel’s Packet
Ethernet
Data
Ctrl Word Ethernet
Remainder FCS
Of Ethernet
Packet
With FCS
Ctrl Word

Burst Interleaved Packet in Egress


Across SPI-4.2 FIFO
Copyright©2004 Vitesse Semiconductor Corporation 17
Ethernet MAC Transmits a Packet
Tx Tx
Ingress Tx Tx VC
Payload SONET/
Buffer Mapper

SPI-4.2

SPI-4.2
FIFO Processor SDH

GMII
MACs
Egress Rx Rx
FIFO Rx Rx VC
Payload SONET/
Buffer Mapper
Multi-Service MAC Processor SDH
VCAT Mapper

Inter
 Ethernet Frame Pulled from the Egress
Packet FIFO
Gap

Preamble  Included FCS Checked


SFD
 Statistics Updated
 Extensive Packet and Byte Counters
Ethernet Ethernet
Packet Packet
 Ethernet Frame Transmitted
 8B/10B Encoding For SerDes Interfaces
Ethernet Ethernet
FCS FCS  Inter Packet Gap, Preamble and Start of Frame
IPG Delimiter are Inserted as Required

Ethernet Packet Outgoing Ethernet


Packet Stream
Copyright©2004 Vitesse Semiconductor Corporation 18

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