DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING

MANIPAL INSTITUTE OF TECHNOLOGY

(A Constituent College of Manipal University)
MANIPAL 576 1! ("A#NA$A"A)% IN&IA
Manipal
'!(5('1'
CERTIFICATE
$)is is to *ertify t)at t)e pro+e*t title, Digital IC Tester using dsPIC3F3!!
"i#r$#$ntr$ller is a re*or, of t)e -onafi,e .or/ ,one -y S%a&a" Tri'at(& (#eg No0
126'!6) su-3itte, in partial fulfil3ent of t)e re4uire3ents for t)e a.ar, of t)e &egree%
5a*)elor of 6ngineering (506) in 6le*tri*al an, 6le*troni*s 6ngineering (6 7 6) of Manipal
Institute of $e*)nology Manipal% "arnata/a% (A Constituent College of Manipal University)%
,uring t)e a*a,e3i* year '1181'0
Ms) *(arat(i R)*)
Project Guide
Dr) *)+) Sing(
HOD, E&E
M.I.T, MANIPAL


AC+NO,LEDGMENTS
I .oul, li/e to t)an/ everyone .)o )a, *ontri-ute, to su**essful t)e *o3pletion of t)is pro+e*t0
$)e spe*ial t)an/ goes to 3y )elpful supervisor% Mr) Nitin -ain .)ose en*ourage3ent% gui,an*e
an, support fro3 t)e initial to t)e final level ena-le, 3e to ,evelop an un,erstan,ing of t)e
pro+e*t0 $)e supervision an, support t)at )e gave truly )elp t)e progression an, s3oot)ness of
t)e pro+e*t0 $)e *o8 operation is 3u*) in,ee, appre*iate,0
I also e9ten, 3y )eartiest t)an/s an, appre*iation to t)e )elpful people at S$na +$&$ Steering
S&te"s for t)eir support0
My grateful t)an/s also go to 3y De'art"ent Su'er.is$r Ms) *(rat(i R)*) A -ig *ontri-ution
an, *o8operation fro3 )er ,uring t)e ,evelop3ent .as very great in,ee,0 :)e too/ pains to go
t)roug) ann, 3a/e *orre*tions in t)e pro+e*t as an, .)en nee,e,0
I also .ante, to t)an/ 3y fa3ily .)o inspire,% en*ourage, an, fully supporte, 3e for every
trial t)at *o3e 3y .ay 0In giving 3e not +ust finan*ial% -ut 3orally an, spiritually0 I .oul, li/e
to t)an/ every-o,y .)o .as i3portant to t)e su**essful reali;ation of t)esis% as .ell as
e9pressing 3y apology t)at I *oul, not 3ention personally one -y one0
I e9press 3y t)an/s to Pr$/) Dr) *)+) Sing( 0 HOD0 De't0 $/ Ele#tr$ni#s and Ele#tr$ni#s% for
)is support in allo.ing us to ta/e up an, *arry out innovative pro+e*ts0
I .oul, also ta/e t)is opportunity to t)an/ t)e Dire#t$r0 Mani'al Institute $/ Te#(n$l$g& for
)is *onstant support to t)e stu,ents in *arrying out su*) pro+e*ts in a )ealt)y .o/ environ3ent
outsi,e t)e *ollege *a3pus0
A*STRACT
IC testing is of very )ig) i3portan*e in ,igital *ir*uits0 It *an )elp t)e ,esigners -y
presenting t)e3 in a,van*e .it) t)e non8fun*tioning )ar,.are0 IC testing *onventionally
re4uires ,ifferent types of *ir*uits for ,ifferent types of integrate, *ir*uits0
<ere is presente, an IC tester% .)i*) uses 3i*ro*ontroller for t)e -asi* testing0 A
3i*ro*ontroller )ere is progra33e, to tell .)et)er a parti*ular IC is .or/ing or not0 $)e
3i*ro*ontroller use, )ere is a PIC=f=11% .)i*) is a 168-it 3i*ro*ontroller0 $)e IC to -e teste,
is pla*e, in t)e >I? so*/et an, t)e *orrespon,ing IC nu3-er is entere, t)roug) an interfa*e,
/eypa,0 $)e 3i*ro*ontroller t)en goes t)roug) t)e 3ain IC testing algorit)3% an, t)en s)o.s t)e
result on t)e interfa*e, LC&0
$)e IC tester is ,esigne, )ere to test a list of 7! series logi* ICs0 $)e IC testing algorit)3
3ainly ,epen,s on t)e trut) ta-le of t)e *orrespon,ing ICs% .)i*) is fe, into t)e progra3% an, is
fet*)e, ,epen,ing on t)e nu3-er entere, -y t)e user t)roug) t)e /eypa,0 $)e ,isplay on t)e
LC& s)o.s .)i*) parti*ular pins are .or/ing an, finally s)o.s .)et)er t)e IC is goo, or -a,0
$)e -asi* a,vantages of ,esigning a 3i*ro*ontroller -ase, IC tester are t)at no
*o3pli*ate, *ir*uits are re4uire, for testing ,ifferent /in,s of ICs0 @nly t)ing t)at nee,s to -e
,one is to fee, t)e 3i*ro*ontroller .it) t)e trut) ta-le of t)e fun*tionality for t)e logi*
i3ple3ente, -y t)e parti*ular IC0 $)is fa*tor also a,,s on to a feature of t)e tester t)at t)e
,esign in pi*ture *an -e e9ten,e, to any nu3-er of ICs0 ?urt)er% a feature t)at *an -e a,,e, is
using t)e sa3e ,esign for :M& *o3ponents0 $)e progra33ing language use, is e3-e,,e, C
an, t)e progra33ing an, ,e-ugging soft.are use, is MPLA5 (a 3i*ro*)ip pro,u*t ,esigne,
espe*ially for PIC 3i*ro*ontrollers ,esigne, -y 3i*ro*)ip)0
LIST OF TA*LES
Ta1le N$ Ta1le Title Page N$
1 Pro+e*t Aor/ :*)e,ule =
LIST OF FIGURES
Figure N$ Figure Title Page N$
1 $)e progra33e for toggling P@#$ 5 of t)e Mi*ro*ontroller 5
' $ype A ti3er *ontrol register 6
= $ype 5 ti3er *ontrol register 6
! $ype C ti3er *ontrol register 7
5 5lo*/ &iagra3 of t)e *ir*uit 2
6 $ypi*al Cir*uit in <ar,.are 1
7 Pro*ess ?lo. &iagra3 11
1 Ar*)ite*ture of ,sPIC=? 1=
2 Pin &iagra3 of Controller 1!
1 Po.er generation *ir*uit '2
11 Cir*uit Conne*tions '
1' LC& Interfa*ing '=
1= "eypa, Interfa*ing '!
CONTENTS
Page No
A*/no.le,ge3ent i
A-stra*t ii
List @f ?igures iii
List @f $a-les vi
C(a'ter ! INTRODUCTION !
!)! Intro,u*tion 1
!)2 Motivation 1
!)3 Literature 1
!)3 @-+e*tive '
!)4 $arget :pe*ifi*ations '
!)5 @rganisation of t)e #eport '
!)6 Pro+e*t Aor/ :*)e,ule =
!)7 ?un*tional Partitioning of t)e Pro+e*t =
C(a'ter 2 *AC+GROUND THEORY 3
2)! Progra33ing t)e I(@ Mo,ule !
2)2 Progra33ing t)e $i3ers 5
C(a'ter 3 METHODOLOGY 8
3)! Intro,u*tion 2
3)2 Met)o,ology 2
3)3 $ools Use, ''
3)3 Con*lusion ''
C(a'ter 3 RESULT ANALYSIS 23
3)! Intro,u*tion '=
3)2 LC& Interfa*ing '=
3)3 "eypa, Interfa*ing '!
3)3 :ignifi*an*e of t)e #esult o-taine, '!
3)4 Con*lusion '5
3)5 ICs $este, '5
C(a'ter 4 CONCLUSIONS 9 FUTURE SCOPE 25
4)! A 5rief :u33ary '6
4)2 Aor/ Con*lusions '6
4)3 ?uture :*ope of Aor/ '7
REFERENCES : *I*LIOGRAPHY 27
PRO-ECT DETAILS 28
CHAPTER !
INTRODUCTION
!)! Intr$du#ti$n;
An i3portant part of -uil,ing a ,igital pro+e*t is to 3a/e sure t)at all t)e a*tive
*o3ponents .or/ properly -efore t)ey are installe,0 Unfortunately% fe. of us ,o pre8installation
tests -e*ause it is so3e.)at ,iffi*ult to routinely test ,igital ,evi*es of any /in,0 Ae si3ply
sol,er t)e parts into t)e *ir*uit% *ross our fingers an, apply po.er0 If t)e *ir*uit ,oesnBt .or/% .e
po/e aroun, till .e fin, t)e -a, part0 $)en .e repla*e it )oping t)at .e .onBt ,a3age t)e PC5%
or install anot)er ,efe*tive *o3ponent0 Clearly a -etter .ay is to test ea*) part (espe*ially ICs)
-efore using it0 In any 3anufa*turing in,ustry t)ere are *ontinuous efforts to effe*t *ost
re,u*tions% upgra,e 4uality an, i3prove overall effi*ien*ies0 In t)e ele*troni*s in,ustry% .it) t)e
,ra3ati* in*rease in *ir*uit *o3ple9ity an, t)e nee, for )ig)er levels of relia-ility% a 3a+or
*ontri-utory *ost of any pro,u*t *an -e in t)e testing0 <o.ever% in t)e real .orl, .e )ave to
re*ogni;e t)at no pro*ess *an -e perfe*t% so t)at testing% an, in parti*ular% auto3ati* testing% .ill
-e an essential part of pro,u*tion for t)e foreseea-le future0 In t)is paper t)e ,evelop3ent of a
prototype ,igital fun*tional IC tester is ,es*ri-e,0
!)2 M$ti.ati$n;
ICBs% t)e 3ain *o3ponent of ea*) an, every ele*troni* *ir*uit *an -e use, for .i,e
variety of purposes an, fun*tions0 5ut so3eti3e ,ue to faulty ICs t)e *ir*uit ,oes not .or/0 It is
a te,ious .or/ to ,e-ug t)e *ir*uit an, *onfir3 .)et)er t)e *ir*uit is *reating pro-le3 or t)e IC
itself is ,ea,0 :o to eli3inate t)is pro-le3 .e inten, to 3a/e a ,evi*e t)at .oul, *onfir3
.)et)er t)e IC un,er *onsi,eration is .or/ing properly or not0
$o,ayBs .orl, ,e3an,s a fast an, effe*tive tool to save ti3e an, )u3an effort0 Ait) t)is
pro+e*t .e save t)e effort an, ti3e of t)e user -y provi,ing a si3ple .ay to test t)e IC .it) t)e
)elp of a fast% effi*ient an, not so e9pensive 3i*ro*ontroller0
!)3 Literature;
$)e IC tester is a si3ple ,evi*e t)at tests t)e IC for its fun*tionality% .)et)er t)e IC use,
is fine or not0 A .i,e variety of ICs *an -e teste, starting fro3 t)e si3plest 1! pin ICs to
*o3ple9 ! pin ICs0 @ver t)e years of its ,evelop3ent% t)e integrate, *ir*uit te*)nology )as
-roug)t great progress to t)e ,esign of )ig) perfor3an*e syste3s0 Many *)allenges in t)e
3anufa*turing pro*ess )a, to -e solve, to a*)ieve t)is0 @ne of t)e steps in t)is pro*ess% na3ely
testing% is posing t)e 3ost signiC*ant *)allenge to *onte3porary an, future integrate, *ir*uit
(IC) 3anufa*turing0 $)is is a *ontinuing tren,% -e*ause ,ue to ,e*reasing sili*on *ost an,
in*reasing *o3ple9ity of integrate, *ir*uits% testing *onstitutes a very si;a-le portion of t)e IC
3anufa*turing *ost0 $)is tren, is furt)er a**entuate, -y t)e e3ergen*e of 3i9e, signal%
in*lu,ing ra,io fre4uen*y (#?) *ir*uits% *ouple, .it) t)e *o3petitive pri*e pressures of t)e )ig)
volu3e *onsu3er 3ar/et0 A goo, IC is one t)at satisCes all of its perfor3an*e spe*iC*ations
un,er all spe*iCe, *on,itions0 $)e pro-a-ility of a -a, IC in*reases in proportion to its si;e an,
*o3ple9ity0 It is also in*rease, -y pro*ess sensitivities t)at o**ur in ,igital an, analog ICBs t)at
rely on t)e *ontrol an,(or 3at*)ing of IC *o3ponents or para3eters to a*)ieve t)eir spe*iCe,
fun*tionality0
!)3 O1<e#ti.e;
$)e 3ain o-+e*tive of t)e pro+e*t% as its na3e suggests% is to test t)e IC un,er o-servation
an, to )elp t)e user fin, out .)i*) pins an, .)i*) gates in t)e IC are fun*tioning0 $o si3plify
t)e pro*ess% t)e entire pro*e,ure is -ro/en ,o.n into several stages of t)e pro+e*t0 All t)e stages
of t)e pro+e*t are liste,0
:tage 1D $ests .)et)er an IC is goo, or -a,
:tage 'D I,entifies t)e gates insi,e t)e IC
:tage =D :)o.s t)e fun*tioning of ea*) gate
:tage !D $ells .)i*) parti*ular gate is not .or/ing
:tage 5D &isplays on LC& .)et)er IC *an -e use, or not
!)4 Target S'e#i/i#ati$ns;
$)e en, result on*e o-taine, .ill s)o. t)e ease .it) .)i*) t)e IC tester *an -e operate,0
It .ill not only tell t)e user .)et)er t)e IC is goo, or -a, -ut .ill also )elp )i3 /no. .)at is
.rong in t)e parti*ular IC0 $)is a,,e, infor3ation *an )elp re,u*e t)e .astage of ICs +ust
-e*ause of one non8fun*tioning gate0 $)e a,vantage of t)is *an -e o-serve, in -ig 3anufa*turing
fir3s .)ere surplus 4uantities of ICs are use,0
!)5 Organi=ati$n $/ t(e re'$rt;
$)e report -egins .it) t)e -a*/groun, -asi* progra33ing /no.le,ge re4uire, to
pro*ee, on t)is pro+e*t0 It t)en ,etails t)e .or/ing 3et)o,ology use, to i3ple3ent t)e ,esign0 It
starts .it) t)e -lo*/ ,iagra3 of t)e *ir*uit re4uire, an, t)en pro*ee,s to t)e .or/ing algorit)3
for ea*) step0 $)en t)e report )as t)e *ir*uit ,iagra3 of all t)e in,ivi,ual *onne*tions follo.e,
-y t)e *o3plete *ir*uit ,iagra30 :in*e t)e entire progra3s *annot -e s)o.n )ere in t)e pro+e*t%
s*reens)ots of t)e progra3s .)ile .or/ing on t)e soft.are are s)o.n as an, .)en any progra3
is .ritten an, i3ple3ente,0
!)6 Pr$<e#t ,$r> S#(edule;
M$nt( A#ti.it& Status
Ean '1' &etaile, stu,y of t)e 3i*ro*ontroller *o3plete, an,
preparing t)e s*)e3ati* *onne*tions in progress
Co3plete,
?e- '1' Preparing t)e s*)e3ati* *onne*tions *o3plete, an,
*onstru*tion of t)e *ir*uit for t)e LC& 3o,ule in progress
Co3plete,
Mar '1' Interfa*ing t)e LC& *o3plete, an, t)e /ey-oar,0 Co3plete,
Apr '1' "ey-oar, interfa*ing an, t)e >I? so*/et interfa*ing0
:i3ultaneous ,evelop3ent of t)e *o,e
Co3plete,
May '1' &evelop3ent of t)e *o,e to in*orporate as 3any ICs as
possi-le0
Co3plete,
$a-0 1D Pro+e*t Aor/ :*)e,ule
!)7 Fun#ti$nal 'artiti$ning $/ 'r$<e#t
$)e pro+e*t )as -een ,ivi,e, into t)e follo.ing partsD
F P)ase I
$)is in*lu,es t)e ,etaile, stu,y of t)e ,sPIC=?=11 3i*ro*)ip ,ata s)eet0 Also in*lu,e,% is t)e%
t)e preparation of t)e s*)e3ati* an, *onne*tion ,etails an, )ar,.are prototype0
F P)ase II
$)is in*lu,es t)e *o,ing part of t)e pro+e*t0 $)e ,evelop3ent of t)e *o,e .ill )appen in t)is
p)ase an, t)e *o,e is si3ulate, for *orre*tness0
F P)ase III
<ere .e interfa*e t)e various ,evi*es one -y one an, a,, features0 Ae test t)e *ir*uit .it)
various ICs0
CHAPTER 2
*AC+GROUND THEORY
$)e progra33ing in t)e entire pro+e*t is *arrie, out in e3-e,,e, C0 $o learn progra33ing in C
an, to learn a-out t)e PIC 3i*ro*ontroller perip)erals% .e start progra33ing 3o,ule -y 3o,ule
an, pro*ee, to interfa*ing e9ternal ,evi*es later0
2)! Pr$gra""ing t(e I:O M$dule
All of t)e ,evi*e pins (e9*ept G,,% Gss% MCL# an,@:C1(CL"1) are s)are, -et.een t)e
perip)erals an, parallel I(@ ports0 A)en a perip)eral is ena-le, an, it is a*tively ,riving an
asso*iate, pin% t)e use of t)e pin as a general8purpose output pin is ,isa-le,0 All port pins )ave
t)ree registers ,ire*tly asso*iate, .it) t)e operation of t)e port pin0 $)e ,ata ,ire*tion register
($#I:9) ,eter3ines .)et)er t)e pin is an input or an output0 If t)e ,ata ,ire*tion -it is a H1B% t)en
t)e pin is an input0 All port pins are ,efine, as input after a reset0 #ea,s fro3 t)e lat*) (LA$9)
rea, t)e lat*)0 Arites to t)e lat*)% .rite t)e lat*) (LA$9)0 #ea,s fro3 t)e port (P@#$9)% rea, t)e
port pins% an, .rites to t)e port pins% .rite t)e lat*) (LA$9)0
T$ggling $ne 1it $/ '$rt *;
It s)oul, -e note, )ere t)at sin*e port 5 is an analog ,igital 3ultiple9e, port% A&PC?I
(analog ,igital port *onfiguration) register nee,s to -e set for t)e port to .or/ as a ,igital port0
?ig0 1D $)e progra33e for toggling P@#$ 5 of t)e Mi*ro*ontroller
2)2 Pr$gra""ing Ti"ers
A ,sPIC=? )as a total of = ti3er 3o,ules .it) 5 16 -it ti3ers0 6a*) ti3er )as t)e follo.ing
:?#s asso*iate, .it) itD
$M#9D 16 -it ti3er *ount
P#9D 16 -it perio, register
$9C@ND 16 -it *ontrol register
Asso*iate, -its for interrupt *ontrolD
$9I6D Interrupt ena-le (in I6C9 :?#)
$9I?D Interrupt flag status -it (in I?:9 :?#)
$9IPD Interrupt priority *ontrol -its (in IPC9 :?#)
$)ere are 5 ti3ers in ,sPIC=f=110 $)ese five ti3ers *an -e groupe, into = typesD
T&'e A ti"er;
?ro3 ,evi*e lo. po.er =' "<; os*illator
?ro3 an e9ternal *lo*/ sour*e in asyn*)ronous 3o,e
$i3er 1 is a type A ti3er0 $)e *ontrol register is s)o.nD
?ig0 'D $ype A ti3er *ontrol register
$@NJ1 D $i3er on
$:I&LJ1 D $i3er .ill stop .)en CPU is in i,le 3o,e
$IA$6J1 D $i3er gate operation is set (ti3er runs only .)en $1C" is )ig))
$C"P:K1DLD Pres*aling t)e input *lo*/
$C:J1 D $i3er *lo*/ sour*e is e9ternal
$:MNCJD 69ternal *lo*/ sour*e is asyn*)ronous
T&'e * ti"er
Can -e *on*atenate, .it) type C to for3 a =' -it ti3er
Clo*/ syn*)roni;ation after pres*ale logi*
$i3er ' an, = are type 5 ti3er0 $)e *ontrol register is s)o.nD
?ig0 =D $ype 5 ti3er *ontrol register
T&'e C ti"er
Can -e *on*atenate, .it) type 5
At least one type C *an trigger A(& *onversion
$i3er ! an, 5 are type C ti3er0 $)e *ontrol register is s)o.nD
?ig0 !D $ype C ti3er *ontrol register
$i3ers *an -e operate, in various 3o,es0 5elo. are 3entione, a fe. 3o,esD
Ti"er "$de
All ti3ers *an .or/ in t)is 3o,e0
Input *lo*/ is t)e internal syste3 *lo*/ (?os*(!)
$C:J ($9C@NK1L)
$:MNC ($9C@NK'L) )as no effe*t
S&n#(r$n$us #$unter "$de using e?ternal #l$#> in'ut
$C:J1
$:MNCJ1 (for type A)
$ype 5 7 C D e9ternal *lo*/ sour*e is al.ays syn*)roni;e,
As&n#(r$n$us #$unter "$de using e?ternal #l$#> in'ut
@nly type A
$C:J1
$:MNCJ
A,vantagesD
Can operate in sleep 3o,e an, *an .a/e up t)e pro*essor on P# 3at*)
$i3e -ase *an -e po.ere, fro3 lo. po.er =' "<; os*illator
Ti"er $'erati$n %it( /ast e?ternal #l$#> s$ur#e
$ype A 7 5 D *lo*/ syn*)roni;ation after ti3er pres*aler
Gated ti"e a##u"ulati$n "$de
$i3er .or/s .)en $9C" pin is )ig)
Clo*/ sour*e is internal syste3 *lo*/
$i3er *ounts till eit)er P# or till $9C" pin is )ig) ($9I? goes )ig) .)en ti3er stops *ounting)
$IA$6J1 ($@NJ1% $C:J)
CHAPTER 3
METHODOLOGY
3)! Intr$du#ti$n;
$)is *)apter tells in ,etail a-out t)e 3et)o, of i3ple3entation of t)e *ir*uit0 It starts
.it) t)e -lo*/ ,iagra3 of t)e *ir*uit0 It is t)en follo.e, -y a progra3 flo. ,iagra30 $)e *)apter
t)en pro*ee,s .it) t)e ,etaile, algorit)3 of ea*) step telling t)e progra33ing flo. at a 3i*ro
level0 Ne9t *o3es t)e *o3plete *ir*uit ,iagra30 $)is s)o.s t)e final *onne*tion of t)e *ir*uit0
$)e *)apter t)en ,etails a-out t)e *o3ponents an, t)e tools use, to *o3plete t)e pro+e*t0
3)2 Met($d$l$g&;
3)2)! *l$#> Diagra" $/ t(e #ir#uit;
?ig0 5D 5lo*/ &iagra3 of t)e *ir*uit
6a*) an, every -lo*/ a-ove )as to -e interfa*e, .it) t)e 3i*ro*ontroller0 $)e 3i*ro*ontroller
ta/es in input fro3 t)e /ey-oar, t)at it uses later in t)e progra3 to i,entify t)e IC inserte, an, to
sen, )ig) or lo. signals to t)e IC0 $)e trut) ta-le of ea*) IC is follo.e, in t)e respe*tive
3o,ule of t)e progra3 an, t)e signals are sent to t)e input pins of t)e IC a**or,ingly0 $o *)e*/
Po.er :upply
Crystal Cir*uit
#eset Cir*uit
"ey
IC to -e
teste,
M
I
C
#
@
C
@
N
$
#
@
L
L
6
#
.)et)er t)e IC is fun*tioning properly t)e output fro3 t)e IC is retrieve, -y t)e 3i*ro*ontroller0
$)e po.er supply )ere is 3a,e to prevent *osts ,ue to -attery usage0 It is a si3ple 5 G po.er
supply% .)i*) is ,esigne, to ta/e in nor3al ''G AC 3ains supply0
?ig0 6D $ypi*al Cir*uit in <a,.are
Inputs an, @utputsD
Po.er :upply
IC to -e teste,
"eypa,
Li4ui, Crystal &isplay
<ar,.areD
Co3ponents of a regulate, po.er supply
,sPIC=?=11 3i*ro*)ip
Li4ui, Crystal &isplay
IC to -e teste,
"ey -utton
>I? :o*/et
3)2)2 Alg$rit("; ?ig 7D Pro*ess ?lo. &iagra3
P@A6# @N
P@A6# @N
MIC#@C@N$#@LL6# INI$IALI:A$I@N
"6MPA& INI$IALI:A$I@N
LC& INI$IALI:A$I@N
INPU$ ?#@M >I? :@C"6$
IC $6:$INI #@U$IN6 "6MPA& :CANNINI U:6# INPU$
#6:UL$ &I:PLAM @N LC&
$)e a-ove ,iagra3 s)o.s t)e pro*ess flo. of t)e IC testing pro*e,ure0 $)e ,etaile, algorit)3
for ea*) su- pro*ess is 3entione, -elo.D
Mi#r$#$ntr$ller initiali=ati$n;
Conne*ting Gss an, G,,
:ele*ting *lo*/ fre4uen*y (-au, rate if any serial *o33uni*ation is re4uire,)
?ig0 1D ,sPIC=? ar*)ite*ture
?ig0 2D $)e pin ,iagra3 of t)e *ontroller use,
Mi*ro*ontroller featuresD
<ig) perfor3an*e 3o,ifie, #I:C CPU0
Mo,ifie, <arvar, ar*)ite*ture .it) fle9i-le a,,ressing 3o,es0
1= -ase instru*tions0
'!8-it .i,e instru*tions% 168-it .i,e ,ata pat)0
'! "-ytes on8*)ip ?las) progra3 spa*e (1" Instru*tion .or,s)0
1 "-yte of on8*)ip ,ata #AM0
1 "-yte of non8volatile ,ata 66P#@M0
16 9 168-it .or/ing register array0
Up to = MIPs operationD
o &C to ! M<; e9ternal *lo*/s input0
o ! M<;81 M<; os*illator input .it) PLL a*tive (!9% 19% 169)0
'2 interrupt sour*es
o = e9ternal interrupt sour*es0
o 1 user8sele*ta-le priority levels for ea*) interrupt sour*e0
o ! pro*essor trap sour*es0
Perip)eral ?eaturesD
o <ig)8*urrent sin/(sour*e I(@ pinsD '5 3A('5 3A
o $i3er 3o,ule .it) progra33a-le pres*alerD
?ive 168-it ti3ers(*ountersN optionally pair
168-it ti3ers into ='8-it ti3er 3o,ules
o 168-it *apture input fun*tions
o 168-it *o3pare(PAM output fun*tions
o =8.ire :PI 3o,ules (supports ! ?ra3e 3o,es)
o I'C$M 3o,ule supports Multi8Master(:lave 3o,e an, 78-it(18-it a,,ressing
o ' UA#$ 3o,ules .it) ?I?@ 5uffers
18-it Analog8to8&igital Converter (A&C) .it)
! :(< InputsD
o 1 Msps *onversion rate
o 2 input *)annels
o Conversion availa-le ,uring :leep an, I,le
Progra33a-le 5ro.n8out #eset
Lo.8po.er% )ig)8spee, ?las) te*)nology
Ai,e operating voltage range ('05G to 505G)
In,ustrial an, 69ten,e, te3perature ranges
Lo. po.er *onsu3ption
?le9i-le Aat*),og $i3er (A&$) .it) on8*)ip lo. po.er #C os*illator for relia-le
operation
?ail8:afe *lo*/ 3onitor operation ,ete*ts *lo*/ failure an, s.it*)es to on8*)ip lo.8
po.er #C os*illator
Progra33a-le *o,e prote*tion
In8Cir*uit :erial Progra33ingO (IC:PO)
:ele*ta-le Po.er Manage3ent 3o,esD
8 :leep% I,le an, Alternate Clo*/ 3o,es
LCD initiali=ati$nD
LC&8 ' lines% 5P7 3atri9
Call ,elay an, *o33an, su-routine
&isplay on *ursor -lin/ing
Call ,elay an, *o33an, su-routine
Co33an, su-routine (value)
Q
L*,Rrea,y()N
Put SvalueT on pinsN
#sJN r.JN enJ1N
#eturnN
6nJN
U
&elay()
&ataR,isplay su-routine (value)
Q
l*,Rrea,y()N
Put SvalueT on pinsN
rsJ1N r.JN enJ1N
returnN
enJN
U
l*,Rrea,y()
Q
5usyJ1N
#sJN r.J1N
.)ile (-usyJJ1)
Q
enJN ,elay()N enJ1N
U
returnN
U
+e&'ad Initiali=ati$n;
for( iJN iJK=1NiVV)
Q if( valueJJ1)
Q iJiV1N
if(iJJ=1)
Q iJN
U
U
U
if (fi9JJ 1U
LC&R*o33an,(91!)N
U
s.it*) (i)
Q
*ase 1D
LC&Rputs(ST)
-rea/N
*ase 'D
LC&Rputs(S1T)
-rea/N
WW00
*ase 1D
LC&Rputs(S2T)
-rea/N
*ase 11D
LC&Rputs(SAT)
-rea/N
*ase 1'D
LC&Rputs(S5T)
-rea/N
WW0
*ase =5D
LC&Rputs(SMT)
-rea/N
*ase =6D
LC&Rputs(S>T)
-rea/N
,efaultD
-rea/N
U
IC testing;
A ,ata-ase is prepare, for all t)e ICBs t)at *an -e teste,
I(p is ta/en fro3 t)e /eypa, to i,entify t)e IC
Correspon,ing infor3ation is fet*)e, fro3 t)e ,ata-ase
#e4uire, o(p goes fro3 3i*ro*ontroller to t)e IC 7 IC is teste, for *orrespon,ing
appropriate o(p
@(p is given to t)e LC& to ,isplay result
Result dis'la& $n t(e LCD;
I(p is re*eive, fro3 t)e IC testing progra3
Correspon,ing 3essage is to -e ,isplaye, on t)e LC&
&ata ,isplay su-routine is fet*)e, fro3 LC& initiali;ation
@(p is ,isplaye, on t)e LC&
LC& is t)en *leare, an, a 3essage S:.aya3 $ripat)yT is ,isplaye,0
+e&'ad C$nne#ti$ns;
$)e /eypa, use, )ere is a t.o8-utton "eypa, /eypa,0 It is *onne*te, to t)e I(@ ports of t)e
3i*ro*ontroller0 $)e 3i*ro*ontroller is progra33e, su*) t)at it ,ete*ts any press of /ey on t)e
/eypa, an, t)e *orrespon,ing nu3-er is sent to t)e progra3 for i,entifi*ation of t)e IC0
LCD C$nne#ti$n;
$)e LC& )ere is *onne*te, to t)e 3i*ro*ontroller for a ! -it ,ata transfer0 @nly t)e )ig)er ! -its
of t)e ,ata pin are *onne*te, to t)e 3i*ro*ontroller0 Port 6 is use, for ,ata an, *o33an, transfer
to t)e LC&0
$)e LC& use, is E<& 16'A0 $)e spe*ifi*ations are as follo.sD
&isplay *onstru*tion 16 C)ara*ters X ' Lines
&isplay 3o,e $N(:$N
&isplay type Positive $ransfle*tive
5a*/lig)t L6&(5(50G)
Gie.ing ,ire*tion 6 oB*lo*/
@perating te3perature In,oor
&riving voltage :ingle Po.er
&riving 3et)o, 1(16 ,uty% 1(5 -ias
$ype C@5 (C)ip @n 5oar,)
Nu3-er of ,ata line 1 -it parallel
Conne*tor Pin
?ig0 1D Cir*uit Conne*tion
?or t)e 6 pinD
$)is line allo.s a**ess to t)e ,isplay t)roug) #(A an, #: lines0 A)en t)is line is lo.% )e LC&
is ,isa-le, an, ignores signals fro3 #(A an, #:0 A)en (6) line is )ig)% t)e LC& *)e*/s t)e
state of t)e t.o *ontrol lines an, respon,s a**or,ingly0
D A**ess to LC& ,isa-le,
1 D A**ess to LC& ena-le,
?or t)e #: pinD
Ait) t)e )elp of t)is line% t)e LC& interprets t)e type of ,ata on ,ata lines0 A)en it is lo.% an
instru*tion is -eing .ritten to t)e LC&0 A)en it is )ig)% a *)ara*ter is -eing .ritten to t)e LC&0
D Instru*tion Input
1D &ata Input
?or t)e #(A pinD
$)is line ,eter3ines t)e ,ire*tion of ,ata -et.een t)e LC& an, 3i*ro*ontroller0 A)en it is lo.%
,ata is .ritten to t)e LC&0 A)en it is )ig)% ,ata is rea, fro3 t)e LC&0
D Arite to LC& Mo,ule
1 D #ea, fro3 LC& Mo,ule
Ariting t)e ,ata to t)e LC& is ,one in several stepsD
1) :et #(A -it to lo.
') :et #: -it to logi* or 1 (instru*tion or *)ara*ter)
=) :et ,ata to ,ata lines (if it is .riting)
!) :et 6 line to )ig)
5) :et 6 line to lo.
6) #ea, ,ata fro3 ,ata lines (if it is rea,ing)
Conne*tions in t)e LC& 3o,uleD
?ig0 11D LC& &iagra3
1 G:: (Po.er :upply Iroun,)
' GCC (Po.er :upply (V5G))
= G66 (Contrast A,+ust)
! #: (#egister :ele*t Pin)
5 #(A (#ea, ( Arite :ignal)
6 6 (6na-le :ignal)
7 & (&ata Line) (L:5)
1 &1 (&ata Line)
2 &' (&ata Line)
1 &= (&ata Line)
11 &! (&ata Line)
1' &5 (&ata Line)
1= &6 (&ata Line)
1! &7 (&ata Line) (M:5)
15 L6&V (5a*/lig)t Cat)o,e)
16 L6&8 (5a*/lig)t Ano,e)
3)2)3 P$%er Su''l&
Cir#uit diagra"
?ig0 1'D Po.er generation *ir*uit
E?'lanati$n
$)e po.er supply re4uire, for t)e 3i*ro*ontroller is in t)e range of '05G8505G &C0 It
is 3ore e*ono3i*al to ,esign a 5G po.er supply t)an to use a -attery supply0 A step ,o.n
transfor3er is use, t)at *onverts '=G AC supply in pri3ary .in,ings to 1'G AC supply in
se*on,ary .in,ings0 A -ri,ge re*tifier is ,esigne, using 1N!1 ,io,es to *onvert AC to &C0
$)e &C pro,u*e, -y t)e re*tifier a-ove )as 3any ripples an, to pro,u*e a s3oot) &C supply
.e use a !7Y? *apa*itor0 $)e output of t)is *apa*itor (its *)arging an, ,is*)arging) serves
as t)e input to t)e voltage regulator0 An IC 715 is use, for voltage regulation to give an
output of 5 volt0
$)e ,evi*es *onne*te, in*lu,e t)e LC& s*reen% t)e pus) -utton /ey% t)e po.er supply% t)e
*rystal *ir*uit% t)e reset *ir*uit an, t)e >I? so*/et for t)e IC to -e teste,0
$)e 3i*ro*ontroller use, is in t)e $Z?P arrange3ent0
$)e >I? so*/et is a 1!8pin >I? so*/et0
$)e nu3-er of pus) -utton /eys use, is t.o0 @ne for fee,ing in t)e na3e of t)e IC for
referen*e in t)e LU$s present for testing purposes an, t)e ot)er for fi9ing t)e sele*te,
value0
$)e po.er supply use, is a regulate, 5G &C supply0
$)e reset *ir*uit is present on t)e *ontroller -oar, availa-le in t)e La- of t)e ,epart3ent0
$)e *rystal *ir*uit is present on t)e *ontroller -oar, availa-le in t)e La- of t)e
,epart3ent0
$)e LC& use, is a 169' LC& s*reen0
3)3 TOOLS USED
:ol,ering of all t)e a-ove *o3ponents is ,one 3anually on a *opper -are -oar, using
sol,ering iron0
@n*e any *ir*uit is *o3plete% t)e *ontinuity is *)e*/e, using a ,igital 3ulti3eter0
A progra3 is .ritten on t)e soft.are availa-le0
$)e progra3 is .ritten% *o3pile,% -uilt an, run on t)e si3ulator first0
If t)e progra3 is fun*tioning .ell% it is t)en -urnt on to t)e 3i*ro*ontroller using MPLA5
IC& (in *ir*uit ,e-ugger)0
:A $oolD MPLA5 I&6 v10=6
Co3piler C= v=0'5
<A $oolD Pspi*e for ,e-ugging *ir*uits
3)3 CONCLUSION
$)e pro*e,ure% as it *an -e seen in t)is *)apter is -ro/en ,o.n into su- parts for ease
of un,erstan,ing an, i3ple3entation0 6a*) an, every interfa*ing is ,one turn8-y8turn an,
*)e*/e, for a**ura*y0 ?irst t)e /eypa, is interfa*e,0 It is follo.e, -y i3ple3entation of LC&
interfa*ing0 After -ot) t)e I(@ ,evi*es are interfa*e, an, t)ey are .or/ing s3oot)ly -ot) on
t)e si3ulator an, t)e )ar,.are% .e pro*ee, .it) t)e progra3 to test t)e IC -ase, on t)e
infor3ation given to us -y t)e user t)roug) t)e /eypa,0 $)is -it of *o,e is at last 3erge, .it)
-ot) t)e *o,es as ,ata input an, output syste30
CHAPTER 3
RESULT ANALYSIS
3)! Intr$du#ti$n
$)e *)apter s)o.s a gli3pse of )o. t)e progra3s in t)e pro+e*t are stru*ture,0 It s)o.s t)e
i3ple3entation of t)e progra3 using t)e 3i*ro*)ip soft.are *alle, MPLA50 $)e progra3s
for LC& an, /eypa, interfa*ing along .it) t)e 3ain *o,e lengt) for IC testing *annot -e
,is*usse, )ere0 :till a s*reens)ot of all t)e progra3s an, .or/spa*e on MPLA5 is s)o. )ere
to give a -rief overvie. of t)e pro*ess0 $)ese progra3s .ere t)en -urnt on t)e
3i*ro*ontroller0 Pla*ing of t)e 3i*ro*ontroller in t)e *o3plete *ir*uit -oar, t)en follo.e, it0
3)2 LCD Inter/a#ing
?ig0 1=D LC& interfa*ing
3)3 +e&'ad Inter/a#ing
?ig0 1!D "eypa, Interfa*ing
3)3 Signi/i#an#e $/ t(e Result O1tained
$)e result% .)i*) is seen after i3ple3enting t)e progra3% s)o.s )o. t)e 3i*ro*ontroller
tests t)e given IC for t)e fun*tioning of ea*) an, every gate0 $)is )elps t)e user to fin, out
.)at e9a*tly is .rong in an IC an, up to .)at e9tent is it fun*tioning0 If suppose an IC )as
four logi* AN& gates out of .)i*) only one is not goo,% t)e IC tester )elps us /no. t)at0 In
su*) a situation% sin*e .e /no. .)at e9a*tly is .rong in an IC% t)e rest of t)e IC *an -e use,
appropriately .it)out any glit*)0
$)e IC tester ,esigne, )ere also is very )an,y sin*e it is a porta-le ,evi*e t)at *an -e easily
*arrie, along0 Also% t)e ,esign is not ,evi*e spe*ifi*N t)at is to say% it *an -e e9pan,e, to fit in
testing of any logi* IC .)ose trut) ta-le is /no.n0 $)e tester ,esigne, )ere only tests 7!
series logi* ICs0
3)4 C$n#lusi$n
$)e result o-taine, )ere-y is very si3ple to un,erstan, for any user0 Also% t)e result is very
spe*ifi* an, tells t)e pre*ise fun*tioning of t)e IC0 $)is *an also )elp t)e user to /no.
i,entify t)e logi* gates present an, un,erstan, itBs fun*tioning if it is not alrea,y /no.n0
3)5 ICs Tested;
7!D 4ua, ' input NAN& gate
7!1D 4ua, ' input AN& gate
7!='D 4ua, ' input @# gate
7!16D 4ua, ' input P@# gate
CHAPTER 4
CONCLUSIONS 9 FUTURE SCOPE OF ,OR+
4)! A *rie/ Su""ar&
4)!)! Pr$1le" state"ent
$esting of an ICBs fun*tionality is of ut3ost i3portan*e in ,igital IC testing0 IC testers
availa-le )ave ,ifferent *ir*uits for ,ifferent types of ICs0 &esign a universal IC tester% .)i*)
*an .or/ for any logi* IC -ase, on its trut) ta-le0 #e,u*e t)e *ir*uitry as 3u*) as possi-le
an, si3plify t)e *ir*uit using a 3i*ro*ontroller0 Progra3 t)e 3i*ro*ontroller to i,entify t)e
IC an, let t)e user /no. .)at gates an, in turn .)at pins are fun*tioning0
4)!)2 ,$r> "et($d$l$g&
As 3entione, earlier% t)e IC to -e teste, is pla*e, on t)e >I? so*/et an, t)e IC nu3-er is to
-e entere, -y t)e user t)roug) t)e /eypa,0 $)e progra3% .)i*) is -urnt on t)e
3i*ro*ontroller% rea,s t)e ,ata entere, -y t)e user an, uses it to i,entify t)e IC an, start t)e
testing of t)e ,evi*e0 $)e results step -y step are s)o.n on t)e LC& present0 $)e
re4uire3ents in t)e pro+e*t are a -asi* un,erstan,ing of any progra33ing language0 $)e
progra33ing language use, )ere is e3-e,,e, C0 Progra33ing t)e I(@ ports an, ti3ers an,
t)e interrupts separately initially learn t)e progra33ing *on*ept0 @n*e t)e I(@ port an, ti3er
is su**essfully progra33e,% an L6& is *onne*te, to t)e i(o pin to s)o. t)e fun*tioning0
$)en later% giving t)e3 various priority levels also progra3s .it) 3ore t)an one ti3er0 $)us
.e learn t)e *on*ept of servi*ing 3ultiple interrupts at a ti3e0 $)e snaps)ots of all t)ese
progra3s are s)o.n previously in t)e pro+e*t0
$)e 3i*ro*ontroller is t)en turn -y turn interfa*e, .it) t)e LC& an, t)en t)e /eypa,0 $)e
/eypa, use, is a 3atri9 /eypa, an, a -utton press is ,ete*te, -y *ontinuously s*anning for a
press0 A )ig)er priority is given to t)e /eypa, s*anning su-routine0 $)e LC& is interfa*e, to
t)e 3i*ro*ontroller using a ! -it ,ata transfer s*)e3e -e*ause of t)e lo.er nu3-er of I(@
pins availa-le on t)e 3i*ro*ontroller0
$)e progra3s are si3ulate, on a soft.are *alle, MPLA5 an, t)en t)e 3i*ro*ontroller is
progra33e, using MPLA5 IC& (in *ir*uit ,e-ugger)0 $)e final pro+e*t is teste, using a fe.
ICs of t)e 7! series0
4)2 C$n#lusi$ns
4)2)! General #$n#lusi$ns
$)e pro+e*t )ere 3ainly s)o.s t)e a,vantages of using a 3i*ro*ontroller as a ,esign -ase for
si3plifying *ir*uits an, re,u*ing t)eir si;e an, *ost at t)e sa3e ti3e0 $)ere are IC testers
availa-le in t)e 3ar/et% .)i*) are eit)er *ostly or -ul/y0 $)e -ul/iness of t)e *ir*uit is )ig)ly
re,u*e, -e*ause in t)e ,esign presente, in t)is pro+e*t 3ainly revolves aroun, )e progra3
.)i*) pi*/s up t)e *ase asso*iate, .it) t)e IC in 4uestion% an, )an,les t)e testing0 :in*e t)e
3ain *o3ponent of t)e ,esign is +ust a 3i*ro*ontroller .it) an LC& an, a /eypa, as input
output ,evi*es% t)ere is no 3u*) *ost involve,0
4)2)2 Signi/i#an#e $/ result $1tained
$)e result% .)i*) is seen after i3ple3enting t)e progra3% s)o.s )o. t)e 3i*ro*ontroller
tests t)e given IC for t)e fun*tioning of ea*) an, every gate0 $)is )elps t)e user to fin, out
.)at e9a*tly is .rong in an IC an, up to .)at e9tent is it fun*tioning0 If suppose an IC )as
four logi* AN& gates out of .)i*) only one is not goo,% t)e IC tester )elps us /no. t)at0 In
su*) a situation% sin*e .e /no. .)at e9a*tly is .rong in an IC% t)e rest of t)e IC *an -e use,
appropriately .it)out any glit*)0
4)3 Future S#$'e $/ ,$r>
$)e IC tester ,esigne, )ere *an -e later on e9pan,e, to .or/ for 3ore nu3-er of ICs0 $)is is
one of t)e 3ain a,vantages0 Anyone .)o )as a little progra33ing /no.le,ge *an e9pan, t)e
sour*e *o,e to test any IC .)ose logi* fun*tioning *an -e ta-ulate, in t)e for3 of a trut)
ta-le0 6ven if t)e fun*tioning of a pin is /no.n an, t)e output is al.ays an e9pe*te, value%
t)e IC *an -e teste, using t)is 3et)o,0
As of no. in t)e pro+e*t only lea,e, *o3ponents *an -e teste, sin*e .e )ave use, a >I?
so*/et )ere0 $)is testing *an also -e e9ten,e, to surfa*e 3ount ,evi*es0 It *an -e ,one -y
si3ply using an :M& to lea,e, *o3ponent *onverter0 $)e *onverter *an -e 3ounte, on to
t)e >I? so*/et an, t)en ,esign presente, )ere .ill *)e*/ -ot) lea,e, *o3ponents an, surfa*e
3ount ,evi*es0
@n*e a t)oroug) stu,y of ot)er *o3ple9 ICs is ,one% an, t)eir fun*tioning is un,erstoo,% t)e
,evi*e *an -e progra33e, to test all /in,s of ICs an, t)us *an )elp t)e user /no. .)at
e9a*tly is .rong insi,e an IC0 $)is *an )elp prevent t)e .astage of a .)ole IC +ust -e*ause a
fe. non8fun*tioning pins0
REFERENCES
[1\ :trun; #% $oal & an, M*Io.an C% SA soft.are( )ar,.are ,igital -ase, fun*tional IC
testerT% &epart3ent of 6le*troni*s% University of Li3eri*/% Irelan,0
['\ Mu)a33a, Ali Ma;i,i% Eani*e Iillispie Ma9i,i an, #olin &0 M*"inlay% $)e 151
Mi*ro*ontroller an, 63-e,,e, :yste3s% Pearson 6,u*ation% '20 I:5N 2718118=1781'685
[=\ An,re. Iro*)o.s/i% &e-as)is 5)atta*)arya% $0 #0 Gis.anat)an an, "en La/er%
SIntegrate, Cir*uit $esting for Zuality Assuran*e in Manufa*turingD <istory% Current :tatus%
an, ?uture $ren,sT% I666 $#AN:AC$I@N: @N CI#CUI$: AN& :M:$6M:]IID
ANAL@I AN& &III$AL :IINAL P#@C6::INI% volu3e no0 !!% 1227% page nu3-ers8 '!
[4] A)3e,% M0:0% U3air% I0M0% 7 Me)-oo-% "0 ('5)0 Mi*ro*ontroller 5ase, IC $ester0
6ngineering :*ien*es an, $e*)nology% '50 :C@N6:$ '50 :tu,ent Conferen*e on % 8
(8 )% 18!0
Reference / Hand Boo!
[1\ ,sPIC=?=1(=11 ,atas)eet% Mi*ro*)ip% '6
['\ E<& 16'A ,atas)eet% un/no.n% ver 10
[=\ C)oosing an Appropriate Pull8up(Pull8,o.n #esistor for @pen &rain @utputs% $e9as
Instru3ents
PRO-ECT DETAILS

"tudent Detai#!
Student Na"e S%a&a" Tri'at(&
#egister Nu3-er 126'!6 :e*tion ( #oll No C(1'
63ail A,,ress s.aya3tripat)y^live0in P)one No (M) 265!6=27=
Project Detai#!
Pr$<e#t Title Digital IC Tester using dsPIC3F3!! "i#r$#$ntr$ller
Pro+e*t &uration 16 .ee/s &ate of reporting 17
t)
Ean0% '1'
Or$ani%ation Detai#!
Organi=ati$n Na"e S$na +$&$ Steering S&ste"s Li"ited
?ull postal a,,ress
.it) pin *o,e
:ona "oyo :teering :yste3s Lt,0
=1(6% N<81% &el)i8Eaipur #oa,% Iurgaon
1''1 <aryana IN&IA
Ae-site a,,ress ...0sonagroup0*o3
"u&er'i!or Detai#!
Su'er.is$r Na"e Mr) Nitin -ain
&esignation &eputy Manager
?ull *onta*t a,,ress
.it) pin *o,e
Mr0 Nitin Eain
#7& 6le*troni*s%
:ona "oyo :teering :yste3s Lt,0%
=1(6% N<81% &el)i8Eaipur #oa,% Iurgaon
!22! Har&ana INDIA
63ail a,,ress nitin0+ain^sonagroup P)one No (M) 21212'12!!
Interna# Guide Detai#!
Fa#ult& Na"e Ms) *(arat(i R)*)
?ull *onta*t a,,ress
.it) pin *o,e
&ept of 6le*tri*al 7 6le*troni*s 6ngg% Manipal Institute of
$e*)nology% Manipal 576 1! ("arnata/a :tate)% IN&IA
63ail a,,ress -)arat)i0r-^3anipal0e,u