Introduction to Mentor Graphics:-ICFlow2006.

1
It is a comprehensive and proven set of building blocks that enables semiconductor
companies and electronics systems manufacturers to jump-start their design cycles
hence reducing time-to-market and ensuring manufacturing success of ICs. This
Mentor Graphics integrated IC Flo consists of the folloing tools! "esign #rchitect-IC
for schematic entry$ %ldo and #"M& for analog and mi'ed-signal simulation$ IC
&tation and ICassemble for schematic-driven layout and chip assembly$ and Calibre
for "(C)*+& verification and e'traction. The Mentor Graphics Technology "esign ,its
include all of the overhead symbols necessary to set up a schematic to simulate-
including current sources$ I)- pins$ voltage references and more.
Invoking the ool
It can be invoked by giving command icstudio &. It is available only on .C* computers
so you have to log on to one of those computers.
!esign Flow "verview
The design flo primarily includes creating a schematic$ setting up a testbench$
simulating a design and laying out that design. It is also described in the above figure.
Creating a #ro$ect
%tep 1: -pen IC&tudio by typing the command icstudio/ the IC&tudio interface ill be
invoked and appear on the screen.
%tep 2: To create a project click on File & 'ew & #ro$ect from the menu bar. The 'ew
#ro$ect setup i0ard ill open to help you in creating the ne project. 1ress 'e(t to
proceed ith the i0ard.
%tep ): %nter the project name and brose for the project location and then press 'e(t.
%tep *: 1ress on the "pen +ocation Map ,ditor button to set your location map.
%tep - : &elect ,dit Menu folloed by .dd MGC !esign /it. This ill add a ro ith
a library name MGC0!,%IG'0/I. #lso to add standard libraries$ again select ,dit
Menu$ and then select .dd %tandard MGC +i1raries.

%tep 6: #fter that press "/. 1ress 'e(t to proceed. This ill proceed onto the
echnolog2 %ettings. 1ress "pen %etting ,ditor to set the technology settings.
%tep 3: 2rose for the paths of the #rocess 4ile$ !5C$ +6%$ %!+ and #,7 rule files.
2rose appropriate rule files. 3ith in the 4MC library$ they are available as give
belo.
1rocess! )cad)Mentor5tools)umc5678)process
"(C! )cad)Mentor5tools)umc5678)rule5deck)"(C)9Choose5appropriate
*+&! )cad)Mentor5tools)umc5678)rule5deck)*+&)9Choose5appropriate
Click -,.
%tep 8: 1ress "/ to return back to the main i0ard. # summary of all the previous steps
ill then be shon.
%tep 9: 1ress Finish to finali0e the creation of ne project. This is ho the IC&tudio
interface ill look like after creating the ne project.
Creating +i1rar2
%tep 1: o create a li1rar2 click on File & 'ew & +i1rar2 from the menu bar. #
indo ill pop-up asking for the library name.
Creating a %che:atic Cell 6iew
%tep 1: To create a schematic cell click on File & 'ew & 6iew from the menu bar. #
indo ill pop-up asking for the cell name$ and vie type. *et the cell name be
inverter and choose %che:atic as vie type$ the vie name ill be named
automatically %che:atic.
%tep 2: 2y 1ressing Finish this ill open the "esign-#rchitect IC.
Creating a %che:atic
%tep 1: From the left icon palette press on .dd !evice icon. The !evice +i1rar2
dialog bo' containing the entire device list for this process ill pop-up. .oy key a can
also be pressed to call the same dialog bo'.
%tep 2: &elect the Mos4et from the !evice +i1rar2 dialog bo' to call the dialog bo' of
the analog M-&F%Ts. &elect the :M-&; press "/. #n image of the transistor ill be
tied to the cursor. 1lace the nmos transistor in the schematic. &imilarly place a pmos
transistor in the schematic.
%tep ): 1oer could be added by pressing ;.dd Instance< icon in the left icon palette
or the hot key i to call an .dd Instance indo. &elect the MGC0IC0G,',5IC0+I<
library folloed by 6!! cell and its %2:1ol vie. 1lace it in the schematic indo.
"o the same for Ground.
%tep *: 1lace the I' and "= ports in a similar ay or by pressing the >.dd #ort?
icon in the left icon palette.
%tep -: 1lace the cursor over the :%T on the left of the I' port. &elect %hi4t-F3 key.
This ill bring up a form as shon belo. %nter I' for the net name.
%tep 6! Connect the devices by dragging the mouse from the pin of the device. =ou
can also use the hot key w.
%tep 3: "o the same for the "= net. The schematic should no look as follos.
%tep 8! :o from the right palette select Check @ %ave.
Generating a symbol
%tep 1: &elect ools & Generate %2:1ol from the pull don menu. 3hen generate
symbol is selected$ the ne't form ill popup. =ou can "/ the form or you can change
the shape to be a buffer and add a circle to create a classic inverter shape.
%tep 2: 3hen you finish editing the symbol click Check @ %ave.
Creating a Test Bench

%tep 1: Go back to ICstudio. :otice that no the created lib contains a cell ith
to vies$ a &chematic and &ymbol vie. Create a ne cell ith a &chematic
vie named test5bench.
%tep 2: :o instantiate the ne inverter symbol by selecting .dd & Instance from
the
%che:atic ,dit 1alette menu or pressing the hot key i. &elect the %2:1ol vie
of the inverter cell.
%tep ): #dd the I' and "= net as before by selecting the hot key i. :ame the nets
ith shi4t-F3 function key. #dd 6!! and Ground ports in a similar fashion.
%tep *: #dd a "C voltage source dc0v0source$ from the MGC0IC0%"=5C,%0+I<.
Change the value of the !C property to be ).)6. #dd 14*&% voltage source
pulse0v0source and change the value of the pulse0value property to be ).)6
change also the dela2 to be 0%. The testbench schematic may look like as shon
belo!
%tep -: &elect Check @ %ave to &ave schematic changes.
%i:ulating %che:atic
%tep 1: 3hen you have no errors select the %i:ulation icon from the left icon palette
to
go into design conte't and simulate our design.
%tep 2: Click ok hen the form appears.
:o you are in the "esign conte't and need to setup the analysis type$ plots and
load in the %ldo models
%tep ):
&elect the %etup .nal2sis icon. This ill open a form for you to select the analysis
type.
There are various types of analysis that can be performed ith this simulator$ as
shon in the form.
&elect ransient folloed by selecting the %etup button.
*et the %top i:e A%"#B be 766n and "/ the to forms.
%tep *: :o select the I' and "= terminals by holding don the left mouse button
and
draing a bo' around the terminals hile pressing %hi4t. This ill cause the ires
to be highlighted.
%tep -: 3hile the I: and -4T nets are selected press on the %etup "utputs icon
from
the Icon 1alette. This dialog bo' ill appear. &elect %elected Co:ponents tab
make sure the #lot Ite:sAsB is selected$ and click "/.
%tep 6: #nother indo ill appear asking about the plot type$ select Individuall2
then
"/.
%tep 3: Create a netlist by selecting 'etlist in the ,(ecute section or &imulation >
Create
:etlist . This ill open a 'term indo. 1ress 5eturn to close the 'term indo.
:etlist and run makes the netlist of the design you have made. #nd then it
does the simulation.
%tep 8: +ie the netlist by selecting! .%CII 4iles & 6iew 'etlist in the 5esults
session or
+ie > :etlist File.
%tep 9: Close the netlist indo ?%hi4tCF12@ or right-to-left stroke and select the 5un
,+!" button under the %i:ulation &ection or select 5un icon. This ill open
another 'term.1ress 5eturn to close the &imulation 'term.
%tep10! If the simulation is done successfully then go for ;vie outputs<. .ere you
can check the outputs aveform.
%tep 11:Close %Aave and "#5IC.
Creating a +a2outA%che:atic !riven +a2out %!+B
%tep 1: To create a layout cell vie select the inverter cell and click on File & 'ew &
6iew from the menu bar. # indo ill pop-up asking for the cell vie type.
Choose +a2out as vie type$ the vie name ill be named automatically *ayout.
%tep 2: 2y pressing :e't a ne indo ill appear asking you for the Connectivity
&ource. select &chematic to open IC&tation in the &"* mode.
%tep ): 2y 1ressing Finish this ill open IC&tation.
Creating %!+ using Icstation
%tep 1: 1lacing the devices. :o there are to ays of placing the devices in
the layouts
AaB Manual pick B 1lace!Click on pick B place icon. It ill ask for placement of
pmos in log area and the layout ill appear in the layout indo. click on the
layout indo for placing the pmos. Then it ill sho the layout of nmos hich
should be placed in similar manner
?b@#uto pick B place! 1ress on the .uto #ick @ #lace icon from the Icon 2ar.
The tool ill place the devices one by one.
=ou have no instantiated the pmos and nmos and the connectivity is
maintained as illustrated by the fly lines. :e't you ill add ports and complete
the routing.
%tep 2: 1lacing the ports
&elect the place port icon from the icon bar.It ill sho you a pop up indo ith all
ports.
%tep ): &elect the 6!! port and select M,1 as a layer for this port. The Didth and
Eeight ill be updated automatically according to the minimum metal7 dimensions.
1ress .ppl2 to place the port. &imilarly place the remaining C ports.
Pull Down
step 3o add the su1strate contacts toelect .dd !evice icon 4ro: the
%tep *: #dd the substrate contacts. In the left side icon bar$ click on D"E icon. It shos
a pop up indo of add device as shon above. &elect the path based guard option
from
the option. It ill sho another pop up indo. &et idth to 7 and select psub and
then ;-,<
Go to layout indo and dra the substrate contact. &imilarly dra the nell contact.
The psubstrate contact has been dran over ground thereby connecting it to
ground. &imilarly nell contact has been dran over +""$ thereby connecting it to
+"".
If this is not done then set up th connection of psub ith +"".
&elect psub then Connectivity > :et > #dd to :et to set psub to Ground and the same
for nell to set it to +"".
5outing +a2out
%tep 1: &elect the *ayout indo and ma'imi0e it. This ill create a full indo
image of
the layout.
%tep 2: To start routing press on the I5oute icon in the icon bar. -nce you place the
cursor on here you ant to start routing$ it ill start guided by the fly lines. =ou
can toggle beteen the connectivity layers by pressing space-1ar.This is :anual
routing.
There is an other option of .uto routing! 4se options tools > and then click on
;Icassemble<. The routing toolbar gets added to icon bar. #lternatively it can also be
activated from +ie > toolbar.
%tep ): #dd te't labels to the ports to make them recogni0able by *+& by pressing the
hot key l or select #dd > Te't.
This is ho the layout ill look like as above.
6eri4ication o4 +a2out
:o you can verify the layout by running "(C and *+& checks. e ill run Calibre
Interactive.
5unning Cali1re Interactive !5C
%tep 1: This step involves "(C check. Go to tools > calibre > run "(C. The "(C file
is already loaded? *oaded at time of creating the project and creating the schematic@.
%tep 2: The Calibre Interactive F *+& indo ill popup. Make sure ,(port 4ro:
sche:atic viewer is selected hile the Inputs and 'etlist tabs are active as
shon.
%tep ):&elect 5un !5C.
5unning Cali1re Interactive +6%
%tep 1 &elect ools & Cali1re & 5un +6% entry from the pull don menu.
%tep 2 The Calibre Interactive F *+& indo ill popup. Make sure ,(port 4ro:
sche:atic viewer is selected hile the Inputs and 'etlist tabs are active as
shon.
%tep ):&elect 5un +6%.