WWW Eecs Ucf Edu Jinyier Courses EEE5390 Cadence Part 6 Lay

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Home > Courses > EEE5390: Full-Custom VLSI Design > Cadence Tutorial
Part 6 - Layout Creation
Cadence Tutorial
Part 1 | Part 2 | Part 3 | Part 4 | Part 5 | Part 6 | Part 7 | Part 8 | Part 9
Overview
Now that we have designed a circuit and convinced ourselves that it should work, we actually want to implement this
circuit in silicon. That requires us to create a physical layout for the circuit. This physical layout will be used to
generate the mask set used to fabricate the circuit on a silicon wafer. There are a variety ways to go from a
schematic to a physical layout. These range from full-custom hand layout where every single transistor and wire is
drawn by hand to fully-synthesized layouts which are entirely computer generated. Most designers use something in
between. In order to learn as much as possible we will do the entire design by hand. This isn't as bad as it sounds as
long as you use good hierarchical design principles.
Getting Started
We will create a new Cell View for our layout. Open the library manager, select your EEE5390 library then select
File->New->Cell View. Enter 'layout' for the cell view name and Virtuoso for the tool. Click ok.
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The virtuoso window will appear and will look similar to the one you used for drawing schematics and symbols,
however, there will be another new window, called the LSW (layer selection window.) This window lists all the
available layers for the process you have selected. It also allows you to select the current layer for drawing as well as
to choose which layers to display or to protect.
Drawing the PMOS
We will start laying out our circuit by drawing the PMOS. It is slightly more complicated than the NMOS so we'll do it
together and then you can do the NMOS on your own.
Active (Diffusion)
The first step is to draw the p-type diffusion (or active) region. This will define the source and drain regions of the
transistor and well as the width of the channel. Recall that our PMOS had a width of 1.6um. Select pactive from the
LSW, and use the rectangle tool (Create->Shape->Rectangle from the menu) to draw a rectangle that is 3.6um wide
and 1.5um high. The location is not important as we will move it around later.
You may also need the ruler tool (Tools->Create Ruler from the menu) to precisely draw the layout.
Notice that you can only move the mouse by increments of 0.15um. This is not an accident. For the current process,
AMI06, lambda is 0.3um. So 0.15 corresponds to 1/2 lambda. This increment is called the design grid or
manufacturing grid and is the minimum address size of features on your masks. So even though the smallest feature
you can draw is 0.6um or 2 lambda, you can position these features with a precision of 0.15 um.
Gate Poly
Now we will draw the gate of the transistor. Select Poly from the LSW. Draw a rectangle that is 0.6um wide and
2.7um high, centered at the same point as the active region. Wherever poly crosses active will form the channel of a
transistor.
Here's what you should have now:
Hint: To zoom in press ctrl-z, to zoom out press shift-z. Use arrow keys to move the view around.
Active Contacts
Now we will contact the active region to form the source and drain of the PMOS. Select layer 'cc' from the LSW.
Don't ask me why they named this layer 'cc' I don't know. 'cc' allows you to form a contact between active or poly and
the first metal layer, 'metal1.' Draw two rectangles that are 0.6um by 0.6um (2 lambda x 2 lambda) to form source
and drain contacts as shown:
Hint: You could have used the copy function to make the second rectangle. Highlight an object or multiple objects,
press 'c' and then point to the destination and click. Also, try out the ruler function. It's the last button of the toolbar.
Metal
Let's draw the metal layer that will contact the diffusion layer through the contacts we just drew. Select 'metal1' from
the LSW. Draw two rectangles that surround the contacts by at least 0.3um or 1 lambda. Typically they would be the
same width as the active region but they don't have to be. Draw them as shown for now:
P Select
The active layer tells the foundry where to perform ion implantation, but not what type of dopant to use. That
information is conferred through the layers 'pselect' and 'nselect' You might have thought that the name 'pactive'
implied that this was the p-diffusion region and that 'nactive' implied n-diffusion, but actually both these layers share
the same layer number and get converted to a single layer 'active'. In fact, you could have used active in place of
pactive or nactive and the result would be the same. They are just there for convenience (they help you remember
which flavor of MOS you are working with.
Select layer 'pselect' from the LSW. Draw a rectangle that surrounds the pactive by 2 lambda(0.6um) in all directions
as shown:
N-Well
The PMOS transistors must sit in an n-type diffusion well to isolate them from the p-type substrate. Select 'nwell' from
the LSW and draw a rectangle of width 7.8um and height 5.1um as shown.
You may wonder why the well is not centered with respect to the PMOS. This is where we are going to put the well
tap. The well tap allows us to contact the n-well and ensure that the pn junction formed by the active region and the
well remains reverse-biased, electrically isolating the transistor.
Well Tap
Now we are going to draw the well tap. This consists of an n-type diffusion region (nactive and nselect) and a
contact.
First we need to use the stretch command to edit one of the rectangles we already drew. hit 's' and select the edge
that you wish to stretch, then click on the destination. Move the left edge of the pselect rectangle 0.6 um to the right.
Now select 'nselect' from the LSW and draw a rectangle that abuts the 'pselect' with a width of 2.1um and a height of
2.7um.
Select 'nactive' and draw a 1.5um square abutting the 'pactive' region.
Finally, using 'cc' draw a 0.6um square contact in the 'nactive' region. It should be a distance of 2 lambda from the
adjacent p diffusion region. Stretch the metal layer covering the left contact so that it also covers the well tap. This will
tie the well to the drain of the pmos. You just finished drawing your first transistor.
Here is what the completed PMOS with the well tap should look like.
Drawing the NMOS
I expect that you can do most of this on your own now so I'll just give you a few hints. Most of the rectangles will be the
same size for the nmos as for the pmos since the design rules don't specify which type of doping they refer to.
Active (Diffusion)
This time we will use 'nactive' to draw the n-type diffusion region, although, recall that you could also just use 'active.'
Make the active region for the nmos the same size as the pmos you alread drew. Again we are going to draw a fet
that is the minimum allowable size.
Gate Poly
Draw the gate poly as before.
Active Contacts
Place the contacts using 'cc'
Metal
Draw the metal1 layer surrounding the contacts.
N Select
Draw the n-select region to assign n-type doping to the active region.
Substrate Tap
In the case of the nmos we don't need to draw a well because the substrate is already p-type so the device is already
isolated by a pn junction as long as this junction remains reverse-biased. We can ensure this by drawing a substrate
tap to tie the substrate to ground. Draw the substrate tap just like the well tap, substituting 'pactive' for 'nactive' and
'pselect' for 'nselect.' Stretch the metal contact from the source to cover the substrate tap contact.
Here is what your nmos should look like.
Wiring up the Inverter
Now that we have drawn our transistors, we will want to connect them together to make the inverter.
First of all you will want to position your transistors properly. Select the entire nmos transistor and drag it below the
pmos so that the gates are aligned horizontally and there is a gap of 1.2um between the nwell of the pmos and the
pselect of the nmos. This is shown here:
Drawing Connections
First we will connect the outputs of the transistors to form the output net of the inverter circuit. Select 'metal1' from the
LSW and draw a rectangle that connects the right contact of the pmos to the right contact of the nmos. Its alright if
these rectangles overlap since they will be joined when the file gets converted to the mask set. If you want you can
join them now by selecting them and using the 'merge' command or pressing shift-m. Sometimes this helps your
layouts to look less cluttered. Only objects on the same layer will be merged.
While we have the metal1 layer selected lets draw the power rails. Draw a rectangle that is 3 lambda tall and the
entire width of the both select regions (6.2um), spaced 3 lambda above the pmos active region. Repeat this below
the nmos active region. These will be the supply rails for the circuit. Now connect these to the source/drain contacts
of the transistors as shown here.
Note that we drew our supply rails the minimul allowable width (3 lambda.) This is not ususally advisable since these
wires generally carry a lot of current. However, in this exercise we are trying to draw the smallest allowable inverter
circuit, not necessarily one that will perform well for any given application. You will have to decide how wide you need
to make your power rails when you draw the gates for your own project.
Now we will connect the gates and make a poly-metal1 contact to form the input of the circuit. Select 'poly' and
connect the gates of the two transistors. Now we want to draw a square that is 4 lambda, abutting the connected
gates. Place a 'cc' contact (2x2 lambda) in the center of this square. Finally draw a 'metal1' square covering the
contact (4x4 lambda). Heres what you get:
Creating Pins
Now we need to add pins to get signals into and out of our circuit. Select 'metal1' from the LSW. Now select Create-
>Pin from the menu in Virtuoso. The create pin dialog box will open. We want to give out pins the same names we
gave them in the other cell views (vdd, vss, in, out) so that they all match. First do vdd. Type in the pin name, keep the
type as inputoutput. Select the Display Pin Name option so that pin names will be showed in the layout view. Click ok
and draw a rectangle overlapping the high supply rail as shown below. Repeat for the other pins.
You are now finished with the layout for your inverter.
Design Rules Check
Before we proceed, we want to make sure we haven't made any errors in our layout. We will use the design rules
checker (DRC) to ensure that we haven't violated any of the MOSIS design rules. This doesn't guarantee that the
circuit will work properly; it only guarantees that the foundry can fabricate it as drawn.
Before running DRC, go back to your PuTTY window and do the following:
cd ~/ncsu-cdk-1.6.0.beta/lib/NCSU_TechLib_ami06
rm divaDRC.rul
ln -s ~/ncsu-cdk-1.6.0.beta/techfile/divaDRC.rul divaDRC.rul
rm divaEXT.rul
ln -s ~/ncsu-cdk-1.6.0.beta/techfile/divaEXT.rul divaEXT.rul
rm divaLVS.rul
ln -s ~/ncsu-cdk-1.6.0.beta/techfile/divaLVS.rul divaLVS.rul
Select Verify->DRC
The default options should work just fine. Click OK and the DRC will run. Check the CIW for the results. If there are no
errors it will read
********* Summary of rule violations for cell "test layout" *********
Total errors found: 0
otherwise there will be a list of errors like this one:
4 (SCMOS Rule 6.5.b) active contact to active spacing: 1.50 um
The rule number will be listed along with a description, which is very helpful when troubleshooting. You can go to the
Mosis rules website to get the details of the rule in question.
You are done with this section.
This website is created and maintained by Prof. Yier Jin. Please contact Yier Jin if you have any questions
concerning the materials on the website and all other general questions.

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