Tpel 2013 2294425

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10.1109/TPEL.2013.2294425, IEEE Transactions on Power Electronics
1
Control of Inverters via a Virtual Capacitor to
Achieve Capacitive Output Impedance
Qing-Chang Zhong, Senior Member, IEEE, and Yu Zeng
Abstract
Mainstream inverters have inductive output impedance at low frequencies (such inverters are called L-inverters). In this paper,
a control strategy is proposed to make the output impedance of an inverter capacitive at low frequencies (such inverters are called
C-inverters). The proposed control strategy involves the feedback of the inductor current through an integrator, which is actually
the impedance of a virtual capacitor. The gain of the integrator or the virtual capacitance is rstly selected to guarantee the stability
of the current feedback loop and then optimised to minimise the total harmonic distortion (THD) of the output voltage. Moreover,
some guidelines are developed to facilitate the selection of the lter components for C-inverters. Simulation and experimental
results are provided to demonstrate the feasibility and excellent performance of C-inverters, with the lter parameters of the test
rig selected according to the guidelines developed. It is shown that, with the same hardware, the lowest voltage THD is obtained
when the inverter is designed to be a C-inverter. A by-product of this study is that, as long as the current ripples are kept within
the desired range, the lter inductor should be chosen as small as possible in order to reduce voltage harmonics. This helps reduce
the size, weight and volume of the inductor and improve the power density of the inverter.
Index Terms
Power quality, total harmonic distortion (THD), inverters with capacitive output impedance (C-inverters), inverters with
inductive output impedance (L-inverters), inverters with resistive output impedance (R-inverters)
I. INTRODUCTION
Energy and sustainability are now on the top agenda of many governments. Smart grids have become one of the main
enablers to address energy and sustainability issues. Renewable energy, distributed generation, hybrid electrical vehicles, more-
electric aircraft, all-electric ships, smart grids etc. will become more and more popular. DC/AC converters, also called inverters,
play a common role in these applications to convert a DC source into an AC source. Arguably, the integration of renewable
and distributed energy sources, energy storage and demand-side resources into smart grids is the largest new frontier for
smart grid advancements [1], [2]. Inverters are also widely used in uninterruptible power supplies (UPS), induction heating,
high-voltage DC (HVDC) transmission, variable-frequency drives, electric vehicle (EV) drives, air conditioning, vehicle-to-grid
Some preliminary results were presented at the 37th Annual Conference of the IEEE Industrial Electronics Society (IECON), Melbourne, Australia, November
2011.
Qing-Chang Zhong and Yu Zeng are with the Dept. of Automatic Control and Systems Engineering, The University of Shefeld, Shefeld,
S1 3JD, UK, email: Q.Zhong@Shefeld.ac.uk; yu.zeng@shefeld.ac.uk, tel: +44-114 22 25630, fax: +44-114 22 25683.
The nancial support from the EPSRC, UK under Grant No. EP/J001333/1 and EP/J01558X/1 is greatly appreciated.
Copyright (c) 2013 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
2
(V2G) etc. and, hence, have become a common key device for many energy-related applications. How to control inverters is
critical for these applications.
There are several important control problems associated with inverters. For example, how to make sure that the total harmonic
distortion (THD) of the inverter voltage remains within certain range when the loads are nonlinear and the grid voltage, if
present, is distorted; how to make sure that the output voltage of an inverter is maintained within a certain range; how to
share loads proportionally according to their power ratings when inverters are operated in parallel; how to make sure that
inverters can be operated in the grid-connected mode and the standalone mode and how to minimise the transient dynamics
when the operation mode is changed [3]; how to connect inverters to the grid in a grid-friendly manner so that the impact on
the grid is minimised [4], [5]; how to minimizing the total microgrid operating cost [6], etc. There have been a lot of research
activities on these problems, from one aspect to another, and a systematic treatment of the control problems related to inverters
in renewable energy and smart grid integration can be found in [1].
The voltage THD can be improved by using deadbeat or hysteresis controllers [7], [8], selective harmonic elimination
pulsewidth modulation strategies [9], and repetitive controllers [10][16] [17], [18], injecting harmonic voltages [19], [20],
introducing a voltage feedback loop [21] etc. Another way is to investigate the role of the output impedance as it is known
that the output lter also contributes to the output voltage quality [22][25]. It is well known that mainstream inverters have
inductive output impedance at low frequencies because of the lter inductor. Moreover, the output impedance of an inverter
can also change with the control strategy adopted [26][30]. The general understanding is that inverters with resistive output
impedance are better than inverters with inductive output impedance because resistive output impedance makes the compensation
of harmonics easier. Some questions pop up immediately. For example, 1) Is it possible to have inverters with capacitive output
impedance? 2) If so, what are the advantages, if any? 3) If so, how to achieve parallel operation for such inverters? The
preliminary results presented in [31] have shown that an inverter can be designed to have capacitive output impedance. This
concept has been further developed in [32] to implement active capacitors that are accurate and stable with respect to the
change of environmental factors, e.g., temperature and humidity. In order to facilitate the presentation, inverters with inductive,
resistive and capacitive output impedance are called L-, R- and C-inverters, respectively.
In this paper, a simple but effective control strategy is proposed to design the output impedance of an inverter to be
capacitive, following [1], [31]. Then, the control parameter (i.e. the output capacitance) is designed to guarantee the stability
and, furthermore, optimised to minimise the THD of the output voltage. Moreover, detailed analyses are carried out to provide
guidelines for selecting the lter components for C-inverters. Note that the typically-needed voltage loop to track a voltage
reference [26], [27], [33] is not adopted, which reduces the number of control parameters and the complexity of the controller.
Experimental results are presented to demonstrate the feasibility and performance of C-inverters and the guidelines for the
component selection. It is shown that, with the same hardware, the lowest voltage THD is obtained when the inverter is
designed to be a C-inverter.
Note that the output impedance of an inverter can be dened at different terminals that have different pairs of voltage and
current and hence can be different. In this paper, the output impedance of an inverter is dened at the terminal with the output
voltage and the lter inductor current. In order to avoid confusion, the output impedance that takes into account the effect of
3
the lter capacitor and the control strategy is called the overall output impedance. At low frequencies, for which the major
voltage harmonics are concerned, the overall output impedance is more or less the same as the output impedance without
considering the lter capacitor.
The rest of the paper is organised as follows. A controller is proposed in Section II to force the output impedance of an
inverter to be capacitive and the stability is analysed. The control parameter is optimised to minimise the voltage THD in
Section III and guidelines for selecting the lter components are provided in Section IV. Experimental and simulation results
are presented in Section V and VI, followed by conclusions and discussions made in Section VII.

v
o

PWM
i o i
L
IGBT
H-bridge
u
C
CB
+
-
V
DC

u
f
AC bus

(a) Descriptive circuit

~
E

o
Z
jQ P S + =

o
0
o
V
(
r
v )
(
o
v )
i

(b) Simplied model with terminal voltage v
o
and terminal current i
Figure 1. Single-phase inverter
II. DESIGN OF C-INVERTERS
A. Implementation
Figure 1(a) shows an inverter, which consists of a single-phase H-bridge inverter powered by a DC source, and an LC lter.
The control signal u is converted to a PWM signal to drive the H-bridge so that the average of u
f
over a switching period is
the same as u, i.e. u u
f
. Different PWM techniques and the associated switching effect play an important role in inverter
design [34][36] but from the control point of view the PWM block and the H-bridge can be ignored when designing the
controller; see e.g. [37][40]. In particular, this is true when the switching frequency is high enough. The inverter can be
modelled as shown in Figure 1(b) as the series connection of a voltage reference v
r
and the output impedance Z
o
, taking the
voltage v
o
as the output voltage and the current i as the output current. This is equivalent to regarding the lter capacitor as
a part of the load [37]. The output impedance Z
o
is inductive when no controller is adopted and can be made resistive after
introducing the proportional feedback of the lter inductor current, which is often used to dampen oscillations in the system.
Here, the controller shown in Figure 2 is proposed to make the output impedance of an inverter capacitive.
4

o
sC
1

-
u
i
v
r

Figure 2. Controller to make the output impedance of an inverter capacitive
The following two equations hold for the closed-loop system consisting of Figure 1(a) and Figure 2:
u = v
r
1
sC
o
i, and u
f
= (R +sL)i +v
o
, (1)
where R is the equivalent series resistance (ESR) of the inductor. It is normally small but not exactly 0. Since the average of
u
f
over a switching period is the same as u, there is (approximately)
v
r
1
sC
o
i = (R +sL)i +v
o
, (2)
which leads to
v
o
= v
r
Z
o
(s) i, (3)
with the output impedance Z
o
(s) given by
Z
o
(s) = R +sL +
1
sC
o
. (4)
As a result, the integrator block
1
sCo
is added virtually to the original output impedance of the inverter. This is equivalent to
connecting a virtual capacitor C
o
(inside the inverter) in series with the lter inductor L. It is worth noting that the original
lter capacitor C is still required. Although the virtual capacitance introduced by the feedback changes the output impedance
within the bandwidth of the controller, the switching noises are often far beyond the reach of this control and an LC lter is
still needed to suppress switching noises. The impact of the control strategy is on the change of the inverter dynamics, with
some practical implications discussed in the rest of this section.
If the capacitor C
o
is chosen small enough, the effect of the inductor (R+sL) is not signicant and the output impedance
can be made nearly purely capacitive around the fundamental frequency, i.e., roughly
Z
o
(s)
1
sC
o
. (5)
Hence, the virtual capacitor C
o
resonates with the lter inductor L at a frequency higher than the fundamental frequency,
which is able to reduce the harmonic voltage dropped on the lter inductor caused by the harmonic components of the load
current. This allows C-inverters to achieve better voltage quality than R- and L- inverters without additional hardware cost.
5
B. Stability of the current loop
When the controller is implemented digitally, the effect of computation and PWM conversion can be approximated by a
one-step delay e
sTs
, where T
s
is the sampling period. Hence, the approximate block diagram of the current loop can be
derived as shown in Figure 3(a). The corresponding open-loop transfer function is
L(s) =
1
sC
o
1
sL +R
e
sTs
, (6)
which has a pole at s = 0 but does not have any unstable poles in the right-half-plane of the s-domain. A typical Nyquist plot
of such systems is shown in Figure 3(b). In order to make sure that the system is stable, according to the well-known Nyquist
theorem, the plot should not encircle the critical point (1, 0). Assume that the plot crosses the real axis for the rst time at
the frequency
0
, then
0
satises
2
atan
0
L
R

0
T
s
= . (7)
In other words,
0
can be found as the rst positive number from 0 that satises
R
0
L
= tan(
0
T
s
). (8)
At this frequency, the loop gain
1
0Co
2
0
L
2
+R
2
should be less than 1. In other words, the loop is stable if
1
C
o
<
0
2
0
L
2
+R
2
. (9)
It can be easily seen that
0 <
0
<

2T
s
. (10)
Hence, the current loop is stable if
1
C
o
<

2T
s
(
L
2T
s
)
2
+R
2
, (11)
of which the right-hand side is about (

2Ts
)
2
L for small R 0. In other words, the loop is stable if the capacitance C
o
or the
sampling frequency f
s
=
1
Ts
is chosen large enough so that the sampling frequency f
s
is larger than four times the resonant
frequency
1
2
LCo
with L, which can be easily met without any problem. Note that R is not exactly zero in reality, which
helps maintain the stability of the loop.
C. DC offset in the system
Because of the presence of the integrator
1
sCo
, any DC offset in the current i, e.g. that caused by the conversion process
or faults in the system etc., would lead to a DC offset in the output voltage. In order to avoid this problem, some simple
mechanisms can be adopted. For example, the integrator
1
sCo
can be reset when the inductor current passes zero if the offset
exceeds a given level. Alternatively, the integrator
1
sCo
can be slightly modied as
1
sCo+
with a negligible positive number
0. This is equivalent to putting a large resistor
1
in parallel with C
o
, which does not change the performance at non-DC
6

o
sC
1
-
u
i
v
r

R sL +
1
s T
s
e
v
o

-
u
f

0
0
I
m
a
g
i
n
a
r
y

A
x
i
s
Real Axis
(a) Approximate block diagram (b) Typical Nyquist plot
Figure 3. The current loop
frequencies.
III. OPTIMISATION OF THE VOLTAGE QUALITY
Assume that the output current of the inverter is
i =
h=1
I
h
sin(ht +
h
), (12)
where is the system frequency. Then the amplitude of the h-th harmonic voltage dropped on the output impedance is
2I
h
|Z
o
(jh)|. Moreover, assume that the voltage reference v
r
is clean and sinusoidal and is described as
v
r
=
2E sin(t +). (13)

Then the fundamental component of the output voltage is
v
1
=
2E sin(t +)
2I
1
|Z
o
(j)| sin(t +
1
+) (14)
=
2V
1
sin(t +) (15)
with
V
1
=
E
2
+I
2
1
|Z
o
(j)|
2
2EI
1
|Z
o
(j)| cos(
1
+ ), (16)
= arctan(
|Z
o
(j)| sin(
1
+ )
I
1
|Z
o
(j)| cos(
1
+ ) E
). (17)
The sum of all harmonic components in the output voltage is
v
H
=
h=2
I
h
|Z
o
(jh)| sin(ht +
h
+Z
o
(jh)). (18)
It is clear that v
1
and v
H
do not affect each other. v
1
is determined by the clean reference voltage, the fundamental current
and the output impedance at the fundamental frequency. v
H
is determined by the harmonic current components and the output
impedance at the harmonic frequencies.
7
According to the denition of THD, the THD of the output voltage is
THD =
h=2
I
2
h
|Z
o
(jh)|
2
V
1
100%. (19)
Hence, the THD is mainly affected by the output impedance at harmonic frequencies. As a result, it is feasible to optimise
the design of the output impedance at harmonic frequencies to minimise the THD of the output voltage.
For the C-inverter designed in the previous section, according to (4), there is
|Z
o
(jh
)|
2
= R
2
+ (h
L
1
h
C
o
)
2
, (20)
where
is the rated angular system frequency. In order to minimise the THD of the output voltage, the virtual capacitor C
o
should be chosen to minimise
h=2
I
2
h
|Z
o
(jh
)|
2
(21)
because the fundamental component V
1
can be assumed to be almost constant. This is equivalent to
min
Co
h=2
i
2
1h
(h
L
1
h
C
o
)
2
, (22)
where i
1h
=
I
h
I1
is the normalised h-th harmonic current I
h
with respect to the fundamental current I
1
. Depending on the
distribution of the harmonic current components, different strategies can be obtained.
Assume that the harmonic current is negligible for the harmonics higher than the N-th order (with an odd number N). Then
C
o
can be found via solving (22). Dene
f(C
o
) =
N
h=2
i
2
1h
(h
L
1
h
C
o
)
2
. (23)
Then C
o
needs to satisfy
df(C
o
)
dC
o
= 2
N
h=2
i
2
1h
(h
L
1
h
C
o
)
1
h
C
2
o
= 0, (24)
which is equivalent to
N
h=2
i
2
1h
(L
1
(h
)
2
C
o
) = 0. (25)
Hence,
N
h=2
i
2
1h
L =
1
(
)
2
C
o
N
h=2
i
2
1h
h
2
, (26)
and the optimal capacitance can be solved as
C
o
=
1
(
)
2
L
N
h=2
i
2
1h
h
2
N
h=2
i
2
1h
, (27)
8
which is applicable for any current i with a known harmonic prole. The corresponding f(C
o
) is
f
min
(C
o
) =
N
h=2
i
2
1h
(h
L
h
N
h=2
i
2
1h
N
h=2
i
2
1h
h
2
)
2
= (
L)
2
N
h=2
i
2
1h
(h
1
h
N
h=2
i
2
1h
N
h=2
i
2
1h
h
2
)
2
. (28)
Hence, the THD of v
o
is in proportion to the inductance L of the inverter LC lter. A small L does not only reduce the cost,
size, weight and volume of the inductor but also improves the voltage quality. However, a small L leads to a high
di
dt
for the
switches and large current ripples. See the guidelines of selecting the components in the next section for details. Moreover,
since
1
Co
L, a small L leads to a small gain for the integrator, which is good for the stability of the current loop.
If the distribution of the harmonic components is not known, then it can be assumed that the even harmonics are zero, which
is normally the case, and the odd harmonics are equally distributed. As a result, the optimal C
o
can be chosen, according to
(27), as
C
o
=
1
(
)
2
L
h=3, 5, 7, ..., N
1
h
2
N
h=3, 5, 7, ..., N
1
(29)
=
1
(
)
2
L
h=3, 5, 7, ..., N
1
h
2
(N 1)/2
. (30)
This can be written as
C
o
=
1
(
)
2
L
1
(N 1)/2
(
1
3
2
+
1
5
2
+... +
1
N
2
), (31)
where (N 1)/2 is the number of terms in the summation. The corresponding f(C
o
) is
f
min
(C
o
) = (
L)
2
h=3, 5, 7, ..., N
(h
1
h
(N 1)/2
h=3, 5, 7, ..., N
1
h
2
)
2
. (32)
If a single h-th harmonic component is concerned, then the optimal C
o
is
C
o
=
1
(h
)
2
L
. (33)
This forces the impedance at the h-th harmonic frequency close to 0 and hence no voltage at this frequency is caused,
assuming R = 0. According to the stability analysis carried out in the previous section, the current loop is stable in this case
if (h
)
2
L < (

2Ts
)
2
L, or in other words if f
s
> 4hf
, where f
2
is the rated system frequency.
A. Special Case I: To minimise the 3rd and 5th harmonic components
In most cases, it is enough to consider the 3rd and 5th harmonics only. This gives the optimal capacitance
C
o
=
17
225(
)
2
L
. (34)
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9
As a result, the output impedance is
Z
o
(j) = R +j(L
1
C
o
) (35)
= R +j
L(

225
17
). (36)
The gain factor

225
17
of the imaginary part with respect to the normalised frequency

is shown in Figure 4. It changes

from negative to positive at around

= 3.638. At the fundamental frequency, i.e., when =
, the output impedance is

Z
o
= R j
208
17

L j12.23
L. (37)
It is capacitive as expected because R is normally smaller than
L.
B. Special Case II: To minimise the 3rd harmonic component
In this case, the optimal C
o
is
C
o
=
1
(3
)
2
L
(38)
and the corresponding impedance is
Z
o
(j) = R +j(L
1
C
o
) (39)
= R +j
L(

). (40)
The gain factor


is also shown in Figure 4. It

changes from negative to positive at = 3
. At the fundamental frequency, i.e., when =

Z
o
= R j8
L j8
L, (41)
which is capacitive as well.
1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
14
12
10
8
6
4
2
0
2
4
6
/
*
T
h
e

g
a
i
n

f
a
c
t
o
r
Original inductor
3rd and 5th
3rd only
5th only
Figure 4. The gain factors to meet different criteria
10
C. Special Case III: To minimise the 5th harmonic component
In this case, the optimal C
o
is
C
o
=
1
(5
)
2
L
(42)
and the corresponding impedance is
Z
o
(j) = R +j(L
1
C
o
) (43)
= R +j
L(

25
). (44)
The gain factor

25

is also shown in Figure 4. It

changes from negative to positive at = 5
. At the fundamental frequency, i.e., when =

Z
o
= R j24
L j24
L. (45)
This is capacitive as well.
IV. COMPONENT SELECTION
A. Selection of the lter inductor L
As discovered in the previous section, the smaller the lter inductor, the smaller the output impedance and the better the
voltage quality. Thus, it is better to have a small output inductor than a big one. This leaves the selection of the lter inductor
to meet the requirement on the allowed current ripples only. According to [23], it is recommended that the current ripples
should satisfy
0.15
I
I
ref
0.4, (46)
with
I =
U
dc
4Lf
s
, (47)
where I is the inductor current ripple and I
ref
is the rated peak current at the fundamental frequency. Thus, the inductor
should be chosen to satisfy
5U
dc
8f
s
I
ref
L
5U
dc
3f
s
I
ref
. (48)
This could be applied to analyse the impact on the DC-bus voltage. For example, assume that L is selected to achieve the
maximum current ripple of 0.4I
ref
. Moreover, . assume that the peak of the h-th harmonic current reaches 50% of I
ref
.. Then
the voltage drop of the h-th harmonic current on the inductor is h
5U
dc
8fsI
ref
I
ref
2
=
5h
16fs
U
dc
. In other words, the maximum
increase of the required DC bus voltage is
5h
16fs
100%. For h = 5, f
s
= 10kHz and
= 100rad/sec, this is 4.9% so it is

not demanding at all and there is no need to take any special action when determining the DC bus voltage.
11
B. Selection of the lter capacitor C
The main function of the LC lter is to attenuate the harmonics generated by the PWM conversion and the H-bridge via
re-producing the control signal u, especially the harmonics around the switching frequency f
s
. When there is no load, the
transfer function between u
f
and v
o
is
H(s) =
1
s
2
LC + 1
. (49)
Indeed, the virtual capacitor C
o
does not change the role of the LC lter in suppressing the switching noises because the actual
output voltage u
f
generated by the inverter is still passed through the LC lter. The cut-off frequency f
c
can be found from
|H(j2f
c
)| =
1
|1 (2f
c
)
2
LC|
=
1
2
(50)
as
f
c
=
1
2
LC
2 + 1, (51)
which is about 1.5 times of the resonant frequency
1
2
LC
. Since it is very close to the resonant frequency, it is reasonable
to use the resonant frequency when selecting the components.
The overall output impedance Z(s) after taking into account the lter capacitor C is
Z(s) =
Z
o
(s)
1
sC
Z
o
(s) +
1
sC
=
Z
o
(s)
sCZ
o
(s) + 1
. (52)
At low frequencies, there is
Z(s) Z
o
(s) = R +sL +
1
sC
o
(53)
and at high frequencies, there is
Z(s)
1
sC
. (54)
This actually veries that the denition of the output impedance Z
o
without considering the lter capacitor C does not materially
affect the analysis at low frequencies. Dening the output impedance at the terminal with the output voltage and the lter
inductor current is simply to facilitate the presentation.
For conventional inverters, which are mainly L-inverters, Z(s) is inductive at low frequencies. Hence, the overall output
impedance Z(s) changes its type from inductive to capacitive at the resonant frequency. However, according to (52), the overall
output impedance Z(s) for the C-inverters designed above is
Z(s) =
sL +R +
1
sCo
s
2
LC +sCR +
C
Co
+ 1
. (55)
It is capacitive at both low frequencies (
1
sCo
) and high frequencies (
1
sC
). In order to better demonstrate this, the Bode plots of
the overall output impedances of typical L- and C-inverters are shown in Figure 5. The output impedance of the C-inverter is
capacitive over a wide range of both low and high frequencies and is inductive only over a small range of mid-frequencies.
There is a series resonance between L and C
o
, in addition to the parallel resonance between L and C, which is slightly changed
12
because of C
o
. The output impedance of the L-inverter is inductive for low frequencies up to the resonant frequency of the
lter and capacitive for the frequencies above.
40
20
0
20
40
60
M
a
g
n
i
t
u
d
e

(
d
B
)

10
1
10
2
10
3
10
4
10
5
10
6
90
45
0
45
90
P
h
a
s
e

(
d
e
g
)
Bode Diagram
Frequency (rad/sec)
Cinverter
Linverter
Figure 5. Overall output impedance of an L-inverter and a C-inverter after taking into account the lter capacitor C
The optimisation of the voltage quality discussed in the previous subsection is achieved via tuning the series resonance
between L and C
o
. Since the load current i
o
may include a large amount of harmonic components, especially when the load
is nonlinear, the parallel resonance between L, C and C
o
should be considered when designing the lter. According to (55),
the parallel resonant frequency f
r
can be obtained as
f
r
=
1
2
C +C
o
LCC
o
=
1
2
LC
C
C
o
+ 1. (56)
With the same L and C, the resonance frequency f
r
of C-inverters is higher than, but very close to, that of the corresponding
L-inverter or R-inverters, which is
1
2
LC
, because C
o
is often much larger than C. In order to avoid amplifying some harmonic
current components, the resonance frequency f
r
is recommended to be chosen between 10 times the line frequency
and
half of the switching frequency f
s
[23]. Hence, f
r
is often far away from the harmonics to be eliminated by designing C
o
.
Indeed, if C
o
is designed to eliminate the h-th harmonic, then according to (56), there is
f
r
=
1
2
LC
o
C
o
C
+ 1 =
h
C
o
C
+ 1. (57)
That is, the resonant frequency is
Co
C
+ 1 times the harmonic frequency h
under control. If
Co
C
+ 1 > 3, then f
r
>
3h
2
and it is over 9 times the system frequency
even for h = 3. Hence, it is recommended to select f

r
to satisfy
3h
2
f
r

1
2
f
s
, (58)
that is to select the parallel resonant frequency between three times of the harmonic frequency under control and half of the
13
switching frequency. Accordingly, it is recommended to select the lter capacitor C to satisfy
3h
2

h
C
o
C
+ 1
1
2
f
s
or, equivalently,
C
o
(
fs
h
)
2
1
C
1
8
C
o
. (59)

+
vri

s
1

*

vo
i
Ei
it+ i

Pi
ni
mi
e
K
-
E
*

RMS

s
1

+
Qi
P
o
w
e
r
C
a
l
c
u
l
a
t
i
o
n
Figure 6. The robust droop controller for C-inverters [31] to generate the voltage reference vr
V. SIMULATION RESULTS
Simulations were carried out with a single-phase inverter powered by a 350V DC voltage supply. The switching frequency
is 10kHz and the system frequency is 50Hz. The rated output voltage is 230V and the rated peak current is chosen as 40A.
Thus the rated apparent power of the inverter is 6.5 kVA. The load is a full-bridge rectier loaded with an LC lter (2.2mH,
150F) and a resistor R
L
= 30. An extra load consisting of a 200 resistor and a 22mH inductor in series is connected
at t = 2s, and disconnected at t = 9s to test the transient response of C-inverters, R-inverters and L-inverters. The inverter
reference voltage was generated by the robust droop controller proposed in [31], which is shown in Figure 6 for convenience.
As can be seen from Figure 6, at the steady state, there is
K
e
(E
V
o
) = n
i
P
i
,
where V
o
is the RMS value of the output voltage. As a result, the RMS output voltage is
V
o
= E
n
i
K
e
P
i
,
which shows that the output voltage is regulated and the voltage error could be maintained small via choosing a large K
e
.
Hence, there is no need to have an extra voltage loop to regulate the instantaneous output voltage. The parameters of the robust
droop controller were chosen as n
i
= 6.3 10
4
, m
i
= 3.4 10
5
and K
e
= 10, according to [31].
According to (48), the lter inductor should be chosen between 0.55mH and 1.46mH. To make the output voltage THD
small, the inductor is chosen as 0.55mH. The virtual capacitor C
o
is chosen to be 1400F to reduce the 3rd and 5th harmonics.
14
0 1 2 3 4 5 6 7 8 9 10
0
500
1000
1500
2000
2500
P

[
W
]
Time [s]
1.9 2 2.1 2.2
1700
1950
2200
0 1 2 3 4 5 6 7 8 9 10
0
500
1000
1500
2000
2500
P

[
W
]
Time [s]
1.9 2 2.1 2.2
1700
1950
2200
0 1 2 3 4 5 6 7 8 9 10
0
500
1000
1500
2000
2500
P

[
W
]
Time [s]
1.9 2 2.1 2.2
1700
1950
2200
(a) Active power
0 1 2 3 4 5 6 7 8 9 10
1500
1200
900
600
300
0
Q

[
V
a
r
]
Time [s]
0 1 2 3 4 5 6 7 8 9 10
1500
1200
900
600
300
0
Q

[
V
a
r
]
Time [s]
0 1 2 3 4 5 6 7 8 9 10
1500
1200
900
600
300
0
Q

[
V
a
r
]
Time [s]
(b) Reactive power
0 1 2 3 4 5 6 7 8 9 10
49.98
49.99
50
50.01
50.02
F
r
e
q
u
e
n
c
y

[
H
z
]
Time [s]
0 1 2 3 4 5 6 7 8 9 10
49.98
49.99
50
50.01
50.02
F
r
e
q
u
e
n
c
y

[
H
z
]
Time [s]
0 1 2 3 4 5 6 7 8 9 10
49.98
49.99
50
50.01
50.02
F
r
e
q
u
e
n
c
y

[
H
z
]
Time [s]
(c) Frequency
0 1 2 3 4 5 6 7 8 9 10
0
50
100
150
200
250
V
o

[
V
]
Time [s]
0 1 2 3 4 5 6 7 8 9 10
0
50
100
150
200
250
V
o

[
V
]
Time [s]
0 1 2 3 4 5 6 7 8 9 10
0
50
100
150
200
250
V
o

[
V
]
Time [s]
(d) Output Voltage RMS Vo
1.98 2 2.02 2.04 2.06 2.08 2.1
400
200
0
200
400
v
o

[
V
]
Time [s]
1.98 2 2.02 2.04 2.06 2.08 2.1
400
200
0
200
400
v
o

[
V
]
Time [s]
1.98 2 2.02 2.04 2.06 2.08 2.1
400
200
0
200
400
v
o

[
V
]
Time [s]
(e) Output Voltage vo
0 1 2 3 4 5 6 7 8 9 10
0
2
4
6
8
10
T
H
D

o
f

v
o

(
%
)
Time [s]
0 1 2 3 4 5 6 7 8 9 10
0
2
4
6
8
10
T
H
D

o
f

v
o

(
%
)
Time [s]
0 1 2 3 4 5 6 7 8 9 10
0
2
4
6
8
10
T
H
D

o
f

v
o

(
%
)
Time [s]
(f) THD of output Voltage vo
1.98 2 2.02 2.04 2.06 2.08 2.1
40
20
0
20
40
C
u
r
r
e
n
t

[
A
]
Time [s]
1.98 2 2.02 2.04 2.06 2.08 2.1
40
20
0
20
40
C
u
r
r
e
n
t

[
A
]
Time [s]
1.98 2 2.02 2.04 2.06 2.08 2.1
40
20
0
20
40
C
u
r
r
e
n
t

[
A
]
Time [s]
(g) Inductor current i
Figure 7. Simulation results with the extra load consisting of a 200 resistor and a 22mH inductor in series connected at t = 2s and disconnected at t = 9s:
C-inverter with Co = 1400F to reduce the 3rd and the 5th harmonics (left column), R-inverter with Ki = 4 (middle column) and L-inverter (right
column)
According to (59), the lter capacitor C should satisfy
1.84F C 174F, (60)
from which the lter capacitor was selected as C = 20F.
The simulation results of the C-inverter, together with those of an L-inverter and a R-inverter with K
i
= 4, are shown in
Figure 7. The C-inverter achieves lowest output voltage THD among the three types of inverters. When the extra load of a
200 resistor and a 22mH inductor in series is connected or disconnected, all the three type of inverter are able to respond
fast and reach the steady state quickly and smoothly. It can be seen that the transient response of the C-inverter is better than
15
the other two.
VI. EXPERIMENTAL VALIDATION
Experiments were carried out with a single-phase inverter powered by a 180V DC voltage supply, which was obtained from
a non-regulated diode rectier. The switching frequency and the system frequency are the same with the ones used in the
simulation, respectively. The rated output voltage is 110V and the rated peak current is 8A. The load is a full-bridge rectier
loaded with an LC lter (2.2mH, 150F) and a resistor R
L
= 200. The inverter reference voltage was also generated
by the robust droop controller [31] shown in Figure 6 , and the parameters of the robust droop controller were chosen as
n
i
= 3.4 10
3
, m
i
= 3.9 10
4
and K
e
= 10.
According to (48), the lter inductor should be chosen between 1.41mH and 3.75mH. The inductor 2.2mH on board on-board
the inverter falls into this range. Three different cases with the virtual capacitor C
o
chosen to reduce the 3rd harmonic, the
5th harmonic, and both the 3rd and the 5th harmonics, respectively, were tested. The corresponding virtual capacitance C
o
is
512F, 184F and 348F, respectively. According to (59), the lter capacitor C should satisfy
0.46F C 23F. (61)
The lter capacitor C = 10F on-board the inverter falls into this range. The corresponding resonant frequency is 1131Hz
for the case with h = 5 and 1083Hz for the case with h = 3, which leaves enough room for a normal switching frequency,
e.g. 5kHz.
The experimental results are shown in Figure 8, together with those from an R-inverter with Z
o
= 4 and an L-inverter
designed according to the current feedback controller proposed in [37] with K
i
= 4 and K
i
= 0, respectively, for comparison.
When the inverter was designed to have capacitive output impedance to reduce the effect of the 3rd and the 5th harmonics, the
3rd harmonic was reduced by about 50% from the case of the L-inverter and by about 65% from the case of the R-inverter,
and the 5th harmonic was reduced by about 30% and 18%, respectively. The THD was reduced by about 40% and 50%,
respectively. When the inverter was designed to have capacitive output impedance to minimise the effect of the 3rd harmonic,
the 3rd harmonic was reduced by 63% from the case of the L-inverter and by 74% from the case of the R-inverter, respectively.
The THD was reduced by about 36% and by 47%, respectively .When the inverter was designed to have capacitive output
impedance to minimise the effect of the 5th harmonic, the 5th harmonic was reduced by 41% from the case of the L-inverter and
by 31% from the case of the R-inverter, respectively. The THD was reduced by about 37% and 48%, respectively. Apparently,
C-inverters performed much better than the R- and L-inverters. Moreover, the THD is the lowest when C
o
is designed to
optimise the 3rd and 5th harmonics than to optimise these two separately. This is because the major harmonic components of
the load current are the 3rd and the 5th harmonics, as can be seen from Figure 8(e).
The recorded average RMS values of the output voltage are 109.7V for the R-inverter, 110.2V for the L-inverter and 109.8V
for the C-inverters, which shows the excellent voltage regulation capability of the robust droop control strategy. This is true
regardless of the virtual capacitance concept.
16
VII. CONCLUSIONS AND DISCUSSIONS
It has been shown that it is feasible to force the output impedance of an inverter to be capacitive over a wide range of
both low and high frequencies although it normally has an inductor connected to the inverter bridge. Such inverters are called
C-inverters. One simple but effective approach is to form an inductor current feedback through an integrator, of which the
time constant is the desired output capacitance. This is a virtual capacitor so there is no limit on the current rating and can
be applied to any power level. The capacitance can be selected to guarantee the stability of the current loop and an algorithm
is proposed to optimise the value of the output capacitance so that the THD of the output voltage is minimised. Detailed
guidelines have been provided to place the relevant frequencies properly so that the lter components can be determined.
Extensive experimental results have shown that the THD of an inverter can be reduced when it is designed to have capacitive
output impedance, with comparison to an inverter having resistive or inductive output impedance. Moreover, no visible DC
offsets are seen from the experimental results. One by-product of this study is that the lter inductor should be chosen small
in order to reduce voltage harmonics and the criterion is reduced to meet the current ripples allowed on the inductor. A small
inductor helps reduce the size, weight and volume of the passive components needed.
Since the C-inverter concept is completely new, some issues should be further investigated, in particular, for grid-connected
applications. For example, because of the introduction of a capacitor into the output impedance, a natural question is whether
this would lead to possible resonance with the rest of the system (such as the line, loads, etc.). This may not be an issue because
in exible AC transmission systems (FACTS), capacitors have been physically connected in series with transmission lines to
improve the line capacity. Another question is whether this will affect the current quality for grid-connected applications. It
has been found that C-inverters offer the lowest output voltage THD among R-, L- and C-inverters with the same hardware.
Further investigations should be carried out to explore other advantages and applications of C-inverters.
ACKNOWLEDGEMENTS
The authors are grateful to the Reviewers and Editors for their detailed comments, which have considerably improved the
quality of the paper. Yokogawa Measurement Technologies Ltd is greatly appreciated for the donation of a high-precision
wide-bandwidth power meter WT1600 and a digital 8-channel oscilloscope DL7480.
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Qing-Chang Zhong is the Chair Professor in Control and Systems Engineering at the Department of
Automatic Control and Systems Engineering, The University of Shefeld, UK. He is a Distinguished
Lecturer of IEEE Power Electronics Society and is invited to represent the UK at the European Control
Association. In 2012-2013, he spent a six-month sabbatical at the Cymer Center for Control Systems
and Dynamics (CCSD), University of California, San Diego, USA and an eight-month sabbatical at the
Center for Power Electronics Systems (CPES), Virginia Tech, Blacksburg, USA. He received his PhD
degree in control and power engineering (awarded the Best Doctoral Thesis Prize) from Imperial College
London, London, UK, in 2004, and a PhD degree in control theory and engineering from Shanghai
Jiao Tong University in 2000. He (co-)authored three research monographs: Control of Power Inverters
in Renewable Energy and Smart Grid Integration (Wiley-IEEE Press, 2013), Robust Control of Time-
Delay Systems (Springer-Verlag, 2006), Control of Integral Processes with Dead Time (Springer-Verlag,
2010). His fourth research monograph entitled Completely Autonomous Power Systems (CAPS): Next Generation Smart Grids
is scheduled to appear in 2015. He, jointly with G. Weiss, invented the synchronverter technology to operate inverters to mimic
synchronous generators, which was awarded Highly Commended at the 2009 IET Innovation Awards. He is the architect of
the next-generation smart grid and a Specialist recognised by the State Grid Corporation of China (SGCC), a Fellow of the
Institution of Engineering and Technology (IET), a Senior Member of IEEE, the Vice-Chair of IFAC TC 6.3 (Power and Energy
Systems) and was a Senior Research Fellow of the Royal Academy of Engineering/Leverhulme Trust, UK (20092010). He
serves as an Associate Editor for IEEE Transactions on Power Electronics, IEEE Access and the Conference Editorial Board
of the IEEE Control Systems Society. His research focuses on advanced control theory and its applications in various sectors,
19
including power electronics, renewable energy and smart grid integration, electric drives and electric vehicles, robust and
H-innity control, time-delay systems, process control, mechatronics.

Yu Zeng received the B.Eng. degree in automation from Central South University, Changsha, China,
in 2009. She is currently working toward the Ph.D. degree from the Department of Automatic Control
and Systems Engineering, the University of Shefeld, Shefeld, UK. Her research interests include
control of power electronic systems, microgrids and distributed generation, in particular, the parallel
operation of inverters.
20

i: [2A/div]
vo: [60V/div]
t: [8ms/div]
3 5 7 9 1113151719212325272931
0
1%
2%
3%
4%
5%
THD 3.47%
T
H
D

o
f

v
o

(
%
)
Harmonic order
(a) C-inverter with Co = 348F to reduce the 3rd and the 5th harmonics

i: [2A/div]
vo: [60V/div]
t: [8ms/div]
3 5 7 9 1113151719212325272931
0
1%
2%
3%
4%
5%
THD 3.72%
T
H
D

o
f

v
o

(
%
)
Harmonic order
(b) C-inverter with Co = 512F to reduce the 3rd harmonic

i: [2A/div]
vo: [60V/div]
t: [8ms/div]
3 5 7 9 1113151719212325272931
0
1%
2%
3%
4%
5%
THD 3.63%
T
H
D

o
f

v
o

(
%
)
Harmonic order
(c) C-inverter with Co = 184F to reduce the 5th harmonic

i: [2A/div]
vo: [60V/div]
t: [8ms/div]
3 5 7 9 1113151719212325272931
0
1%
2%
3%
4%
5%
THD 7.03%
T
H
D

o
f

v
o

(
%
)
Harmonic order
(d) R-inverter with Ki = 4

i: [2A/div]
vo: [60V/div]
t: [8ms/div]
3 5 7 9 1113151719212325272931
0
1%
2%
3%
4%
5%
THD 5.8%
T
H
D

o
f

v
o

(
%
)
Harmonic order
(e) L-inverter
Figure 8. Experimental results: output voltage vo and inductor current i (left column), harmonic distribution of vo (right column)

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2E sin(t +). (13)

of the imaginary part with respect to the normalised frequency

is shown in Figure 4. It changes

= 3.638. At the fundamental frequency, i.e., when =

, the output impedance is

of the imaginary part with respect to the normalised frequency

is also shown in Figure 4. It

. At the fundamental frequency, i.e., when =

, the output impedance is

of the imaginary part with respect to the normalised frequency

is also shown in Figure 4. It

. At the fundamental frequency, i.e., when =

, the output impedance is

= 100rad/sec, this is 4.9% so it is

even for h = 3. Hence, it is recommended to select f

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