Digital Electronics Lab Manual

KALASALINGAM UNIVERSITY
Kalasalingam Academy of Research and Educaion

Anand Nagar !rishnan!oil
"e#armen of Elecronics and $ommunicaion
Engineering
%dd semeser &'()*+'(),-
La. manual
for
"igial Elecronics La.oraory
E$E '/)
II year0III semeser0$SE
Digital Electronics Lab
KALASALINGAM UNIVERSITY
(Kalasalingam Academy of Research and Education)
Anand Nagar, Krishnankoil-626 126
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
COURSE PLAN
1. Course Name wi! Co"e Di#ia$ E$e%ro&i%s La'oraor()ECE*+1
Cre"is 2
*. Name o, !e Sa,, I&-%!ar#e
.i! !eir s/e%ia$i0aio&
!s" #"Nithya - $%N
1. Course Re2uire" or E$e%i3e %ourse Re&uired
4. Course S%!e"u$e
Le%ure ' hours()eek
Dis%ussio& *+ minutes()eek"
5. Course Assessme&
6ome .or7 $esign of sim,le digital circuits, -.ser/ation and
Record 0ork
E8am 2 !odel la.oratories and an End 1emester
2ractical E3amination
9. Gra"i&# Po$i%( A.solute 4rading 1ystem (5nternal *+6 and
E3ternal *+6)
:. Course Prere2uisies 7asic kno0ledge in conce,ts of $igital circuits
and integrated %ircuits and also de/ices related to that circuit
;. Course O'<e%i3e =
1" 8o im,art the conce,ts of digital electronics ,ractically and train students
0ith all the e&ui,ment9s 0hich 0ill hel, in im,ro/ing the .asic kno0ledge"
2" 8o analy:e and design com.inational logic and se&uential logic circuits"
+. Course Ou%ome=
1" Analy:e semiconductor digital circuits"
2" 5nter,ret .asic digital circuits"
'" 8rou.leshoot .asic digital e&ui,ment"
1>. Lesso& P$a&
To/i%
No.
To/i% Name
Num'er o,
Perio"s
Cumu$ai3e
Perio"s
C(%$e I
ECE dept, Kalasalingam University
*
1 Reali:ation of logic gates ' '
2
5m,lementation of com.inational logic
circuits
' 6
' !ulti,le3er and $e-multi,le3er ' ;
< $ecoders and Encoders ' 12
* 5terati/e circuits ' 1*
6 2arity %heckers and 4enerators ' 1=
!odel >a. 5 ' 21
C(%$e II
? 1hift Registers ' 2<
=
Ri,,le %ounters and 1ynchronous
counters
' 2?
; 1e/en 1egment $ecoder ' '+
1+ !emory $e/ices ' ''
11 Analog to digital con/erters ' '6
12 1ynchronous @inite 1tate !achine ' ';
!odel >a. 55 ' <2
11. .e' Resour%es
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>a.oratory-!anual-RE%
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1*. A""iio&a$ E8/erime&s
1" %ode %on/erters"
2" 7%$ Adders"
'" 1e&uence 4enerator"
11. Pre/are" $a'. Ma&ua$ A/aila.le 0ith instructors"
14" Porio&s ,or Mo"e$ La's
1" !odel 5 - %ycle 5
2" !odel 55 E %ycle 55
2re,ared .y Ferified .y
1
(!r 1uresh !") ($r" !" 2allikonda RaBasekaran)
A2-5(E%E Go$(E%E
DIGI T AL
ELECTRONICS
DOS

DON TS
4
1. Be regular to the lab.
1. Do not exceed the voltage Rating.
2. Follow proper Dre !ode.
2. Do not inter change the "! while
#. $aintain Silence.
doing the experi%ent.
&. 'now the theor( behind the
#. )void looe connection and hort
experi%ent be*ore co%ing to the lab.
circuit.
+. "denti*( the di**erent lead or ter%inal
&. Do not throw the connecting wire to
or pin o* the "! be*ore %a,ing
*loor.
connection.
+. Do not co%e late to the lab.
-. 'now the Biaing .oltage re/uired *or
di**erent *a%ilie o* "! and connect -. Do not operate "! trainer ,it the
power uppl( voltage and ground unnecearil(.
ter%inal to the repective pin o* the
"!.
0. Do not panic i* (ou dont get the
output.
0. 'now the !urrent and .oltage rating
o* the "! be*ore uing the% in the
experi%ent.
1. )void unnecear( tal,ing while doing
the experi%ent.
2. 3andle the "! Trainer 'it properl(.
14. $ount the "! 5roperl( on the "! 6i*
Soc,et.
11. 3andle the other e/uip%ent
properl(.
12. 7hile doing the "nter*acing8 connect
proper voltage to the inter*acing ,it.
1#. 'eep the Table clean.
1&. Ta,e a ignature o* the "n charge
be*ore ta,ing the ,it9co%ponent.
1+. )*ter the co%pletion o* the
experi%ent witch o** the power
uppl( and return the apparatu.
1-. )rrange the chair9tool and
E?.NO=1 Rea$i0aio& o, Lo#i% Gaes
5
Aim=
8o Reali:e the >ogic gates (AN$, -R, N-8, NAN$, N-R and EH--R gate
using ?<HH 5%9s"
A//araus Re2uire"=
S$.No Com/o&e& T(/e @ua&i(
1 8rainer Kit - 1
2 AN$ 4ate 5% ?<+= 1
' -R 4ate 5% ?<'2 1
< N-8 4ate 5% ?<+< 1
* NAN$ 4ate 5% ?<++ 1
6 N-R 4ate 5% ?<+2 1
? EH--R 5%?<=6 1
= %onnecting 0ires - Re&uired
T!eor(=
Lo#i% Gaes=
8he logic gate is the .asic .uilding .lock in digital systems" >ogic gates
o,erate 0ith .inary num.ers" 4ates are therefore referred to as .inary logic gates" All
/oltages used 0ith logic gates 0ill .e either G54G or >-)" A G54G /oltage 0ill mean
a .inary 1" A >-) /oltage 0ill mean a .inary +" Remem.er that logic gates are
electronic circuits" 8hese circuits 0ill res,ond only to G54G /oltages (called 1s) or
>-) (ground) /oltages (called -s)"
AND Gae=
A .asic AN$ gate consists of t0o in,uts and an out,ut" 5f the in,uts are A, 7I
H, the out,ut (often called J) is KonL only if all the in,uts A, 7IH are also Kon"L
YA A AND B AND CC AND ?
)here A, 7, I N are the in,ut /aria.les and J is the out,ut /aria.le" 8he
/aria.les are .inary, i"e" each /aria.le can assume only one of the ,ossi.le /alues, + or 1"
@or e3am,le, for an AND o,eration the gate o,ens (J C 1) only, 0hen all the in,uts are
,resent"
OR Gae=
A .asic -R gate consists of t0o in,uts and an out,ut" 5f the in,uts are A, 7IH,
the out,ut (often called J) is KonL, if one the in,uts A, 7IH is Kon"L
YA A OR B OR CC OR ? A ADBDCC DN
9
)here A, 7, I N are the in,ut /aria.les and J is the out,ut /aria.le" 8he
/aria.les are .inary, i"e" each /aria.le can assume only one of the ,ossi.le /alues, + or 1"
@or e3am,le, for an OR o,eration the gate o,ens (J C 1), 0hen one of the in,ut is
,resent"
NOT Gae=
A N-8 gate is also called an in/erter" A N-8 gate, or in/erter, is an unusual
gate" 8he N-8 gate has only one in,ut and one out,ut"
Y A NOT A. A A
8he ,rocess of in/erting is sim,le" 8he in,ut is al0ays changed to its o,,osite" 5f the
in,ut is +, the N-8 gate 0ill gi/e its com,lement, or o,,osite, 0hich is 1" 5f the in,ut to
the N-8 gate is a 1, the circuit 0ill com,lement it to gi/e a +"
NAND Gae=
NAND 4ate is a circuit 0hich ,erforms, the logic or 7oolean o,eration deri/ed
from the .asic logic o,erations NOT and AND, namely the NAND o,eration"
EEEEEEEE
Y A A B C N
$igital signals are a,,lied at the in,ut terminals A, 7, %IN" 8he out,ut is
o.tained at the out,ut terminal marked J" 8he NAND o,eration is defined as the out,ut
of an NAND gate is + if and only if all the in,uts are 1" 5t is the in/erse of the AND
o,eration" 8he NAND gate is kno0n to .e one of the Mni/ersal gates"
NOR Gae=
NOR 4ate is a circuit 0hich ,erforms, the logic or 7oolean o,eration deri/ed
from the .asic logic o,erations NOT and OR, namely the NOR o,eration"
EEEEEEEEEEE
Y A A DBD C DN
$igital signals are a,,lied at the in,ut terminals A, 7, %IN" 8he out,ut is
o.tained at the out,ut terminal marked J" 8he NOR o,eration is defined as the out,ut
of an NOR gate is 1 if and only if all the in,uts are +" 5t is the in/erse of the OR
o,eration" 8he NOR gate is kno0n to .e one of the Mni/ersal gates"
E?-OR Gae=
8he e3clusi/e--R gate is referred to as the Ka&( 'u &o a$$L gate or Fo&e or !e
o!er 'u &o 'o!F. 8he e3clusi/e--R term is often shortened to read as H-R" 8he
H-R gate is ena.led only 0hen an odd num.er of 1s a,,ear at the in,uts" 8he H-R
gate could .e referred to as an Kodd-.its check circuitL"
Y A A EX-NOR B
A A BC
:
H
Desi#&=
AND Gae=
Tru! Ta'$e=
Lo#i% Dia#ram= Pi& Dia#ram=
OR Gae=
Tru! Ta'$e=
Lo#i% Dia#ram=
INPUT OUTPUT
A B Y
+
+
1
1
+
1
+
1
+
+
+
1
INPUT OUTPUT
A B Y
+
+
1
1
+
1
+
1
+
1
1
1
;
Pi& Dia#ram=
NOT Gae=
Tru! Ta'$e=

NAND Gae=
Tru! Ta'$e=
INPUT OUTPUT
? Y
+
1
1
+
+
NOR Gae=
Tru! Ta'$e=
INPUT OUTPUT
A B Y
+
+
1
1
+
1
+
1
1
1
1
+
INPUT OUTPUT
A B Y
+
+
1
1
+
1
+
1
1
+
+
+
1>
Lo#i% "ia#ram= Pi& Dia#ram=

E?-OR Gae=
Tru! Ta'$e=

INPUT OUTPUT
A B Y
+
+
1
1
+
1
+
1
+
1
1
+
11
Pro%e"ure=
1" %onnections are made as ,er the circuit gi/en"
2" 8he >o0 le/el in,ut is grounded"
'" 8he G54G le/el in,ut is connected to the N*F su,,ly"
<" -.ser/e the out,ut /arious com.ination of in,uts"
Resu$=
1*
E?.NO=* Im/$eme&aio& o, Com'i&aio&a$
Lo#i% Cir%uis
Aim=
8o reali:e the adder and 1u.tractor using logic gates and to /erify the truth ta.le"
A//araus Re2uire"=
T!eor(=
6a$, A""er=
A com.inational circuit that ,erforms the addition of t0o .its is called a half-
adder" 8his circuit needs t0o .inary in,uts and ,roduces t0o .inary out,uts" -ne of the
in,ut /aria.les designates the augend and other designates the addend" 8he out,ut
/aria.les ,roduce the sum and the carry"
8he sim,lified 7oolean functions of the t0o out,uts can .e o.tained as .elo0
1um 1 C B A B A + C B A
%arry % C A7
)here A and 7 are the t0o in,ut /aria.les"
Tru! Ta'$e=
1 8rainer Kit - 1
2 AN$ 4ate 5% ?<+= 2
' -R 4ate 5% ?<'2 1
< EH--R 5%?<=6 2
* N-8 5% ?<+< 1
6 %onnecting 0ires - Re&uired
INPUT OUTPUT
A B SUM CARRY
+
+
1
1
+
1
+
1
+
1
1
+
+
+
+
1
11
Lo#i% E8/ressio&=
1um 1 C B A B A +
%arry % C A7
Lo#i% Dia#ram=
)
B
S : $
! ) R R ;
0 & < S 1 - )
1
2
#
0 & < S 4 1
1
2
#
Fu$$ A""er=
A com.inational circuit that ,erforms the addition of three .its is called a half-
adder" 8his circuit needs three .inary in,uts and ,roduces t0o .inary out,uts" -ne of the
in,ut /aria.les designates the augend and other designates the addend" !ostly, the third
in,ut re,resents the carry from the ,re/ious lo0er significant ,osition" 8he out,ut
/aria.les ,roduce the sum and the carry"
8he sim,lified 7oolean functions of the t0o out,uts can .e o.tained as .elo0
1um O C C B A
%arry %
out
C A7 N 7%

N %A
)here a,. P c
in
are the three in,ut /aria.les"
Tru! Ta'$e=
INPUT OUTPUT
A B C SUM CARRY
+
+
+
+
1
1
1
1
+
+
1
1
+
+
1
1
+
1
+
1
+
1
+
1
+
1
1
+
1
+
+
1
+
+
+
1
+
1
1
1
14
Lo#i% E8/ressio&=
1um 1 C C B A
%arry % C A7 N A% N 7%
Lo#i% Dia#ram=

!
)
B S : $
! ) R R ;
0 & < S 1 - )
&
+
-
0 & < S 4 1
1
2
#
0 & < S 1 - )
1
2
#
0 & < S # 2
&
+
-
0 & < S 4 1
1 4
2
1
0 & < S 4 1
&
+
-
0 & < S # 2
1
2
#
6a$, su'ra%or=
A half su.tractor is a com.inational circuit that su.tracts t0o .inary in,uts and
,roduces their difference" 5t also has an out,ut to s,ecify if a 1 has .een .orro0ed" 8he
circuit has t0o in,uts, one re,resenting the !inuend .it and the other 1u.trahend .it"
8he circuits ,roduces t0o out,uts, then difference and .orro0" 8he 7oolean functions
for the to0 out,uts can .e 0ritten as
$ C Y X Y X + 7 C Y X
Tru! Ta'$e=
15
Lo#i% E8/ressio&=
$ C Y X Y X +
7 C Y X
Lo#i% Dia#ram=
FULL SUBTRACTOR
A full su.tractor is a com.inational circuit that su.traction .et0een t0o .inary
in,uts, taking into account that a 1 may ha/e .een .orro0ed .y a lo0er significant sage"
8he circuit has three in,uts, re,resenting the minuend .it, the 1u.trahend .it and the
,re/ious .orro0 .it res,ecti/ely" 8he t0o out,uts, d and . re,resent the difference P
out,ut .orro0s" 8he 7oolean functions for the to0 out,uts can .e 0ritten as
INPUT OUTPUT
8 Y Di,,ere&%
e
Borrow
+
+
1
1
+
1
+
1
+
1
1
+
+
1
+
+
19
$ C XYZ Z Y X Z Y X YZ X + + +
7 C YZ Z X Y X + +
Tru! Ta'$e=
Lo#i% E8/ressio&=
$ C XYZ Z Y X Z Y X YZ X + + +
7 C YZ Z X Y X + +
Lo#i% Dia#ram=
INPUT OUTPUT
8 (
0
Di,,ere&%
e
Borrow
+
+
+
+
1
1
1
1
+
+
1
1
+
+
1
1
+
1
+
1
+
1
+
1
+
1
1
+
1
+
+
1
+
1
1
1
+
+
+
1
1:
Pro%e"ure=
1" 8he adder and su.tractor circuits are designed using the 7oolean function 0hich
is found out from the truth ta.les"
'" 8he >o0 le/el in,ut is 4rounded and the G54G le/el in,ut is connected to the
N*F su,,ly"
<" -.ser/e the out,ut /arious com.ination of in,uts"
Resu$=
E?.NO=1 Mu$i/$e8er a&" Demu$i/$e8er
1;
Aim=
8o reali:e the multi,le3er and demulti,le3er circuit using logic gates and to
/erify the truth ta.le"
A//araus Re2uire"=
4=1 Mu$i/$e8er=
T!eor(=
A multi,le3er or mu3 is a de/ice that ,erforms multi,le3ingQ it selects one of
many analog or digital in,ut signals and for0ards the selected in,ut into a single line" A
multi,le3er of 2
n
in,uts has n select lines, 0hich are used to select 0hich in,ut line to
send to the out,ut"
Tru! a'$e=
I&/us
Se$e% Li&es Ou/u
S
>
S
1
Y
5+
+ + 5
+
51
+ 1 5
1
52
1 + 5
2
5'
1 1 5
'
Lo#i% E8/ressio&=
= Y 1 + ' 1 + 2 1 + 1 1 + +
S S I S S I S S I S S I + + +
Lo#i% Dia#ram=
1 8rainer Kit - 1
2 AN$ 4ate( ' in,ut) 5% ?<11 '
' -R 4ate 5% ?<'2 1
< N-8 4ate 5%?<+< 1
* %onnecting 0ires - Re&uired
1+
S 4 S 1
" 4
" 1
" 2
" #
;
0 & < S 1 1
1 1
1 1 4
2
0 & < S 1 1
#
- &
+
0 & < S 4 &
#
&
1
2
0 & < S 1 1
1
1 2 2
1 #
0 & < S 1 1
1
1 2 2
1 #
0 & < S # 2
1 4
2
1
0 & < S # 2
&
+
-
0 & < S # 2
1
2
#
1=4 Demu$i/$e8er=
T!eor(=
8he de-multi,le3er ,erforms the re/erse o,eration of a multi,le3er" 5t is a
com.inational circuit 0hich acce,ts a single in,ut and distri.utes it o/er se/eral out,uts"
8he num.er of out,ut lines is Rn9 and the num.er of select lines is 2
n
lines" $e-
multi,le3er 5%s may ha/e an ena.le in,ut to control the o,eration of the unit" )hen the
ena.le in,ut is in a gi/en .inary state (the disa.le state), the out,uts are disa.led, and
0hen it is in the other state (the ena.le state), the circuit functions as normal de-
multi,le3er" 8he si:e of the de-multi,le3er is s,ecified .y the single in,ut line and the
num.er 2
n
of its out,ut lines"
Tru! a'$e=
Se$e% Li&es Ou/u
S> S1 Y1 Y* Y1 Y4
+ + 1 + + +
+ 1 + 1 + +
1 + + + 1 +
1 1 + + + 1
Lo#i% E8/ressio&=
=
+
Y 1 +
S S I
=
1
Y 1 +
S S I
=
2
Y 1 +
S S I
=
'
Y 1 +
S S I
Lo#i% Dia#ram=
*>
S 1 S 4 ""
; 1
; 2
; #
; &
0 & < S 4 &
#
&
0 & < S 4 &
1
2
0 & < S 1 1
1 1
1 1 4
2
0 & < S 1 1
#
- &
+
0 & < S 1 1
1
1 2 2
1 #
0 & < S 1 1
1
1 2 2
1 #
Pro%e"ure=
1" 8he !ulti,le3er and demulti,le3er circuit is designed and the 7oolean
function is found out"
2" 8he >o0 le/el in,ut is 4rounded and the G54G le/el in,ut is connected to
the N*F su,,ly"
'" 8he in,uts and selection lines are gi/en from the in,ut s0itches"
<" %onnections are made as ,er the circuit gi/en
*" -.ser/e the out,ut for /arious com.inations of in,uts"
RESULT=
E?.NO=4 De%o"ers a&" E&%o"ers
*1
Aim=
8o reali:e the Encoder and $ecoder circuit using logic gates and to /erify the
truth ta.le"
A//araus Re2uire"=
ENCODER=G;=1H
T!eor(=
An encoder has 2
n
(or fe0er) in,ut lines and Rn9 out,ut lines" 8he out,ut lines
generate the .inary code corres,onding to the in,ut /alue" 5n encoders, it is assumed that
only one in,ut has a /alue of 1 at any gi/en time" 8he encoders are s,ecified as m-to-n
encoders 0here m S 2
n
"
Tru! Ta'$e=
D> D1 D* D1 D4 D5 D9 D: A B C
1 + + + + + + + + + +
+ 1 + + + + + + + + 1
+ + 1 + + + + + + 1 +
+ + + 1 + + + + + 1 1
+ + + + 1 + + + 1 + +
+ + + + + 1 + + 1 + 1
+ + + + + + 1 + 1 1 +
+ + + + + + + 1 1 1 1
1 8rainer Kit - 1
2 -R 4ate 5% ?<'2 '
' AN$ gate(' in,ut) 5%?<11 2
< N-8 gate 5% ?<+< 1
**
Lo#i% Dia#ram=
B
)
!
D 4 D 1 D 2 D # D & D + D - D 0
0 & < S # 2
1 #
1 2
1 1
0 & < S # 2
1 4
2
1
0 & < S # 2
1 #
1 2
1 1
0 & < S # 2
&
+
-
0 & < S # 2
1
2
#
0 & < S # 2
1
2
#
0 & < S # 2
&
+
-
0 & < S # 2
1 4
2
1
0 & < S # 2
1
2
#
DECODER =G *=4H
T!eor(=
A decoder is a com.inational circuit that con/erts .inary information from Rn9
in,ut lines to a ma3imum of 2
n
uni&ue out,ut lines" 5t ,erforms the re/erse o,eration of
the encoder" 5f the n-.it decoded information has unused or don9t-care com.inations, the
decoder out,ut 0ill ha/e fe0er than 2
n
out,uts" 8he decoders are re,resented as n-to-m
line decoders, 0here m S 2
n
" 8heir ,ur,ose is to generate the 2
n
(or fe0er) minterms of n
in,ut /aria.les" 8he name decoder is also used in conBunction 0ith some code con/erters
such as 7%$-to-se/en-segment decoders" !ost, if not all, 5% decoders include one or
more ena.le in,uts to control the circuit o,eration" A decoder 0ith an ena.le in,ut can
function as a de-multi,le3er"
Tru! Ta'$e=
INPUTS OUTPUTS
D
IN
? Y D
>
D
1
D
*
D
1
1
1
+
+
+
1
1
+
+
1
+
+
+
+
*1
1
1
1
1
+
1
+
+
+
+
1
+
+
1
Lo#i% "ia#ram=
= ;
D " N
D 4
D 1
D 2
D #
0 & < S 1 1
1 4
1 2
1 1
0 & < S 1 1
#
- &
+
0 & < S 4 &
1
2
0 & < S 1 1
1
1 2 2
1 #
0 & < S 1 1
1
1 2 2
1 #
0 & < S 4 &
1
2
Pro%e"ure=
1" 8he Encoder and $ecoder circuit is designed and the 7oolean function is found
out"
2" 8he >o0 le/el in,ut is 4rounded and the G54G le/el in,ut is connected to the
N*F su,,ly"
'" %onnections are made as ,er the circuit gi/en"
<" -.ser/e the out,ut for /arious com.inations of in,uts"
Resu$=
*4
*5
E?.NO=5 Ierai3e Cir%uis
Aim=
8o design a magnitude com,arator using .asic logic gates and /erify the truth
ta.le"
A//araus Re2uire"=
T!eor(=
A magnitude com,arator is an e3am,le of iterati/e circuits (com.inational
circuit) that com,ares the magnitude of t0o num.ers (A,7) and generates one of the
follo0ing out,uts"
1" AC7
2" AT7
'" AU7
>et A and 7 t0o in,ut num.ers ACA1A+ and 7C717+
1" 5f A1 is greater than 71 then AT7
2" 5f A1 is less than 71 then AU.
'" 5f A1 is e&ual to 71 then 0e ha/e to check the ne3t .it"
<" 5f A+ is greater than 7+ then AT7
*" 5f A+ is less than 7+ then AU.
6" 5f A1 is e&ual to 71 then AC7"
1 8rainer Kit - 1
2 AN$ 4ate 5% ?<+= 1
' '-i(, AN$ 4ate 5% ?<11 2
< -R 4ate 5% ?<'2 1
* EH--R 5%?<=6 1
* N-8 gate 5% ?<+< 1
*9
Tru! a'$e=
5n,uts -ut,uts
A1 A+ 71 7+ AT7 AC7 AU7
+ + + + + 1 +
+ + + 1 + + 1
+ + 1 + + + 1
+ + 1 1 + + 1
+ 1 + + 1 + +
+ 1 + 1 + 1 +
+ 1 1 + + + 1
+ 1 1 1 + + 1
1 + + + 1 + +
1 + + 1 1 + +
1 + 1 + + 1 +
1 + 1 1 + + 1
1 1 + + 1 + +
1 1 + 1 1 + +
1 1 1 + 1 + +
1 1 1 1 + 1 +
E8/ressio&s=
AC7 C
) 1 1 )( + + ( B A B A
AU7 C 1 1 + 1 + + + 1 B A B B A B A A + +
AT7 C + + 1 1 1 + 1 + B A A B A B B A + +
Pro%e"ure=
1" 8he circuit is im,lemented using logic gates"
N*F su,,ly"
'" 8he logic in,uts are gi/en as ,er the truth ta.le"
<" 8he out,uts are o.ser/ed"
*" %om,are the theoretical and ,ractical and /erify the out,ut"
*:
Lo#i% "ia#ram=
) 4 ) 1 B 4 B 1
) > B
) ? B
) @ B
0 & < S 4 &
+
-
0 & < S 4 &
2
1
0 & < S 4 &
#
&
0 & < S 4 &
1
2
0 & < S 1 1
1
1 2 2
1 #
0 & < S 4 1
1 4
2
1
0 & < S 1 1
1 1
1 1 4
2
0 & < S 4 1
&
+
-
0 & < S 1 1
#
- &
+
0 & < S # 2
&
+
-
0 & < S # 2
1
2
#
0 & < S 4 1
1
2
#
0 & < S 1 1
1
1 2 2
1 #
0 & < S # 2
1 #
1 2
1 1
0 & < S # 2
1 4
2
1
0 & < S 4 &
1 # 1 2
0 & < S 4 &
1 1 1 4
0 & < S 1 - )
&
+
-
0 & < S 1 - )
1
2
#
*;
Resu$=
E?.NO.9 Pari( C!e%7ers a&" Ge&eraors
Aim=
8o im,lement the odd and e/en ,arity checkers using the logic gates and also to
generate the odd ,arity and e/en ,arity num.ers using the generators"
A//araus re2uire"=
T!eor(=
2arity checking is used for error detection in data transmission"
O"" /ari( %!e%7er
T!eor(=
5t counts the num.er of 19s in the gi/en in,ut and ,roduces a 1 in the out,ut
0hen the num.er of 19s is odd"
Lo#i% Dia#ram=
)
B
!
D
O D D 5 ) R " T ;
0 & < S 1 - )
1 4
2
1
0 & < S 1 - )
&
+
- 0 & < S 1 - )
1
2
#
E3e& /ari( %!e%7er=
T!eor(=
5t counts the num.er of 19s in the gi/en in,ut and ,roduces a 1 in the out,ut
0hen the num.er of 19s is e/en"
Lo#i% Dia#ram=
1 8rainer Kit - 1
* EH--R 5%?<=6 1
* N-8 gate 5% ?<+< 1
*+
)
B
!
D
O D D 5 ) R " T ; A . A N 5 ) R " T ;
0 & < S 1 - )
1 4
2
1
0 & < S 1 - )
&
+
- 0 & < S 1 - )
1
2
#
0 & < S 4 &
1 2
O"" /ari( #e&eraor=
T!eor(=
5t generates an odd ,arity num.er" 8he odd ,arity checker circuit is used 0ith the
in/erted out,ut and also the in,ut .its" 1o 0hen the in,ut is a <-.it num.er then the
out,ut of the generator circuit 0ill ha/e * .its 0hich is an odd ,arity num.er"
Lo#i% Dia#ram=
)
)
B
B
!
!
D
D
5 ) R " T ; B " T
0 & < S 1 - )
1 4
2
1
0 & < S 1 - )
&
+
-
0 & < S 1 - )
1
2
#
0 & < S 4 &
1 2
E3e& /ari( #e&eraor
T!eor(=
5t generates an e/en ,arity num.er" 8he e/en ,arity checker circuit is used 0ith
the in/erted out,ut and also the in,ut .its" 1o 0hen the in,ut is a <-.it num.er then the
out,ut of the generator circuit 0ill ha/e * .its 0hich is an e/en ,arity num.er"
Lo#i% Dia#ram=
)
B
B
)
!
!
D
D
5 ) R " T ; B " T
0 & < S 1 - )
1
2
#
0 & < S 1 - )
&
+
-
0 & < S 1 - )
1 4
2
1
1>
Pro%e"ure=
1" 8he circuit is im,lemented using logic gates"
2" 8he in,uts are gi/en as ,er the truth ta.le"
'" 8he corres,onding out,uts are noted"
<" 8he theoretical and ,ractical /alues 0ere /erified"
TRUT6 TABLE=
5n,ut %hecker out,ut 4enerator out,ut
A 7 % $ odd e/en odd e/en
+ + + + + 1 ++++1 +++++
+ + 1 1 + +++1+ +++11
+ + 1 + 1 + ++1++ ++1+1
+ + 1 1 + 1 ++111 ++11+
+ 1 + + 1 + +1+++ +1++1
+ 1 + 1 + 1 +1+11 +1+1+
+ 1 1 + + 1 +11+1 +11++
+ 1 1 1 1 + +111+ +1111
1 + + + 1 + 1++++ 1+++1
1 + + 1 + 1 1++11 1++1+
1 + 1 + + 1 1+1+1 1+1++
1 + 1 1 1 + 1+11+ 1+111
1 1 + + + 1 11++1 11+++
1 1 + 1 1 + 11+1+ 11+11
1 1 1 + 1 + 111++ 111+1
1 1 1 1 + 1 11111 1111+
11
Resu$=
E?.NO=: S!i, Re#isers
Aim=
8o Reali:e the 1hift Registers using 5% ?<HH 5c9s and to /erify the truth ta.le.
A//araus re2uire"
T!eor(=
I&ro"u%io&
Shift registers are a ty,e of se&uential logic circuit, mainly for storage of digital
data" 8hey are a grou, of fli,-flo,s connected in a chain so that the out,ut from one
fli,-flo, .ecomes the in,ut of the ne3t fli,-flo," !ost of the registers ,ossess no
characteristic internal se&uence of states" All the fli,-flo,s are dri/en .y a common
clock, and all are set or reset simultaneously"
5n this cha,ter, the .asic ty,es of shift registers are studied, such as 1erial 5n -
1erial -ut, 1erial 5n - 2arallel -ut, 2arallel 5n - 1erial -ut, 2arallel 5n - 2arallel -ut, and
.idirectional shift registers" A s,ecial form of counter - the shift register counter, is also
introduced"
Seria$ I& - Seria$ Ou S!i, Re#isers =
1 8rainer Kit - 1
2 $ @li, @lo, 5% ?<?< 2
' %onnecting 0ires - Re&uired
1*
A .asic four-.it shift register can .e constructed using four $ fli,-flo,s, as
sho0n .elo0" 8he o,eration of the circuit is as follo0s" 8he register is first cleared,
forcing all four out,uts to :ero" 8he in,ut data is then a,,lied se&uentially to the $
in,ut of the first fli,-flo, on the left (@@+)" $uring each clock ,ulse, one .it is
transmitted from left to right" Assume a data 0ord to .e 1++1" 8he least significant .it
of the data has to .e shifted through the register from @@+ to @@'"
Seria$ I& - Para$$e$ Ou S!i, Re#isers=
@or this kind of register, data .its are entered serially in the same manner as
discussed in the last section" 8he difference is the 0ay in 0hich the data .its are taken
out of the register" -nce the data are stored, each .it a,,ears on its res,ecti/e out,ut
line, and all .its are a/aila.le simultaneously"
Para$$e$ I& - Seria$ Ou S!i, Re#isers =
A four-.it ,arallel in - serial out shift register is sho0n .elo0" 8he circuit uses $
fli,-flo,s and NAN$ gates for entering data (i"e" 0riting) to the register $+, $1, $2 and
$' are the ,arallel in,uts, 0here $+ is the most significant .it and $' is the least
significant .it" 8o 0rite data in, the mode control line is taken to >-) and the data is
clocked in" 8he data can .e shifted 0hen the mode control line is G54G as 1G5@8 is
acti/e high" 8he register ,erforms right shift o,eration on the a,,lication of a clock
,ulse, as sho0n in .elo0"
Para$$e$ I& - Para$$e$ Ou S!i, Re#isers =
@or ,arallel in - ,arallel out shift registers, all data .its a,,ear on the ,arallel
out,uts immediately follo0ing the simultaneous entry of the data .its" 8he follo0ing
circuit is a four-.it ,arallel in - ,arallel out shift register constructed .y $ fli,-flo,s"
8he $Vs are the ,arallel in,uts and the WVs are the ,arallel out,uts" -nce the
register is clocked, all the data at the $ in,uts a,,ear at the corres,onding W out,uts
simultaneously.
Seria$ I& - Seria$ Ou S!i, Re#isers=
Tru! Ta'$e=
Lo#i% Dia#ram=
CLK PULSE FF> FF1 FF* FF1 OUTPUT
+ + + + + +
1 1 + + + +
2 + 1 + + +
' + + 1 + +
< + + + 1 1
11
Seria$ I& - Para$$e$ Ou S!i, Re#isers=
Tru! Ta'$e= i&/u se2ue&%e is 1>>1
Lo#i% Dia#ram=
Para$$e$ I& - Para$$e$ Ou S!i, Re#isers=
Tru! Ta'$e=
5N2M8 %>K -M82M8
1 1 + 1 1 1 1 + 1
Lo#i% Dia#ram=
CLK PULSE FF> FF1 FF* FF1 OUTPUT
+ + + + + +
1 1 + + + +
2 1 + + + +
' 1 + + + +
< 1 + + 1 1
14
PIN DIAGRAM =
Pro%e"ure=
1" 8he #ohnson %ounter circuit is designed and the 7oolean function is found out"
N*F su,,ly"
15
Resu$=
E?.NO=; Ri//$e a&" S(&%!ro&ous %ou&ers
Aim=
8o Reali:e the Ri,,le %ounter and synchronous counter using 5% ?<HH9s and to
/erify the truth ta.le"
A//araus re2uire"
Ri//$e Cou&er=
T!eor(=
5n a ri,,le counter, the fli,-flo, out,ut transition ser/es as a source for triggering
other fli,-flo,s" 5n other 0ords, the %lock 2ulse in,uts of all fli,-flo,s (e3ce,t the first)
are triggered not .y the incoming ,ulses, .ut rather .y the transition that occurs in other
fli,-flo,s" A .inary ri,,le counter consists of a series connection of com,lementing fli,-
flo,s (#K or 8 ty,e), 0ith the out,ut of each fli,-flo, connected to the %lock 2ulse in,ut
of the ne3t higher-order fli,-flo," 8he fli,-flo, holding the >17 recei/es the incoming
count ,ulses" All # and K in,uts are e&ual to 1" 8he small circle in the %lock 2ulse
(%ount 2ulse indicates that the fli,-flo, com,lements during a negati/e-going transition
or 0hen the out,ut to 0hich it is connected goes from 1 to +" 8he fli,-flo,s change one
at a time in ra,id succession, and the signal ,ro,agates through the counter in a ri,,le
fashion" A .inary counter 0ith re/erse count is called a .inary do0n-counter" 5n .inary
do0n-counter, the .inary count is decremented .y 1 0ith e/ery in,ut count ,ulse"
Sae Ta'$e=
I&/u Ou/u
1 8rainer Kit - 1
2 #-K, $ @li, @lo,s 5% ?<?6,5% ?<?< <,2
' %onnecting 0ires - Re&uired
19
C$7 Rese A B C D
1 1 > > > >
1 > > > > 1
1 > > > 1 >
1 > > > 1 1
1 > > 1 > >
1 > > 1 > 1
1 > > 1 1 >
1 > > 1 1 1
1 > 1 > > >
1 > 1 > > 1
1 > 1 > 1 >
1 > 1 > 1 1
1 > 1 1 > >
1 > 1 1 > 1
1 > 1 1 1 1
Lo#i% Dia#ram=
Pi& "ia#ram=
1:
Ri&# %ou&er=
T!eor(=
A ring counter is a circular shift register 0ith only one fli,-flo, .eing set at any
,articular timeQ all others are cleared" 8he single .it is shifted from one fli,-flo, tot the
other to ,roduce the se&uence of timing signals"
Lo#i% Dia#ram=
Tru! Ta'$e=
I&/u Ou/u
C$7 Rese @a @' @% @"
1 1 1 > > >
1;
1 > > 1 > >
1 > > > 1 >
1 > > > > 1
1 > 1 > > >
Io!&so& %ou&er=
T!eor(=
A #ohnson counter (or s0itch tail ring counter, t0isted-ring counter, 0alking-ring
counter, or !oe.ius counter) is a modified ring counter, 0here the out,ut from the last
stage is in/erted and fed .ack as in,ut to the first stage"
X1YX2YX'Y
A ,attern of .its e&ual in
length to t0ice the length of the shift register thus circulates indefinitely" 8hese counters
find s,ecialist a,,lications, including those similar to the decade counter, digital to
analogue con/ersion, etc"
Lo#i% Dia#ram=
Tru! Ta'$e=
I&/u Ou/u
C$7 Rese @a @' @% @"
1 1 1 + + +
1 + 1 1 + +
1 + 1 1 1 +
1 + 1 1 1 1
1 + + 1 1 1
1+
1 + + + 1 1
Pro%e"ure=
1" 8he Ri,,le counter and synchronous %ounter circuit is designed"
N*F su,,ly"
'" 8he clock 1ignal is a,,lied from the trainer kit"
<" %onnections are made as ,er the circuit gi/en"
*" -.ser/e the out,ut for /arious com.inations of in,uts"
Resu$=
E?.NO=+ Se3e& Se#me& De%o"er
Aim =
8o reali:e the o,eration of a decoder-dri/er circuit that acce,ts a .inary or 7%$
in,ut code and generates the ?-segment dis,lay signals to ,roduce the num.ers +
through ; and other characters"
A//araus Re2uire"=
T!eor(=
1 2rototy,ing 7oard(7read
7oard)
- 1
2 $% ,o0er su,,ly */ - 1
' ? 1egment >E$ dis,lay
common anode
- 1
< Resistors <?+ -hms(Z))atts ?
* 5% 5%?<<? 1
4>
$ecoder is com.inational circuit that con/erts .inary information from the n coded in,uts to a
ma3imum of 2
n
uni&ue out,uts" 8he decoder ,resented on this e3,eriment are called n-to-m line
decoder 0here mS 2
n
" 5ts ,ur,ose is to generate the 2
n
(or fe0er) minterms of n in,ut
/aria.les
8he o,eration of ?<<? decoder may .e clarified form the truth ta.le" @or each ,ossi.le in,ut
com.ination, there are se/en out,uts that are e&ual to + and only one that is e&ual to 1" 8he out,ut
/aria.le e&uals to 1 re,resents the minterm e&ui/alent of the .inary num.er that is a,,lied to the in,ut
lines"
A se/en segment dis,lay, as its name indicates, is com,osed of se/en elements" 5ndi/idually on
or off, they can .e com.ined to ,roduce sim,lified re,resentations of the ara.ic numerals" 1e/en-
segment dis,lays may use li&uid crystal dis,lay (>%$), arrays of light-emitting diodes (>E$s), and other
light-generating or controlling techni&ues such as cold cathode gas discharge, /acuum fluorescent,
incandescent filaments, and others"
A resistor is a t0o-terminal electronic com,onent that ,roduces a /oltage across
its terminals that is ,ro,ortional to the electric current through it in accordance 0ith
-hmVs la0 FC 5R" 8his is used to im,ede the flo0 of current" @our-.and identification is
the most commonly used color-coding scheme on resistors" 5t consists of four colored
.ands that are ,ainted around the .ody of the resistor" 8he first t0o .ands encode the
first t0o significant digits of the resistance /alue, the third is a ,o0er-of-ten multi,lier or
num.er-of-:eroes, and the fourth is the tolerance accuracy, or acce,ta.le error, of the
/alue"
41
8he first three .ands are e&ually s,aced along the resistorQ the s,acing to the fourth .and is
0ider" 1ometimes a fifth .and identifies the thermal coefficient, .ut this must .e distinguished from the
true *-color system, 0ith 'significant digits" Resistance is measured .y ohms ([)
:44: De%o"er Tru! Ta'$e
$ecimal
Num.er
5n,uts -ut,uts
$ % 7 A a . c d e f g
+ + + + + + + + + + + 1
1 + + + 1 1 + + 1 1 1 1
2 + + 1 + + + 1 + + 1 +
' + + 1 1 + + + + 1 1 +
< + 1 + + 1 + + 1 1 + +
* + 1 + 1 + 1 + + 1 + +
4*
6 + 1 1 + 1 1 + + + + +
? + 1 1 1 + + + 1 1 1 1
= 1 + + + + + + + + + +
; 1 + + 1 + + + 1 1 + +
Pi& Dia#ram=
Cir%ui Dia#ram=
41
Pro%e"ure=
1" %onstruct the circuit sho0n in the circuit diagram on .read.oard" !ake sure
that ,in ',<,* are all connected to the ,ositi/e line of the ,o0er su,,ly"
2" $ue to /ariety of ?-segment dis,lay a/aila.le commercially, you need to test
0hich ,ins are assigned to segment a-g" Jou could check the segment indi/idually .y
connecting the common anode ,in to the ,ositi/e terminal of the ,o0er su,,ly, and the
segment ,in connected to the one (1) <?+ ohms resistor"
'" 8est all in,ut com.ination and determine the num.er dis,lay
Resu$=
44
E?.NO=1> Memor( De3i%es
Aim =
8o store a set of data in a RA! using 5% 211< starting from location ------- to
location-------- and retrie/e the same data""
A//araus Re2uire"=
T!eor(=
1tatic random-access memory (1RA!) is a ty,e of semiconductor memory that
uses .ista.le latching circuitry to store each .it" 8he term static differentiates it from
dynamic RA! ($RA!) 0hich must .e ,eriodically refreshed" 1RA! e3hi.its data, .ut
it is still /olatile in the con/entional sense that data is e/entually lost 0hen the memory
is not ,o0ered"
Pi& Dia#ram ,or IC *114=
7oard)
- 1
2 $% ,o0er su,,ly */ - 1
' 5% 5%211< 1
< %onnecting 0ires - Re&uired
45
Address 5n,uts
A' A2 A1 A+
+ + + +
+ + + 1
+ + 1 +
+ + 1 1
$ata 5n,uts
5(-< 5(-' 5(-2 5(-1
+ + 1 +
+ 1 + +
+ 1 + 1
+ 1 1 +
Address 5n,uts
A' A2 A1 A+
+ + + +
+ + + 1
+ + 1 +
+ + 1 1
$ata -ut,uts
5(-< 5(-' 5(-2 5(-1
+ + 1 +
+ 1 + +
+ 1 + 1
+ 1 1 +
E3am,le for $ata 5n,ut-
E3am,le for $ata -ut,ut
Pro%e"ure=
1" %ircuits connections are made to the a,,ro,riate ,ins of 5% 211<
2" @irst you ha/e to 0rite the data and then read the data, for 0riting data make )E to
lo0 and %1 in,ut to lo0"
'" @or a <-.it data select any address in,ut from A+ to A;" @or e3, select A' to
A+ and connect the data in,uts( out,uts i"e", 5(-< E 5(-1
<" )rite a <-.it data of your choice in each of the re&uired address in,uts or memory
locations
*" 7y doing the a.o/e ste,s 2, ' and < the data 0ill .e stored in the memory location
6" @or reading data
a" !ake )E to high and %1 in,ut to lo0
." $isconnect the data in,uts 5(-< E 5(-1 from in,ut lines and connect
them to out,ut lines to read the data
c" 4i/e the address in,uts of the data you ha/e stored and o.ser/e the
out,uts through 5(-< E 5(-1"
Resu$=
49
E?.NO=11 A&a$o# o Di#ia$ Co&3erers
Aim =
8o rig u, circuit to con/ert an analog /oltage to its digital e&ui/alent
A//araus Re2uire"=
T!eor(=
A @lash A$% (also kno0n as a $irect con/ersion A$%) is a ty,e of analog-to-
digital con/erter that uses a linear /oltage ladder 0ith a com,arator at each \rung\ of the
ladder to com,are the in,ut /oltage to successi/e reference /oltages" -ften these
reference ladders are constructed of many resistorsQ ho0e/er modern im,lementations
sho0 that ca,aciti/e /oltage di/ision is also ,ossi.le" 8he out,ut of these com,arators is
generally fed into a digital encoder 0hich con/erts the in,uts into a .inary /alue"
7oard)
- 1
2 $% ,o0er su,,ly */ - 1
' 5% 5% >! '2<,5% ?<++ 1,1
< Resistors 1+k,1++k <,1
* !ultimeter - 1
4:
Cir%ui Dia#ram=
4;
PROCEDURE=
1" %onnect the circuit as ,er the circuit diagram"
2" Ferify the digital -(2 for different analog /oltages"
Noe= (1)" %onnect FN (,in <) terminal of the -2A!2 to N*F
(2)" %onnect F- (,in 11) terminal of the -2A!2 to ground
Desi#&= Num.er of com,arators re&uired C 2n-1
)here n C desired num.er of .its
%1, %2 P %' C %om,arator o(,
$+ P $1 C Encoder (%oding net0ork) -(2
Resu$=
4+
E?.NO=1* S(&%!ro&ous Fi&ie Sae Ma%!i&e
Aim =
8o understanding !ealy and !oore machine analysis of a se&uence detector and
com,are the results"
A//araus Re2uire"=
T!eor(=
A se&uence detector acce,ts as in,ut a string of .its either + or 1" 5ts out,ut
goes to 1 0hen a target se&uence has .een detected" 8here are t0o .asic ty,es o3er$a/
and &o&-o3er$a/" 5n se&uence detector that allo0s o/erla,, the final .its of one
se&uence can .e the start of another se&uence" -ur e3am,le 0ill .e a 11+11 se&uence
detector" 5t raises an out,ut of 1 0hen the last * .inary .its recei/ed are 11+11" At this
,oint, a detector 0ith o/erla, 0ill allo0 the last t0o 1 .its to ser/e at the first of a ne3t
se&uence" 7y e3am,le 0e sho0 the difference .et0een the t0o detectors" 1u,,ose an
in,ut string 11+11+11+11"

11+11 detector 0ith o/erla, H 11+11+11+11
] ++++1++1++1
11+11 detector 0ith no o/erla, ] ++++1+++++1

8he se&uence detector 0ith no o/erla, allo0ed resets itself to the start state 0hen the
se&uence has .een detected" )rite the in,ut se&uence as 11+11 +11+11" After the initial
se&uence 11+11 has .een detected, the detector 0ith no o/erla, resets and starts
7oard)
- 1
2 $% ,o0er su,,ly */ - 1
' 5% 5% ?<?6,5%?<+2 1,1
< %onnecting 0ires - Re&uired
5>
searching for the initial 1 of the ne3t se&uence" 8he detector 0ith o/erla, allo0ed
.egins 0ith the final 11 of the ,re/ious se&uence as ready to .e a,,lied as the first 11 of
the ne3t se&uenceQ the ne3t .it it is looking for is the +"
Pre$imi&ar( La'. .or7=
$esign a circuit 0hich detects (+11) se&uences in a string of .its coming through
an in,ut line (i"e", the in,ut is a serial .it stream)" -nce the (+11) se&uence is detected,
out,ut .ecomes (1), other0ise it stays as (+)" A sam,le in,ut and out,ut .it streams
(se&uence) are gi/en .elo0" @irst .it coming to the in,ut is the one sho0n on the far left"
E3am,le 5n,ut .it stream +11+1111+11
E3am,le -ut,ut .it stream ++1++1++++1
7efore coming to >A7, find the state diagrams of this se&uence detector
a) As a !ealy machine
.) As a !oore machine"
80o reali:ations (!ealy, !oore) of the a.o/e se&uence detector are gi/en .elo0"
!oore and !ealy Reali:ation of (+11) se&uence detector"
Pro%e"ure=
1" 1et u, the a.o/e gi/en !ealy machine on your .oard"
2" $o not forget ,o0er and ground connections"
'" Mse standard s0itches (88> 1)8) for the ,reset and the clear control in,uts as
re&uired"
<" Mse a standard s0itch (88> 1)8) for the 3 in,ut"
51
*" Mse negati/e ,ulsar s0itch for the clock in,ut"
6" Mse >E$ s for states and : out,ut o.ser/ations"
?" Ferify your !ealy machine reali:ation on the .read.oard 0ith state diagram you
found in ,rela. 0ork"
=" A,,ly the a.o/e gi/en sam,le in,ut .it stream (se&uence) and o.ser/e out,ut
stream"
;" $ra0 time diagrams for the (3) in,ut, (y1, y2) state /aria.les and : out,ut
Ae&io&=
1" @or each in,ut there should .e a clock ,ulse (5n this case 1= ,ulses re&uired)
2" 5nitial state ++ should .e arranged .y ,reset and clear in,uts" Jou ha/e to
rearrange a.o/e e3am,le in,ut stream right after initial state has .een a,,lied"
Resu$
5*
A""iio&a$ E8/erime&s
51
E?.NO=11 Co"e Co&3erers
Aim =
8o reali:e the code con/erter using logic gates and to /erify the truth ta.le"
A//araus Re2uire"=
T!eor(=
8he a/aila.ility of a large /ariety of codes for the same discrete elements of
information results in the use of different codes .y different digital system" 5t is
sometimes necessary to use the out,ut of one system as the in,ut to another" A
con/ersion circuit must .e inserted .et0een the t0o systems if each uses different codes
for the same information" 8hus, a code con/erter is a circuit that makes the t0o systems
com,ati.le e/en though each uses a different .inary code" 8o con/ert from .inary code
A to .inary code 7, the in,ut lines must su,,ly the .it com.ination of elements as
s,ecified .y code A and the out,ut lines must generate the corres,onding .it
com.ination of code 7" A com.inational circuit 0hich ,erforms this transformation .y
means of logic gates is kno0n to .e %ode %on/erter" 1ome of the e3am,les for the code
con/erters are,
7%$ to H1' %on/erter
H1' to 7%$ %on/erter
1 8rainer Kit - 1
2 AN$ 4ate 5% ?<+= 2
' '-i(, AN$ 4ate 5% ?<11 1
< -R 4ate 5% ?<'2 2
* EH--R 5%?<=6 1
* N-8 gate 5% ?<+< 2
54
Lo#i% Dia#ram=
BCD o ?S1 Co&3erer=
Tru! Ta'$e=
BCD CODE E?CESS 1 CODE
B
1
B
*
B
1
B
>
E
1
E
*
E
1
E
>
+
+
+
+
+
+
+
+
1
1
+
+
+
+
1
1
1
1
+
+
+
+
1
1
+
+
1
1
+
+
+
1
+
1
+
1
+
1
+
1
+
+
+
+
+
1
1
1
1
1
+
1
1
1
1
+
+
+
+
1
1
+
+
1
1
+
+
1
1
+
1
+
1
+
1
+
1
+
1
+
Lo#i% Dia#ram=
55
B # B 2 B 4 B 1
A 4
A 1
A 2
A #
0 & < S 4 &
#
&
0 & < S 4 &
1
2
0 & < S 4 1
1 #
1 2
1 1
0 & < S 4 1
1 4
2
1
0 & < S 4 1
&
+
-
0 & < S 4 &
1 1 1 4
0 & < S 4 &
2
1
0 & < S 4 &
+
-
0 & < S 4 1
1
2
#
0 & < S # 2
1 4
2
1
0 & < S # 2
&
+
-
0 & < S # 2
1
2
#
0 & < S 1 - )
1
2
#
?S1 o BCD Co&3erer
Tru! Ta'$e=
E?CESS 1 CODE BCD CODE
E
1
E
*
E
1
E
>
B
1
B
*
B
1
B
>
+
+
+
+
+
1
1
1
1
1
+
1
1
1
1
+
+
+
+
1
1
+
+
1
1
+
+
1
1
+
1
+
1
+
1
+
1
+
1
+
+
+
+
+
+
+
+
+
1
1
+
+
+
+
1
1
1
1
+
+
+
+
1
1
+
+
1
1
+
+
+
1
+
1
+
1
+
1
+
1
Lo#i% Dia#ram=
59
A # A 2 A 1 A 4
B 4
B 2
B #
B 1
0 & < S 4 &
#
&
0 & < S 4 &
1
2
0 & < S 4 &
2
1
0 & < S 4 &
+
-
0 & < S 4 1
&
+
-
0 & < S 1 1
#
- &
+
0 & < S 1 1
1
1 2 2
1 #
0 & < S 4 1
1
2
#
0 & < S 1 - )
1
2
#
0 & < S 1 1
1 1
1 1 4
2
0 & < S # 2
1 4
2
1
0 & < S # 2
&
+
-
0 & < S # 2
1
2
#
Pro%e"ure=
1" 8he code con/erters circuits are designed using the 7oolean function 0hich is
found out from the truth ta.les"
N*F su,,ly"
5:
Resu$=
E?.NO=14 BCD A""ers
Aim=
8o design and im,lement the 7%$ adder using 5% ?<=' and to /erify the truth
ta.le"
A//araus re2uire"=
1 8rainer Kit - 1
2 < .it .inary adder 5% ?<=' 2
' -R 4ate 5% ?<'2 1
< AN$ 4ate 5% ?<+= 1
5;
T!eor(=
A 7%$ adder adds t0o 7%$ digits and ,roduces sum also in 7%$"7%$ num.er
uses 1+ sym.ols"
1" Add 2 four .it num.ers using .inary addition"
2" 5f four .it sum is e&ual to or less than ;, the sum is /alid 7%$ num.er and no
correction is needed"
'" 5f sum is greater then ;, add 6 to sum to ,roduce /alid 7%$ sym.ol"
Lo#i% "ia#ram=
Tru! a'$e
1M! %orrection
Re&uired
1' 12 11 1+ J
+ + + + +
+ + + 1 +
+ + 1 + +
+ + 1 1 +
+ 1 + + +
+ 1 + 1 +
+ 1 1 + +
5+
+ 1 1 1 +
1 + + + +
1 + + 1 +
1 + 1 + 1
1 + 1 1 1
1 1 + + 1
1 1 + 1 1
1 1 1 + 1
1 1 1 1 1
Pi& Dia#ram=
Pro%e"ure=
1" %onstruct the circuit as ,er logic diagram"
2" 1et the logic in,uts as ,er the truth ta.le"
'" -.ser/e the out,uts"
<" %om,are the out,uts and /erify the truth ta.le"
Resu$=
E?.NO=15 Se2ue&%e Ge&eraors
Aim=
8o design and im,lement the 1e&uence generator using 5% ?<=' and to /erify
the truth ta.le"
A//araus re2uire"=
9>
Desi#&=
8o generate a se&uence of length 1 it is necessary to use at least N num.er of
@li,-@lo,s, 0hich satisfies the condition 1S 2N -1"
8he gi/en se&uence length 1 C 1*"
8herefore N C <"
Note - 8here is no guarantee that the gi/en se&uence can .e generated .y < f(fs" 5f the
se&uence is not reali:a.le .y < f(fs then * f(fs must .e used and so on"
Cir%ui D ia#ram=
Tr u! Ta'$e
1 8rainer Kit - 1
2 < .it .inary adder 5% ?<=' 2
' -R 4ate 5% ?<'2 1
< AN$ 4ate 5% ?<+= 1
91
+ + +
1 1 1 1
+ + + +
1 1 1 1
!a,
Falue
%lock WA W7 W% W$ o(, $
1* 1 1 1 1 1 +
? 2 + 1 1 1 +
' ' + + 1 1 +
1 < + + + 1 1
= * 1 + + + +
< 6 + 1 + + +
2 ? + + 1 + 1
; = 1 + + 1 1
12 ; 1 1 + + +
6 1+ + 1 1 + 1
11 11 1 + 1 1 +
* 12 + 1 + 1 1
1+ 1' 1 + 1 + 1
1' 1< 1 1 + 1 1
1< 1* 1 1 1 + 1
Kar&au#! Ma/ ,or D=
WA
W7
W%W$ ++ +1 11 1+
+
Resu$=
9*

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KALASALINGAM UNIVERSITY

Kalasalingam Academy of Research and Educaion

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