... . . . .

To be presented at the International Conference on Microelectronic lest Structures (March 23, 1993)

SEU/SRAM AS A PROCESS MONITOR

B. R, Ellaes and M. G. Buehler
Jet Propulsion latlora~ory 300-329
4800 Oak Grove Drive
Pasadena, CA 91109

ABSTRACT offset voltage, Vo, that is used to evaluate

the spontaneous cell flip potential. lhc
lhe SEU/SRAM is a 4-kbit Static Random Access dimensions of the MOSFE_ls in the cell are
Mmory (SRAM) designed to detect Single-Event listed in lable 1. The timing diagram for
Upsets (SEUS) produced by high energy the operation of the cell is shown in Figure
par(icles. This device was used to dcternline 4. This diagram shows that the cell has
the distribution in the memory Cell three modes of operation: Read, Write, and
spontaneous flip potential. The variance in Stare. In the Read and Write cycles, V. = 5
this potential was dctcrrnincci to be due to v. ]nitially all the cells are written into
the variation in the n-MOSFEl threshold ttlc initial state which is described in
voltage. For a l.?-prn CMOS process, the Figure 3. lhen the cells are operated in the
standard deviation was found to be 8 nOJ. Stare cycle in which V. is gradually lowered
Using cumulative distribution and residual to a potential Vo(stare). In this state
plots, stuck cells and non-normally ionizing particles that deposit sufficient
distrit)uted cells are easily identified. charge will flip individual cells. If V. is
lowered sufficiently, the nmnory cells will
flip spontaneously. lhis is the behavior
INTRODUCTION: that will be analyzed in this paper for its
usefulness as a process monitor. It will be
lhc usc of matrixed test structures has [men shown that the spontaneous flip potential is
shown to tJe an effective approach (0 a measure of the uniformity of the threshold
collecting statistical data with respect to voltage of invcrter #1, Vlil.
inverter threshold voltages [1], mrtal steps
[?] , linewidths [2], and contact resistances
[3] . such structures requi re analog MEMDRY CELL MODE1:
instruments such as a digital voltmrter to
determine the measured value. lhe cell spontaneous flip behavior is
explained hy the SRAM transfer curves shown
The SEU/SRAM can be used to obtain analog in Figure 5. lhese curves were generat.cd
information using externally forced voltages using a simple model for the MOSFE1 drain
and on-chip latches (nmory cells). ?his current which does not include channel length
allows nlorc rapid measurements of analog modulation [5]. lhe inverter has an input
parameters. The structure used in this study voltage, Vin, and output voltage, Vout. 1 he
is the RADMON (RADiation MONitor), shown in CMOS invcrtcr transfer curve is divided into
Figure 1. Its primary purpose is to detect five regions [G] . These regions arc
single-event upset particles and total dose descrik]ed with respect to Vlrl = rl-fEl
radiation. lhe version used in this study threshold voltage, VT = p-FET threshold
-P
is an updated version of a [lr(!VicJllsly voltage, and VTi - inverter threshold
fabricated 1.6-~mI CMOS chip [4]. It consists voltage.
of an SEU/SRAM and two total dose P-FEIs.
in Region I, O < V irl ~ VTrl and Irl = IF] = O
In this study the SEU/SRAM is evaluated as a and Vout = VDD. In Region 11, Vln s Vin ~
process control test structure. The size of Vli and lnsat ~ Iplin. In Region 111, Virl =
the RADMON, as shown in Figure 1, is small ‘out? ‘nsat ‘ lpsat” In Region IV, VTi < Virl
po;tion, 2.7 rnrr?, of the stepper field of 200 < VDO - VTF), Irllin = IF,sat. In Region V, VDD
mm . lhc nmory cell layout is shown in - Vlp ~ Virl s VDDI Irl = IF) = O and Vou t = O.
Figure ?, TIN? SRAM was fatrricated with 1.2-
pm n-well CMOS process at a MOSIS brokered lhe MOSFE1 drain currents arc:
foundry,
( 1 ) ‘nlin ‘ F3n(Vin-Vln-Vout/2)Vout
lhc SRAM cell schematic, shown in Figure 3,
has a six-transistor memory cell with an ( 2 ) lnsat ‘ (~n/~) (Virl-Vln)2
 .

cumulative distribution is:

(3) lpl in = 0P(VDD-Vin-V_IP-(VDD-Vout)/2)
(6) N = Nt{l - crf[(Vo - Vol,)/Voo4?] }/2
. (VDD-Vout)
where crf is the error function. The result
(4) lp~at = (~P/2) (VDD-Vin-Vlp)2 of a least squares fit to each of the curves
shown in Figure 7 is listed in Tat)lc 3. -fhe
where B = KP” We/Lc and VT is the threshold entire range of data was fitted. Notice that
voltage. For p-FETs V1 is the magnitude of the curves with the largest standard
the threshold voltage. Also KP = PoCOX where deviations, namely chips #2 and #4, have
11 is the channel mobility, and C ~ is the CC1lS that deviate significantly from the
gate oxide capacitancclarea. Final fy We = W- main distribution. The standard deviations
AW and LQ = l-AL where W and L are the as- for the distributions is the tightest
drawn channel width and length respectively, observed to date Eming about 8 mV.
AW and AL are the channel width and length Previously observed standard deviation values
correction factors, respectively. lhe MOSFET for a 1.6-pm CMOS process were shout 10 mV
values used in the following analysis are [4] ,
shown in Table 2.
Sclectcd chips are examined in detail in
The memory cell has two stable states located Figures 8 to 10 where the cumulative and
at the upper-left and lower-right corners of residual distributions arc shown. 1 hc
the chart shown in Figure 5. As VQ decreases cumulative distribution allows a critical
from 5 V, the upper-left stable point follows examination of the tails of the distributic)n.
a path dcscribcd by the circles shok’n in lhc residual distribution allows a critictil
Figure 5. When V. = 1.5 V, the cell flips to examination of the cells near the mean of the
the lower-left stable point. distritmtion. An example of a stuck colunm
is shown in Figure 8 and a stuck cell is
shown in Figure 9. Acceptable behavior is
EXPERIMENIA1 RESULTS: shown is shown in Figure 10.

The memory cell V. distributions are shown in The results were simulated with a nomlally
figure 6 for eleven chips from Wafer #l. As distributed sample. As seen in Figure 11.,
seen in Figure 6, the SRAMS have a several data points fall slightly below the
distritwtion of offset voltages at which the fitted line in the tails of the distributicjn.
cells flip. The data was acquired by This sarnc behavior is shown in Figure 10.
lowering the offset voltage, Vo, and counting
the numt)cr of flipped cells at that V. value. A sunmary of the results from all the wafers
lhe memory was then reset and the offset included in this study are shown in Figure
voltage lowered to a V. that is 1 nlV lower 1?. These samples came from four wafers and
than the previous value and again the number arc tightly clustcrcd. Ihc mean offset
of flipped cells dctemlined. ?his process is voltage has a span of 30 rnV and the standard
repeated until all 4096 cells flip. Note deviation of the offset voltage varies from 7
that these curves arc Corrlplctcly to 9 nO1. This is considered excellent CCI1
deterministic. That is for a given Vo, the distributions for CC1lS located (a) within a
same cells flip. chip, (b) bctwccn chips, and (c) t,ctwccn
wafers.
The distributions shown in Figure 6 arc
Gaussian in nature and can bc characterized
by the normal distribution with a mean of Vol{ DAIA ANAIYSIS:
and a standard deviation of Voo. The
cumulative distribution plots for the chips lhc interpretation of results follows from
shown in Figure 6 arc shown in Figure 7. otlscrving the nature of the transfer curves
shown in figure 5, A close examination of
lhe data is characterized by the cumulative this figure reveals that the spontaneous flip
probability function using: point is dctcrmincd when V. reaches the
threshold voltage of invcrtcr #l, VTil. lhc
(5) P(Voi>Vo) ‘ 1OO”(N - 0.5)/N[ CMOS invcrtcr threshold voltage is determined
tly the conditions given in Region 111
where N is the number of flipped cells at V. descrihcd above:
and for this memory Nt = 4096. Ihc
analytical formula that dcscrihcs the
 VDD + VTn{Br - VTP The standard deviation of Vo , V “ “
( 7 ) Vii=- ~+~- duc to the variation in the n- ?fi :Iru;i:]j
r voltage. This conclusion was rcachcd as
follows. Introducing the FET model
where V1” is the n-MOSFEl threshold voltage, parameters listed in lablc 2 into Eqs. (9)
and VTP is the magnitude of the p-MOSFET and (10) leads to:
threshold voltage. The Beta factor is:
(11) VTio2 = 0.055”VTpo2+0.586”VTrlo2+ 0.008.G
KPn(Wn - AWn)(LP - ALP)
(8) Br=!n=. for inverter #1. lhis equation shows that
KPP(WP - AWp)(ln - Aln) Vlno is the dominant parameter.
‘P
The invertcr threshold equation is plotted in Now the results in Figure 12 and lable 3 can
Figure 13 and shows that for Br + 0, Vli = he intcrprctcd as follows. The mean offset
VDD - ‘Tp and ‘or ‘r + ‘$ ‘Ti = ‘Tn. voltage is:

Using propagation of error analysis, the (12) Vo,{ = Vlil

variance of the inverter threshold voltage
is: and

‘Tpo2 , -BrvTno7 (13) V oo z VTnol

(9) Vli02 ‘-
(1 + hr)z (1 + {i,.)? lhe conclusion, given in Eq. (13), is
determined by the layout of lNV#l where Elr] =
Br(VDD - Vln - VIP)? 10.7. Thus by changing the layout of the
i- .G cells, various features of the cells can he
4(1 + @)4 sensed.

where
CONCLUSION:
wno~ , ‘p02 , !no? Lpo2
( 1 0 ) G=- lhe SEU/SRAM provides data on the unifomlity
wer~ w,: le:+i,[: of a CMOS process. lhe 4-ktJit SRAM memory
cell offset voltages were found to t)e
lhcse equations show that for Br = O, Vli = nomlally distributed. lhe offset voltage
(VDD - Vlp,,)*VTpo and for E3r = Dj, VTi = depends on the threshold voltage of invertcr
‘ln~l*vTno. #l and its distribution depends on the
variation in VTnl. Cumulative distribution
1 he spontaneous flip point, Vo , was plots reveal SRAMS with stuck bits which
determined to km equal to the invcrter appear in the tails of the distributicln,
threshold voltage of invertcr #l. lhis Residual plots reveal SRAMS with bits that do
conclusion was reached as follows. The Beta not flip according to a nomlal distribution
factors for the two inverters in the memory near the rncan of the distribution. 1 he
=
cell arc: E3rl 10.7 and Br2 = 15.1. observed variances were about 8 n$l. lhis
Introducing these values into Eq, (7) leads result is considered excellent behavior
to the invcrter thresholds: VTil = 1.48 V and within a chip, chip-to-chip, and wafer-to-
Vli2 : 1.39 V. The VTil = 1.48 V is the wafer. ?his result provides a measure of
spontaneous flip point shown in the excellence to be met by future CMOS founclry
sinwlation given in Figure 5. This value is runs.
close to the experimentally observed V.
values C1OSC to 1.72 V sunmlarized in Figure
1?, ‘Ihc discrepancy between 1.48 and 1.72 is
easily explained hy the sinplislic MOSIET REFERENCES:
model given in Eqs, (l)-(4). If channel
length modulation was included in the MOSFE1 1. D, J. Ilannaman, ct. al., “lnverter Matrix:
model , then the transfer curve for INVT#’1 A vehicle for assessing ttlc process quality
would have a finite slope at the mid-point. through invcrtcr parameter analysis () f
lhis will increase the modeled spontaneous variance”, ICMIS Vol. 4, 107-111 (March
flip point from 1.48 V and bring the result 1991).
closer to the experimental value of 1.72 V.
,.

?. H. Sayah and M. Eluchlcr, “lincwidth and Table 2. MOSFLT Model Parameters

step resistance distribution mcasurcmcnts (Run N260, 1 0 = 20”C)0
using and addressable array”, ICMTS, Vol 3.
89-9? (1990).

M. G. Buchlcr and Il. R. Sayah, “Contact

‘ARAM UNIIS

rl-FEl RESULIS
I MEAN SIDEV

3.
resistance mcasurcrncnts using an addressable
array”, Proc. VLSI Multilevel lntcrconncct VT O 0.69 f 0.0101
‘ 2
/iA/V
Confercncc , ??7-2’37 (1987). KP O 69.00 * 1.2000
Aw pm 0.46 f 0.0200
4. M. G. !3uchler, B. R. Blats, G. A. Soli, AL pm 0.46 i 0.0116
N. 7amani, and K. A. Ilicks, “Design and
Qualification of the SEU/lD Radiation Monitor p-FE’ RESULTS
Chip”, JPL Publication 92-18 (October 1,
1992) . Vl o 0.95 * 0.0087
KPO 23.00 ! 0.5200
5. Y. P. Tsividis, Operation and Modeling of AW 0.30 $ 0.0310
the MOS transistor, McGraw-Hill (New York, Al 0.35 ~ 0.0180
1987) .

6. N. Wcste and K. Eshraghian, Principles of

CMOS VISI Design, A systems Perspective,
Addison-Wesley (Reading, MA, 1985). Tatllc 3. SEU/SkAM V. results.

WAFER NO.1
ACKNOWLEDGMENT: CIIIP Vopfvoo

The research described in this paper was #l 1.7?46+0.0076

performed by the Center for Space #2 1.7202?0.0091
Microelectronics technology, Jet Propulsion #3 1.7226f0.0081
laboratory, California Institute of {4 1.731930.0092
technology, and was sponsored by the #5 1.7209~0.0078
Strategic Defense Initiative Organization. #6 1.7224$0.0075
lhc 1.2!-~mI CMOS SEU/SRAM is a part of RADMON
designed for use on the SIRV (Space
$9
f?
#8
1.7247i0.0077
1.7099f0.0089

I
technology Research Vehicle) to be launched 1.7236%0.0084
in 1994. The authors are indebted to MOSIS #lo 1.7108*O.OO79
for brokering the CMOS fabrication and to #11 1.7205*0.0078
Gcnma Tardio for the MOSFET model parameter
data.

File: lCM13322.doc

Table 1. Dimensions of SEU/SRAM MOSFEIS.

FET [(pm) W (~ml)

Mnl 1.? 2.4 17.92 180.8

Mrr? 1.2 3.? 74.88 16.9
Mpl 3,2 2.4 14,08 255.5
MI)? 3.? ?,4 12,16 16.9
Mtl 1.2 2.4 ---.-
Mt? 1.2 2.4 .--.-

Figure 1. RADMON: 1.6 rrnl x 1.7 nml.

 ,– *
~ , , ,T ,., , ,_T , ,.., , , , ,

lk- - - - - 4
1 I t ,-,-

Vo 1 Vol = 5.0 v
V02 ;:; : :;:; -
F. 4 )--- -- W&q?
V04 = ?.OV
2 V05 = 1.7V
hi V06L 1.5V
23 V03
V07 = 1.3V
!1
~ SF’ONIANEOUS
V04 FLIP POINT
q?
CY
2 -. lNv~l
Lll
c>
yl V“7

o t , .,
t1 d. —f-a::, :2= A—J._L ,. , t (A—, ., ... .,
0 1 2 3 4 ~
MT.-M m+ NODF NO, 1 VOLIAGE, V1 (V)
Figure 5. SRAM transfer curves showing the
variation in the stable point, indicated by
Figure 2. Memory cell: 33.6 pm x 36.0 pm.
lhe n-well and n- and p-select layers are circles, as the offset voltage, VA. is
lowered-to the $~JOntaneOUs flip p;i;t. ‘-
omitted.

4 mo T 1 I --,
t. CHIP41

IVOF~D LINE .—. 4000’

VLm 35EKf
~ 3000
lNV# 1 lNV/2 ~.l VO 0
‘1” ~
/
Mpl-(f3Ff) Mp2’(ON) - c) 2500
1 L, I
n
).- PMmclf Q 2000
E@? S1 &S4&M t+
[“
~I - “ - - 1f
- -1 1
~ 1s00
+3 c+
i L. VI -i “ L 2
M(1 MCI 1000
v?
C4 500
Dnl Cfn? 4 fpulse
0 i
I [ ! 1.70 1.72 1.74 1 .7Ei
Mnl(ON) Mr :OFt) $mf,x,,%
/ .,-- ‘..1 OrFSET VOLTAGE, VO (V)
<BIT > Figure 6. SEU/SRAM spontaneous flip response
from eleven chi~s taken from 1.6-mrl CMOS
Figure 3. SRAM memory cell circuit. Wafcr#l.

99.99 ~
99.9 ‘
..__. -.
1
AXXXXXXX .XxXx Xxxm 2 99,
,@
E. r L - r ” l.r L
R. r L s go
n)
Q- Kx xx xx } $ -/0
c1 50
WF<IIE C<C:E (f{=rO, Q: }1[7, VO=VDD=W) Q
c> ‘ 30
1
AXXXDXXX ! 10
01
r . f“ L -.S L >
w -... r L :, 1
c)
DXXmXHXX
0,1
SIARE CYCIF 0.01
s. (VDD = W)
1.69 1.-/0 1.71 1 .7? 1.73 1,74 1.75
L r
E-1 Dtllk-,, w> OF ISII VOITAC;f, VO (V)
V. -w

\ /VO(store) Figure 7. Cumulative distribution plots for

n,,.,,Ar
the chips shown in Figure 6.
liyure 4. SRAM memory cell timing diagram.
 ~ 99.99
: 99.9
r
c1
.5 99
0
> 90
A
-0
> 70
‘“i6 - - - - - --- - -- ‘ Vh ; so
n
30
.5 ,
r \ n 10
-1
‘k L
it c1 u
~ 1
m
$-5 :
> 0.1
b N?6D v WLu# I I :NlP#4
-- ‘H H
2 0.01
-1o- 1.69 1.-/0 1.71 1.72 1.73 1.74 1.75 1.76
1 .?0 t.?? ““ 1.74 1.76
WU4*$UJT. Of}Sfl WLT,kGf, VQ (V) Of FSLl VOLIAGE, VO (V)
Wrlx?,m
figure 8. Results from Chip#4 Figure 6)
showing a stuck column. Figure 11, Ideal cumulative distribution
plot for Vol[ = 1.72 V and Voo = 8mV.

0.010 ,,, , ., —–—–, .––, .,,

e.
>
I

1
\/b v
0
0
‘. 00 . 0 0 9 0 °
o
~ v
t
VI
~; o.~f3
4 VW

. . . . ..
. . ‘---. . .. .. . 1
,<
$
t, 0.007
II
in
II
L1
c1
0.006 , , , , , , , _,_ ,. I
1.69 1.70 1.71
1.77 1.73 1.74
**14*1 w OF~SO W3LTAGC, Ve (v)
OFFSEI VOLTAGE MEAN, VOP (V)
ti.,, m-.
Figure 9. Results from Chip#2 .-
(Fiqurc 6)
showing a stuck bit. Figure 1?. Standard deviation vs mean offset
voltage for chips fabricated on four wafers.
The lines are linear re~ression fits to data
from each wafer,

99.99

4{/
99.9
>“ ‘
9
, ,,, ,,,,, ! ,,, ,,,,, r ,1, !, IT. , ,,, ,,,,, , rr, ,,,,~ , ,,, ,,

~ 90 . . . . . . . . . . . . . . . . . . i
.
Fij : ““’”’’”’” ““’””’”””””
.
31
0.1
r +
‘“7A ~

:‘[1; I
.8 ,,

j o
b%
$
-5
Ej
N?6D fft R#l HIP#l
- I v .~ 1- t , ,,,,,,,1 t ,,,,,,,1 , ,,,,,,,1 , ,,, ,,,,, , ,,, ,,,,, , ,,, ,,
1.70 t .72
*W,,,,*
1,74 1.76
Ciool 0.01 0.1 10 100 1000
OFf Wl WLTACX V. (v)
W.’,,, ca m% fir’ (b,
Figure 10. Results from Chip#l (Figure 6)
showing acceptable behavior. Figure 1 3 . lnverter threshold voltage
dependence o n tile MOSFE1 geonwtry f a c t o r I?Ir.