Low-Power High-Performance and Dynamically

Configured Multi-Port Cache Memory Architecture

H. Bajwa and X. Chen
EE Dept, Grove School of Engineering, City College and Graduate Center of the City University of New York
Convent Ave. at 140th St., New York, NY, 10031 U.S.A.
Email: bajw@ee.ccny.cuny.edu; xchen@ccny.cuny.edu

Abstract-As on-chip cache size has increased considerably in

recent high-performance microprocessor technologies, power
dissipation and leakage current in SRAM have become critical.
High-performance IC designs use multi-port cache memory to
provide the needed accessibility and bandwidth. Since the word
and bit lines cover the foot-print of the entire cache section,
duplicating the word and bit lines for multiple ports results in
large silicon area and increases bitline discharge and power
dissipation.
As technology scales down device size and supply voltages,
static power dissipation has emerged as a critical factor in total
system power dissipation. In this paper, we present an area- and
energy-efficient multi-port cache memory architecture, which
employs isolation nodes, local sense amplifiers and dynamic
memory partitioning techniques, to facilitate simultaneous multi-
port accesses without duplicating bitlines. The proposed cache
memory architecture also reduces bitline latency.
Sub-threshold leakage current flowing from drain to source,
even when the transistor is not operating, has been a dominant
leakage current in high performance microprocessors where L I
and L2 cache occupy majority of die area [1, 2, 3]. As
transistor size scales down, power dissipation becomes a
serious problem that limits overall system performances [2, 4].
In high performance systems employing multi-core
technologies, bitline leakage current can contribute to as much
as 5000 of overall cache memory leakage power [5]. The trend
of using multi-port cache in modem microprocessor
technologies [6] has exuberated this further, as leakage current
dissipation scales proportionally with the area of the circuit [7].
In this paper, we will further explore low power and area
efficient architecture presented in [1]. We will focus on power
dissipation in dynamically configured memories. The rest of
thesipapern is oganizcasllycows.gur ectrios.
the paper iS organized as follows. In I Sections IIII and III we port configuration. When the word line (WL) is selected, the
analyze present SRAM technologies and leakage current in SRAM cell is connected to the pair of bit lines (BL and BL)
II. SRAM LEAKAGE POWER
Lowering threshold voltage and gate oxide thickness has
resulted in significant increase in sub-threshold leakage in sub-
micron technologies [2]. Since static power strongly depends
upon technology and circuit optimization most of the research
activities toward reducing leakage power focuses on materials
and circuits.
Before we propose low power area efficient SRAM
architecture, we are going to look at leakage current
components in conventional single and dual port memories.
cmpent
Embedded SRAM ionalcsingle
s suffers form cell dland r e ie
leakage current and bitline
leakage current [9]. Five basic components of cell leakage
current are: reverse biased, sub- threshold, gate induced punch
through and gate tunneling leakage current. Sub threshold
leakage current is drain source current of the transistor when
the gate source voltage is less then the threshold voltage i.e.
transistor is operating in weak inversion. It is main contributor
to leakage current and is defined by Berkeley BSIM model as
follows:
VdsA7
a K Vgs - Vth- Voffl
Idsub = Io 1- exp - exp (1)
Vt)] n 7
where, Voff is an empirically-determined model parameter;
Vt = KT / q is a physical parameter proportional to the
temperature; Vth is the threshold voltage, and the current
Io = Iso'*W / L is determined based on the geometry. When a
transistor is off (Vgs=O and Vds=Vcc), the leakage current
going through it can be reduced either by increasing the
threshold voltage or reducing its width.
III. CLASSICAL SINGLE- AND MULTI-PORT SRAM
Fig. 1 shows the classic 6-transistor SRAM cell in a single-
D T

these technologies. In Section IV we review some previously via access transistors T5 and T6. Figure2 shows the SRAM cell
proposed architectura and circuit techniques whichwith dual ports, each is hardwired with dedicated word and bit
leakage acurrentu btine ulatencyIniSectio wedwil
and V lines, and how duplicating bit-lines causes bit-line leakage
preskage am confed memoy. arhiecture flwed
dcufent
present dynamically ponig (DPM) algorithmsur inguSeto transistors T7multiply.
current to The word and bit lines and access
and T8 for the second port would almost double
by dynamic memory parhtitoning (DPM) algorithms in Section Il-.1- -,I .If

VI~~~~~~~~~~~~~~~~.InScinVIw.rsn h ici iuainmdl the silicon area [10] of the single-port configuration.
followed by conclusions in Section VIII. Subthreshold leakage current, drain-source current of the
transistor when the transistor is operating in weak inversion is
a major contributor towards SRAM leakage current [11]. Pre-

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charging, as well as keeping the bit lines high, causes accesses simultaneously. Therefore, it doubles (in the case of
significant power dissipation and contributes heavily to the dual-port) or multiplies (in the case of multi-port) the
total power dissipation. bandwidth of a single-port cache.

When "O" is stored, transistors TI, T5 and T4 dissipate Leakage current for a dual-port memory cell can be
leakage current. When "1" is stored, T2, T3 and T6 dissipate described as:
leakage current. The leakage current in a single-port SRAM Idcell = Idsub(T1) + Idsub(T5) +Idsub(T4) + Idsub(T7) (4)
cell is described as follows
Idcell = Idsub(T1) + Idsub(T5) +Idsub(T4) (2) For a memory core with N rows and M columns this leakage
current of Equation 4 can be represented as:

| WL Idcell.= N Idsub(T1)
J +
Idsub(T5) +Idsub(T4))
I . N * M +Idsub(T7)

IV. TECHNIQUES TO REDUCE LEAKAGE POWER

Xf, -"
T6 Most of the recent research activities in this area are geared
toward reduction of sub-threshold leakage current in on-chip
T2 l / - | [ T4,
cache. Among process and circuit level techniques dynamic Vt,
dual-threshold voltage, reduced-gate SRAM (RG SRAM) and
gated Vdd have been discussed in [12-15]. Dynamic Vt SRAM
BL BL [12] reduces leakage current in cache memories by switching
cache lines to high Vt if the access has a small probability. The
dual-threshold voltage technology [13] uses high threshold
Fig. 1. A Single-PortnSRAM Cell voltage devices to reduce leakage current; low threshold
voltage devices are used where high performance is required.
For a memory core with N rows and M columns this leakage Reduced-gate SRAM (RG SRAM) uses two additional pass
current is described as: transistors connected between the cross couple inverters to
Idcell= N * M(Idsub(Tl) + Jdsub(T5) +Jdsub(T4)) (3) decrease gate leakage current [14]. Gated Vdd [2] reduces
leakage power by using high threshold transistor between a
virtual ground and GND to cut off the power supply to the
0< WL (Port o) memory cell in a low power mode.
0
r Among architectural techniques bitline segmentation [6,
15-

o0
18] and W3
sub-banking have reduced leakage power significantly.
Most of the architectural techniques are combined with
Ow<~~~~~~~~relevant
>O circuit techniques to suppress unnecessary leakage
o S power.
HX Albonesi [15] reduces power dissipation by enabling
X s s / ~~T4[T4
_ E only a small portion of the L2 cache at a time. Zhu et. al. [19]
1> ~~~~designed low power SRAM by enabling banks to switch
T only a smallportionof
between active and standby mode. Bitline segmentation
efficiently reduces leakage current by shorten the bitline length
BL BL dynamically. Karandikar et. al. [16] divides bit lines into
hierarchical segments to reduce bitline capacitance and adds
Fig. 2. A Dual-Port SRAM Cell parallel bit lines to access SRAM cells. Adding parallel bit
lines in the above architecture, however, has the drawback of
Fig. 2 shows the classic hardwired dual-port memory larger memory area. yang et. al. [18] explored this architecture
architecture, where each SRAM cell is accessible by two ports further and proposed hierarchical bit lines with local sense
with dedicated word and bit lines for each The addition of the amplifiers. One major source of energy dissipation is
word and bit lines and access transistors T7 and T8 would charginng the whole bitline. Rao [6] divides bitlines
almost doublerthe siliconoarea. into smaller segments such that segments higher then the
The dual-port (as well as multi-port) memory architecture current access cell are isolated from bitline precharge.
has been implemented with instruction and data cache in multi- Although this approach incurs additional delay, it reduces the
core processors in recent years. The most important advantage
of this architecture is that it can execute multiple cache

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length of bit lines for accessing cells near the physical ports,
hence, reducing latency and power dissipation. IT--
. VMzer Port
--
The cache memory configurations employed in the above Pre-cha e circuit
mentioned approaches use fixed bank size and duplicated word
and bit lines (without providing dual- and multi-port accesses), l
hence, incur either moderate performance degradation or large B
area overhead.
V. DYNAMIC MEMORY PARTITIONING ICL (ii Leakage current
The proposed architecture employs a DMP technique that
uses isolation nodes to partition a cache memory block into Cell
two virtually independent sections based on real-time access Set(x)
addresses of multiple ports. Figure 3 shows placement of
isolation control line (ICL) and isolation node on each of the
1WL6+7,
bit lines to divide an SRAM block into the upper and lower Cell(+7) 0
sections, which are to be accessed by the upper and lower Set(x+7)
ports, respectively. A selected ICL turns off isolation nodes
based on the real-time access addresses at the upper and lower
ports. Compared with the hardwired dual-port SRAM as shown
in Fig. 2, DMP can provide dual-port accesses without the need
of the second pair of bit lines and effectively reduce leakage Group(g)
current, bitline latency and silicon area. RL BL

Isolation nodes placed on bit lines introduce additional

latency. Rao et. al. [6] showed that bit lines segmented by 8 Fig. 3. ICL and Isolation Nodes Placement
isolation nodes pose no significant performance degradation.
With DMP the placement of isolation nodes is of strategic iss T TAG INDEX OFFSET
importance. Placing isolation nodes between adjacent word PortB
lines provides the highest degree of flexibility for DMP, but out

would be overkill if the applications do not need or utilize such

fine-grain DMP capability. In principle isolation nodes are Set512
placed for every n word lines, where n is determined based on
the statistical patterns of access addresses of targeted Set 3
applications.SeIStID
TA
In Fig. 3 the bit lines across 512 word lines which are A T
divided into 8 groups, each contain 8 sub-groups. Each
contains a local sense amplifier block and a local pre-charge
groupGA
RR
block. An ICL and two isolation nodes are placed between sub- A A

groups, each across 8 word lines. When an ICL turns its

isolation nodes off, the upper and lower ports can access
desired cells from different sub-groups. Each group's local
sense amplifiers ensure that the group's bit line section TAG INDEX OFFSET
accesses cells on 64 word lines separated by 8 isolation nodes
wit miia additional delay[6r]. Fig. 4. A Cache Subsystem with DMP
Simultaneous accesses to the cache via multiple ports may
Thus a large cache memory can be divided into virtually encounter potential conflicts, known as access conflicts. For
independent sections. Figure 4 illustrates the structural example, a READ and WRITE operations via Ports X and Y to
the same cells may take place simultaneously. When this
configuration ~ ~ ~ ~ ~ ~ ~~
converting a conventional single-port 8-way ocur
configurahon hadie
cache memory into a dual-port cache with DMP without occurs, existig (hardwired) mulh-portmemory
r existinn
aces
access coflc
conflict multi-ona ortlmemoy
adding the bit lines for the second port. resolutions may require the READ-WRITE-READ sequence to
be executed to ensure data integrity. With DMP, all existing
multi-port memory access conflict resolutions still apply and
no changes to these protocols are necessary.

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 A small circuit block is used to compare the addresses and k = current ICL;
calculate ICLs. DMP operations are carried out in parallel with if (j < k < i) return NULL (no new DMP);
address (including bank selection) setup and bitline precharge else return (j + (i-j)/2);
phases, as depicted in Fig. 5. There is no overall operation For coarse-grain cases, DMP-2 is adjusted accordingly.
delay due to DMP. It is important to note that a new ICL is
enabled only when the current ICL cannot provide valid multi- ORTB
port accesses.
Address ________________________To X ~~~
fI~~ICL(l).--
L(2) -WL (3) -4 -W
VL(1)
L
(2)
<
AddrelI__ fU3)- _______________
-L(3
fCL(4).-----------1 ---WVL (4)
f CL(5){WL)
T1 T * * ~~~~~~~~~~~~~~~~~~~~WL (6)
DMP \ /

Pr e - < X<=~T ICL (i-Il) - - - W

DataI

Toc: Operation cycle time; TAS: Addr setup time
TBA: Bank address setup time;
TICL: ICL identification time;
TDP: Valid data
Tp. Precharge time
ICL (n-i)_.
Fig. 5. Memory Operation Timing with DMP
VI. DYNAMIC MEMORY PARTITIONING ALGORITHMS
Optimal cache partitioning not only provides dual-port
access but also reduces delay and minimizes power dissipation.
Efficiency of dynamically partitioned algorithm is determined
by three factors, delay, power dissipation and complexities of
proposed algorithm. Two generic DMP algorithms are
developed based on fine-grain DMP illustrated in Figure 6.
Algorithm DMP- 1 provides the optimal partitioning that
minimizes bitline latency and power dissipation, with which
two ICLs are turned off during partitioning: ILC(j) is turned off
for the upper port to access WL(j), while ILC(i-1) is turned off
for the lower port to access WL(i), where j < i. This approach
ensures shortest active bitlines for both the upper and lower
ports, hence minimizing latency and power dissipation. The
pseudo-coded of DMP-1 as follows:
addr (A) <1: n>; addr (B) <1: n>;
where addr (A) = i > addr (B) = j;
if i = j +1 return ICL (j);
else return ICL (j) and ICL (i-1);
For coarse-grain DMP (an isolation node is placed on bit
lines between every n word lines), DMP- 1 is adjusted
accordingly to select correct ILCs to turn off.
For applications that do not require a new partition for every
memory access, algorithm DMP-2 minimizes the switching of
isolation nodes by identifying whether or not a current partition
can facilitate new accesses. In this case, one selected ILC is
turned off for a DMP. The generic fine-grain DMP-2 algorithm
is pseudo-coded as follows:
addr (A) <1:n>; addr (B) <1 :n>;
where addr (A) =i > addr (B) = j;
ICL (n-3) -ii ---
ICL (n-2)
-7 W
---3L (n-2)
_WL (n-i)
WL (n)
Fig. 6. Generic DMP Model
VII. CIRCUIT SIMULATION MODEL
Scaling down geometry and voltage parameters has proven
to be too simple to predict behavior of nano-scale technologies.
We have used BSIM Predictive Technology Model [20] to
calculate resistance and capacitance of MOS devices. Bit line
delay, wire resistance and capacitance is an increasing source
of concern in sub-micron cache design [21]. Figure 7 shows
the wire resistance trends evaluated from [22] as technology
scales down form 32nm to 90nm. Fig. 8 shows transmission
gate and MOS devices resistance generated with the BSIM
Predictive Technology Model [21]. As technology scales
down, device resistance decreases and delay due to isolations
nodes will become smaller. Fig. 9 shows the circuit simulation
model for the active bit lines with DMP. The isolation node
(implemented as a transmission gate) is modeled by RT and 2
CT. With Wn/Wp =0.5, using 90nm technology, we calculated
the capacitance and resistance for transmission gate. For
simulation purpose the drive inverter of SRAM cell is replaced
with equivalent Ro and CO. Though the length and width of the
wire is difficult to predict in the earlier stages of design we
used a stick diagram to evaluate the length of the wire to be
602 per memory cell. Rw and Cw represent wire resistance and
capacitance between 2 bit cells on the same bitlines. CL is the
total load capacitance of the local sense amplifier structure.

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 multi-port memory. Shorter active bit lines also means less
latency.
50
40 Cache memory often contributes a large part to the total
30 system power dissipation. This happens as the bit lines remain
i 20 pre-charged even when not accessed. The proposed
r0 ___RWIRE architecture reduces leakage power by using bitline isolation
0 and selective pre-charging. Dynamically configured memory
32 45 65 90 not only reduces leakage current by eliminating pass transistors
Technology 32nm - 9Onm in hardwired multi-port memory, but also reduces the bitline
leakage power to half by eliminating additional bitlines.
Leakage current in dual-port dynamically configured memory
is the same as (2). For a memory core with N rows and M
columns the leakage current is reduced to less than half the
70 value of hardwired dual-port memories.
60 X Idcell= * M(Idsub(Tl) + Idsub(T5) +Idsub(T4)) (6)
50 2_ _

Q 40
30 = _ =
_ .2
Z 20
R-NMOS (Ohms) X<
10 RT-GATE (Ohms)
R-PMOS (Ohms)
_
, _'
0 / OO
32 45 65 90
Technology 32nm - 90nm 600mX

Fig. 8. Technology Scaling Impact on MOS Devices and Transmission Gate-

Resistance iLh W i.

t iv
I
th I solatiNo s
0I0
RO
-A
R Rw Rw RR I
I.0 402P times I 0p

' TCc, TCP FwTrP 1Gw TCWICT TCT CL Fig. 10. Bitline Delay with/without Isolation Nodes
Using 90 nm technology data we estimated bitline delay by
calculating resistance and capacitance in the drive circuit,
i

Drive Wire RC Model Isolation node

---------

Inverter and Pass Transistor RC Model

Capacitance
Fg9.RMdloapactiveBitince with Isolation Node
VIII. CONCLUSION
An area- and energy-efficient multi-port memory architecture
is proposed. It employs new DMP techniques, which use
isolation nodes and control lines to dynamically partition the
bit-lines of a memory block into virtually-isolated sections, so
that they can be accessed simultaneously and independently,
Compared with the classic hardwired multi-port memory
architecture the new DMP facilitates efficient designs with no
significant impact to the timing of memory operations. It
reduces the use of silicon area largely due to the elimination Of
additional bit lines. On average, bitline pre-charge and leakage
currents are reduced to half the value of typical hardwired
wires ' transmission gate and load. Resistance and capacitance
per cell is calculated to be 0.36 Q and 0.6675 JF, respectively.
Capacitance of pass transistor in cutoff mode is calculated to
be 76 jF. Transmission gate resistance RT and two ground
capacitances CT are calculated to be 39.2 Q and 376 if,
respectively. Figure 10 compares the bitline delay in a 64
rd-linelok with an witho islin des. ach
iorlion node sate an 8w'olin s ock from
another. note wors ase, when-the sulous aces
a
addresses are near either the top or the bottom of a cache block
(hence one active bitline is much longer than the other), the
delay of the longer active bitline is increased by about 200 ps
compared to the hardwired bitline without the isolation nodes.
When accesses are facilitated with a DMP in the middle of the
bitlines, the delay of the active bitlines for each section is about
400 more of the hardwired version, with less pre-charge time.

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Combined with local sense amplifiers and port multiplexing,
the proposed DMP can support efficient multi-port cache
architecture to reduce silicon footprint, wiring contention,
power dissipation and bitline latency.
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