Gate Leakage and Its Reduction in Deep Submicron SRAM
Ankur Goel Baquer Mazhari
(goelankur_iitk@rediffmail.com)
Department Of Electrical Engineering, IIT Kanpur (India)
Abstract
In this work the impact of gate leakage on SRAM is
described and two approaches for reducing gate
leakage currents are examined in detail. In one
approach, the supply voltage is reduced while in the
other the potential of the ground node is raised. In both
the approaches the effective voltage across SRAM cell is
reduced in inactive mode using a dynamic self-
controllable switch. Simulation results based on BPTM
(Berkeley Predictive Technology Model) for 45nm
channel length device show that the scheme in which
supply voltage level is reduced is more efficient in
reducing gate leakage than the one in which ground
node potential is raised. Results obtained show that
96% reduction in the leakage currents of SRAM can be
achieved.
1. Introduction
As a result of continued scaling of MOS
transistor, a dramatic increase in the performance of
VLSI ICs has been achieved. However, as a result of
scaling, power dissipation due to leakage currents has
also increased dramatically and is a major source of
concern especially for low power applications. Till now
the dominant leakage mechanism has been due to drain-
source subthreshold current. Assuming this leakage
mechanism, a number of techniques have been proposed
in literature for reducing the impact of leakage power
dissipation such as gated-Vdd scheme [1], Dual-Vt
SRAM [2] etc. With scaling of channel length, oxide
thickness also needs to be scaled to maintain proper
operation of MOS transistor. As a result, even though
supply voltage has also been reduced with new
generations of technology, the magnitude of gate
leakage current has increased steadily and is likely to
become comparable or even larger than Sub-threshold
leakage for future CMOS devices [3]. Although, process
level techniques may be developed in future to alleviate
gate leakage currents through use of high-k gate
dielectrics, it is also important to develop circuit level
solutions for this problem. According to projections
from ITRS, memory will occupy about 71% of the chip
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(baquer@iitk.ac.in)
area by 2005 [4] and 90% by 2013 [5]. With the
perspective that leakage power dissipation in memory
would constitute a significant fraction of overall power
dissipation, an analysis of leakage currents in an SRAM
cell has been carried out and techniques for suppressing
it are compared. Of the several techniques which have
been proposed to reduce subthreshold leakage in SRAM
cells [6], [1], [2], use of a self-controllable switch (SVL)
[7] which allows full supply voltage to be applied in
active mode and reduced supply voltage in inactive
mode appears to be particularly promising for reducing
gate leakage currents as well. An SVL can be used
either to reduce the supply voltage to the SRAM cell or
increase the potential of ground node and the two
approaches can be combined as well. Although a
technique similar to use of SVL for raising the ground
potential has already been reported to yield significant
reduction in gate leakage currents [8], a detailed
comparison of these alternative approaches has not yet
been undertaken. The present work describes such an
analysis and shows that use of SVL for reducing supply
voltage yields the maximum reduction in leakage
currents especially when the pre-charge transistors are
put in cut-off state during the inactive mode. The impact
of reduction in supply voltage on static noise margins is
also discussed.
2. Leakage Currents in SRAM
For CMOS devices of 45nm channel length and physical
oxide thickness of .7nm, both gate as well as
subthreshold leakage currents are important. These two
current components for a 6T SRAM cell are as shown
in Fig. 1. In the inactive state, the word line is held ‘low’
and the bit lines are charged to ‘Vdd’. The leakage
currents flowing through the transistors depend on the
value stored in the cell. When ‘0’ is stored (as shown in
Fig. 1), there is significant gate leakage current through
N-type transistors M2, M5 and M6 and the mechanism
is primarily edge direct-tunneling (EDT). Although a
similar mechanism operates in transistors M3 as well,
the gate leakage here is negligible because of its P-type
nature. Gate leakage is maximum in transistor M1 and
the mechanism here is primarily on direct tunneling.
 Gate leakage current in PMOS M4 is relatively Vdd
insignificant even though a similar mechanism operates.
Subthreshold currents originate in transistors that are in
OFF state and that includes transistors M2 & M3 in the M3 M4
cross coupled inverter pair and access transistors M5
and M6. Except for M6 whose drain-source voltage is '0'
'1'
zero, all three other transistors have significant sub- M5 '1'
'1'
threshold leakage currents. M6
Vdd M1 M2
WL='0'
WL='0'

BIT BITB
Vs
M3 M4
PL1
NL1
CLKB='0'
Vdd 0V Vdd
M5 Vdd PL2
M6
M1 M2 reduced gate
WL=0V un-reduced gate leakage
WL=0V leakage

extra gate
reduced sub-threshold leakage
leakage

gate leakage sub-threshold
leakage
Fig. 1: Dominant Leakage Currents in a 6T CMOS
Conventional SRAM Cell.
. To summarize, there are four dominant components of
gate leakage current through transistors M1, M2, M5 and
M6 and three subthreshold leakage current components
through transistors M3, M2 and M5. A leakage current
strategy should thus address all these leakage current
components.
3. Leakage reduction in SRAM
It was described earlier that self- controllable switch can
be used either at the upper end of the cell to reduce
supply voltage (USVL scheme) or at the lower end of
the cell to raise the potential of the ground node (LSVL
scheme). The impact of these two techniques on leakage
currents is described in the next sections:
3.1. Leakage control using LSVL
Fig. 2 shows a schematic of an SRAM cell in which
LSVL scheme is applied. The switch provides 0 Volt at
the ground node during the active mode and a raised
ground level (virtual ground) during the inactive mode.
This scheme is similar to the diode footed cache design
scheme proposed to control gate and sub-threshold
leakages in SRAM, in which a diode designed with high
Vt MOS transistors was used to raise the ground level of
SRAM in the inactive mode [8].
Fig. 2: Leakage currents in SRAM cell after applying LSVL.
Let us consider the impact of this approach on gate
leakage first. An increase in the virtual ground voltage
(Vs in Fig. 2), results in decrease of gate-source and
gate-drain voltages of transistor M1 and gate-drain
voltage of transistor M2 and results in sharp reduction in
gate leakage currents of these two transistors. However,
there is no improvement in gate leakage currents for
transistors M5 and M6. In fact, as a result of increase in
drain voltage of M1, a new gate leakage current appears
in transistor M5 as indicated in Fig. 2. Incorporation of
SVL results in another new gate leakage current through
NMOS transistor NL1 in the SVL switch. Although only
one transistor is normally used for one bank of SRAM
cells, leakage current through it is not necessarily
negligible because its size has to be much larger than
NMOS transistors within the SRAM cell to avoid
performance degradation in the active state. As far as
subthreshold leakage currents are concerned, LSVL
approach is successful in reducing currents through M3,
M2 and M5 as well. To summarize, one notes that while
all subthreshold currents are reduced using LSVL
approach, it is only partially successful in reducing gate
leakage currents.
3.2 Leakage control using USVL
An SRAM cell incorporating a USVL scheme is shown
in Fig. 3 along with its impact on leakage currents
through different transistors. In this scheme, a full supply
voltage is applied to SRAM in active mode, while the

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 supply voltage level to SRAM is reduced to voltage level Vdd
Vd in inactive mode. Since transistor M4 is in on state,
voltage at the drains of M2 and M4 is also reduced to
Vd. As before let us consider first the impact on gate NU1
leakage currents. As a result of a decrease in gate voltage
CLK
of transistor M1, gate leakage current through it is PU1 NU2
sharply reduced. A decrease in drain voltage of transistor
M2 results in lower gate-drain voltage across it and thus
Vd
gate leakage current through it is also reduced. A
decrease in source voltage of M6 results in a decrease in
one component of EDT leakage across it while leaving M3 M4

the other unchanged. Gate leakage across transistor M5

remains unchanged. Transistor PU1 being a PMOS Vdd 0V
M5 Vd Vdd
transistor does not result in any significant added leakage M6
current as a result of transistors used in UVSL circuit.
M1 M2
One thus sees that USVL scheme has a better impact on WL='0'
WL='0'
gate leakage current reduction than the LSVL scheme.
BITB
However, this scheme is inferior with respect to BIT
subthreshold leakage current. While, subthreshold
leakage through transistors M3 and M2 is reduced,
un-reduced gate un-reduced sub-threshold
leakage across transistor M5 remains unaltered. Further, leakage leakage
a new subthreshold leakage current appears in transistor
M6 as a result of reduction in its source voltage.
reduced gate
To summarize, the USVL approach, while more leakage
reduced sub-threshold
successful in reducing gate leakage current, still leaves leakage
two gate leakage current components in access
transistors unaltered. It also leaves one subthreshold extra gate extra sub-threshold
leakage leakage
current component in access transistor unchanged and
results in an additional subthreshold leakage current Fig. 3: Leakage currents in SRAM cell after applying USVL.
across the other access transistor. One thus notes that
leakage currents in access transistors are not adequately
Vdd
addressed through the USVL approach shown in Fig. 3.
The importance of leakage current through access
NU1
transistors can be gauged from reports [6] that it
contributes about 20% of the total off-state leakage in an PU1
CLK='1' NU2
SRAM. This estimate was however obtained for the case
where only sub-threshold leakage current in transistors Vpre='1'
was considered to be important. The importance of Vd
PreM1 PreM2
leakage current through access transistors becomes even M3 M4
greater when gate leakage current is considered along
with sub-threshold leakage current. As a result, a leakage Vd1 0V Vd
M5 Vd2
current reduction approach must address currents M6
through access transistors as well. These currents can be M1 M2
WL='0'
significantly reduced if along with reduction in supply WL='0'
voltage to the cross coupled inverter pair, the bit lines are
made floating by putting the pre-charge transistors in BIT BITB
cut-off. A mechanism for implementing this idea is
shown in Fig. 4. This scheme was used in [6] to lower reduced gate reduced sub-threshold
leakage leakage
the sub-threshold leakage in access transistors along with
that in SRAM latch, by gating the pre-charge signal with extra gate
leakage
the wake up signal. In the active mode, the pre-charge
Fig. 4: Leakage currents in SRAM cell after applying USVL
transistors will work on full Vdd supply voltage, as for and making the bit lines floating (USVL-A scheme).
SRAM cell. By putting the pre-charge transistors in off

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 state in the inactive mode, the bit-line node voltages float Vdd
(voltage levels Vd1 and Vd2 in Fig 4.) and thus the
leakage currents are reduced. Fig. 4 shows that all
components of gate and subthreshold leakage are USVL Switch
reduced using this approach.
Vd
4. Static noise margins
The static noise margin (SNM) in active mode will
remain unchanged if the size of transistor NL1 in LSVL
circuit and transistor PU1 in USVL circuit is kept - Vn +
sufficiently large so that voltage across SRAM cell is not
significantly reduced in the active mode of operation. 0V Vd
However, one also notes that noise margin is worst under
read operation [9] and is more sensitive to ground - Vn +
potential than the supply voltage. As a result, USVL
approach has a greater noise immunity in principle than
the LSVL approach.
The static noise margin in inactive mode
(ISSNM) changes much more when leakage current Fig. 5: Static Noise Margin of SRAM latch
reduction techniques are applied. For the USVL-A during inactive mode (ISSNM).
technique described in Fig. 4, the inactive mode SNM is
measured by determining the minimum noise voltage
that is required to flip the state of the SRAM as
illustrated in Fig. 5. Since leakage currents decrease 5. Results
monotonically with decrease in supply voltage Vd and
ISSNM also reduces as the value of Vd is reduced (either The leakage currents in the conventional and the
by increasing the number of NMOS transistors in the schemes suggested in sections 3.1 and 3.2, at two
USVL switch or by varying their sizes), the maximum temperatures of 27qC and 100qC are shown in Table 1,
reduction in leakage that can be obtained is determined when effective supply voltage to the SRAM was reduced
by the minimum acceptable noise margins. It has been from 0.8V to 0.4V in each case.
reported that supply voltage can be reduced from 1V in The gate leakage being the only dominant mechanism at
active state to as low as 0.3V in inactive mode and still room temperature, LSVL scheme suppresses the total
obtain reliable operation of SRAM [6], [10]. leakage by 59.8%, while USVL scheme without
changing bit-line voltages provides a leakage reduction
of 69.7%, and when the bit-lines are made floating
during the inactive mode and USVL is applied to the
SRAM latch (USVL-A scheme), 93.4% reduction in the
overall leakage currents was achieved.

Table 1. Leakage currents in SRAM Cell for different leakage reduction schemes at temperatures of 27 qC and 100

Temp M1 M2 M3 M5 M6 Icell % Reduction

(qC) (nA)
Igate Igate Isub Isub Igate Isub Igate Igate Isub Overall
(nA) (nA) (nA) (nA) (nA) (nA) (nA)
Conven. 27 37.1 13.92 0.86 0.56 9.84 0.6 19.56 83.6 - - -
100 41.1 13.8 20.95 10.89 9.84 14.48 19.6 131
LSVL 27 2.35 1.08 .17 0.29 10.68 - 19.44 33.6 58.28 77.2 59.8
100 2.67 1.14 5.17 6 10.64 0.8 19.49 44.6 59.2 74.1 65.9
USVL 27 2.38 1.14 0.58 - 9.84 0.6 10.64 25.31 70.15 41.58 69.7
100 2.56 1.14 14.57 1.55 9.84 14.5 10.64 54.89 71.3 33.9 58.09

USVL-A 27 2.78 1.14 0.58 - 0.32 0.32 1.2 5.49 93.4 55.45 93.4
100 2.56 1.14 14.55 1.56 7.88 7.88 4.63 32.16 90 48.2 75.45

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 At the elevated temperatures, the sub-threshold leakage 200
rises dramatically while the gate leakage remains almost
constant. Though USVL scheme is more efficient in 180
gate leakage suppression but because LSVL scheme is
better for sub-threshold leakage suppression, overall 160
reduction in LSVL scheme is more. USVL-A scheme

ISSNM(mV)
still shows significant better performance as compared 140
to either of these schemes as indicated in table1. The
table also shows that as the supply voltage reduces, the 120

gate leakage reduces more rapidly as compared to the

sub-threshold leakage. The supply voltage to SRAM 100

was lowered to 0.33V (about 50% higher than the

80
threshold voltage) at 27qC by varying the number of
diode-footed transistors in the switch (at this design, the 0.30 0.35 0.40 0.45 0.50 0.55 0.60
effective supply voltage at 100qC was observed to be Reduced Supply Voltage(V)
0.4V) and a total leakage reduction of 95.97% (75.45%
Fig. 7: Variation of ISSNM as the supply voltage to
at 100qC, for this design) was achieved. The percentage
SRAM is varied for USVL-A scheme.
reduction in the leakage currents for USVL-A scheme is
shown in Fig. 6.
6. Conclusions
An analysis of leakage currents in SRAM cells for a
100
45nm device technology shows that both gate and
subthreshold leakage currents contribute significantly to
%reduction in total leakage overall leakage power dissipation in inactive state.
95
Reduction in supply voltage and elevation of ground
potential using self-controllable switches for reducing
90 leakage currents in SRAM was examined in detail. It
% reduction

was found that while the LSVL approach is better in

85 terms of reduction in subthreshold leakage current, the
USVL approach performs better with respect to gate
leakage currents. However, both these techniques were
80
found to be inadequate for reduction of leakage currents
through access transistors. A modified USVL approach
75 (USVL-A) in which pre-charge transistor is put in off
state during the inactive state was found to be very
70 effective in reducing all significant components of
leakage currents. Results show that 95.97% reduction in
0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 the total leakage currents was achieved at 27qC, when
Pseudosupply voltage - Vd(V) supply voltage during the inactive state was lowered to
0.33Volts and reduction of 75.45% in total leakage
Fig. 6: Plot shows the variationof %reductionin leakagecurrents currents was achieved at 100qC for the same design.
0
as Vd isvariedforUSVL-Ascheme (at 27 C).)
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