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Substrate Models
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Note that the proposed chip-level substrate modeling Lp Rp
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technology with the F-matrix computation considerably re-
duces the size of the nodal matrix of a chip-level resistive Vdd Cs
mesh network in an error-free way, except for round-off er-
rors in actual computing. Vsub (n-2)T (n-1)T nT (n+1)T
2.2. Digital substrate noise injection modeling Figure 3. Capacitances parasitic to logic el-
ements switch (a) in rise and (b) in fall.
The leakage of voltage bounce on power-supply/return (c) Time-series divided parasitic capacitance
rails into a substrate is the most dominant source of sub- (TSDPC) model.
strate noises in large-scale digital circuits [7]. This fact nat-
urally indicates that a precise expression of power-supply
current waveforms in digital circuits must be key in simu-
lating the substrate noise injection, since the interaction of
(a) CMOS (b) SGW
the current with power-supply parasitic impedance results
Nwell z0 z1
in the bounce. VDD&Nwell
z0 z1 Cj z0 z1
VDD
We have developed a time-series divided parasitic capac- Cp Cp
TSDPC TSDPC Cp
itance (TSDPC) model shown in Fig. 3(c), where a digi-
tal circuit is equivalently expressed as a series of capaci- z0 z1 GND z0 z1
GND&Psb Noise Cj
z0 z1
tors to be charged by an external power source [8]. Groups injection Psb
Vsub (mV)
20 RSB2,3
RSB1
SGW 10
0
-10
20 Measured
RSB1
Vsensor (mV)
CMOS
RSB2 0
RSB(1)-(3)
RSB3 -20
CLK
0 10 20 30 40
time (ns)
Figure 6. Simplified ground wiring system.
Figure 8. Substrate noise waveforms of con-
ventional and reduced-substrate noise CMOS
circuits.
V DDA z z V DD
Detector TSDPC
TSDPC
TSDPC
VGNDA
z z V GND Simulated Measured
60
Substrate Voltage p-p [mV]
50
CMOS
Figure 7. System-level substrate noise simu- 40
CMOS
lation model.
30
RSB(1)
20 RSB(2)
RSB(3)
10 RSB1
in Fig. 7 is described in a SPICE compatible netlist, which RSB2,3
includes the chip-level substrate model, noise source cir- 0
2 4 6 8 10 2 4 6 8 10
cuits (TSDPC models), a noise detector, and external power N Blk
sources. We inserted an inductor of 1 nH and a resistor of
1 Ω in series to every connections between ports and power Figure 9. Peak-to-peak noise amplitudes ver-
sources as well as the system ground, in order to involve sus number of active noise source circuits.
parasitic impedance networks resulting from the chip as-
sembly.
Figure 8 shows substrate noise waveforms simulated
with the model by a SPICE simulator and those actually
measured in a 100-ps 100-µV resolution by the measure- ing from the conventional CMOS noise sources, which lo-
ment system that we have established on a mixed-signal cate most distant from the detector as shown in Fig. 5(a).
IC tester [8]. The noises from the reduced noise design These analyses costed only 7-MByte memory and 80-sec
using the RSB-CMOS are also shown. Simulated and CPU time per a waveform with a PA8500-440MHz micro-
measured waveshapes are well consistent especially in pri- processor.
mal frequency components correlating with the clock edges Figure 9 compares simulated and measured peak-to-
and peak-to-peak noise amplitudes. Differences in detailed peak noise amplitudes for different numbers of active noise
structure arise dominantly from the simplified models of source circuits, which match roughly with the error of 10%.
parasitic impedance networks. We found the attenuation Note that the noise amplitude in the RSB-CMOS seems to
ratio of roughly 9.5 dB for the substrate noise propagat- be smaller than the lower limit of the measurements due to
Acknowledgments
References