Discrete and Continuous Substrate Noise Spectrum

Dependence on Digital Circuit Characteristics

Enrique Barajas, Luis Elvira*, Miguel A. Méndez, Ferran Martorell, Diego Mateo, José Luis González
Electronic Engineering Department, Universitat Politècnica de Catalunya
C/ Jordi Girona 1-3, Campus Nord – C4, ES-08034 Barcelona, Spain
e-mail: jlgonzalez@eel.upc.es

Abstract—This work presents an experimental spectrum, respectively. In [2] it is investigated how the substrate
investigation about the relation between specific noise spectrum is affected by some specific characteristics of the
characteristics of a digital circuit (clock frequency and digital circuit, but only the discrete term is considered and
architecture) and the substrate noise spectrum that it capacitive coupling of switching outputs to the substrate is the
generates. Both the discrete impulse train term and the only substrate noise source considered. In this work we extend
continuous term of the substrate noise spectrum are that analysis to include both terms of the spectrum with realistic
investigated. The results indicate that the continuous term dI/dt substrate noise generation. Specifically, we present new
sets an upper bound to the substrate noise reduction that may results concerning the continuous term.
be obtained by changing the digital frequency or by
staggering the simultaneous activity of the circuit, two
techniques that have been proposed in the literature to
II. TEST CHIPS DESCRIPTION
reduce substrate noise. Two test chips are used in this investigation. Both chips have
been manufactured in a conventional 3 metal, 2 poly 0.35µm
I. INTRODUCTION CMOS process on high resistivity p substrate wafers. The first
′ test chip (NOISE_GEN, Fig. 1 left) contains a substrate noise
Substrate noise generated by digital circuits and its coupling to
generator: a digital circuit composed of 4 identical blocks (see
sensitive analog blocks is an important problem in nowadays
Fig. 2), each block containing two stacks of eight three-stage
mixed-signal integrated circuits [1]. The dominant source of
tapered inverter chains [4]. The output of the last inverter of each
substrate noise is the dI/dt noise generated by the switching
chain in a stack is connected to a load of 1.5 pF (which
current transients at the digital power supply lines. This noise is
corresponds to the parasitic capacitance of an output pad). Each
injected into the substrate through the local digital biasing
block receives a separate clock as input. The clock signal is
contacts that are connected to the digital supply lines and it is
distributed from the external clock input by using a clock tree
propagated to the sensitive circuitry. A simple model of substrate
with four controllable slew-rate buffers leaves. The four buffers
noise is composed by a noise injection source (the digital
providing output clocks clk_a to clk_d have been sized
switching current) along with a transfer function from that source
differently. In this way, with a single analog control signal (delay
to the substrate [2]. For a digital circuit, the switching current
control), the switching of the four clock tree leaves can be
waveform can be considered to be a cyclostationary stochastic
staggered. We use this mechanism to model a change in the
process. The switching current waveform is characterized by two
digital circuit architecture: from very parallel to more serial. The
additive components: a periodic waveform (the periodic cycle to
chip is encapsulated in a ceramic 28 pins DIL package.
cycle ensemble average or mean of the switching current
waveforms) and a non-periodic cycle-to-cycle variation
waveform (the difference between the actual waveform during
each cycle and the ensemble average waveform) [3]. Each of
these two components produces different spectral terms. The
periodic ensemble average component gives rise to a discrete
impulse train in the frequency domain (the Fourier transform of
the order 0 cyclic autocorrelation of the cyclostationary process),
with the impulses separated by multiples of the clock frequency.
The departure-from-the-mean waveform gives rise to a
continuous term in the frequency domain (the Fourier transform
of the switching current waveform covariance function, which is Fig. 1. Test chips: NOISE_GEN (left) and DAC (right).
non-periodic). The characteristics of the substrate noise
The second test chip (DAC) is a 12-bit current-steering digital-
waveform and its spectrum are a linear transformation of the
to-analog converter with a segmented architecture of 8
characteristics of the digital switching current waveform and its
thermometer bits and 4 binary bits (Fig. 1, right) [5]. In this work,
only the combinational input decoder of the DAC, which is
composed of 400 gates from a standard cell library, is used. The
* ′Now at Philips Research, Eindhoven, The Netherlands

0-7803-8834-8/05/$20.00 ©2005 IEEE. 4273

Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:32 from IEEE Xplore. Restrictions apply.
rest of the DAC circuitry is disabled by setting the LATCH &
SWITCHES block clock signal to a fixed logic level. The DAC
chip is encapsulated in a CQFP64 package.
Fig. 2. Digital noise generator block diagram.
Both test chips contain the same substrate noise sensor with
dedicated supplies. The sensor is based on a two stage amplifier
shown in Fig. 3. This very simple topology provides low gain,
but enough bandwidth to measure substrate noise waveforms
externally up to 1 GHz of frequency [4]. In the DAC test chip the
substrate noise sensor is connected to the substrate through a p+
diffusion contact in the location indicated with a circle in Fig. 1,
right. In the NOISE_GEN test chip substrate noise is sensed close
to the noise generator block. The amplifier sensing input can be
switched to an external calibration input pin. In this way, the gain
and bandwidth of the amplifiers have been characterized in order
to calibrate the noise measurements.
biasing Input stage Output stage
M3
DC blocking Vai 0.6/60 M2
40/0.3
112.5/2 M5
Vent
M4
M1 Vbuf
Vsen Vbi 0.6/60 80/0.3
M6
Fig. 3. Substrate noise sensor schematic.
III. DIGITAL CLOCK FREQUENCY
A way of obtaining a frequency-band free of substrate noise
impulses is to increase the clock frequency of the digital circuit
[2]. In this section we check the effects of this technique on the
discrete term and we also analyze its effects on the continuous
term of the substrate noise.
A. NOISE_GEN test chip results
The first test chip NOISE_GEN has a single digital input
connected to a clock source that drives all the inverter chains.
This implies that there is no cycle to cycle variation in the circuit
activity. Therefore, only the impulse train term of the substrate
noise spectrum is obtained. In the first experiment, the delay
control signal is set at its maximum, what implies that all the sub-
blocks are switching simultaneously. Figure 4 shows a typical
waveform measured with the substrate noise sensor. The output
of the noise sensor is connected to a digital sampling oscilloscope
with a sampling frequency of 2 Gsamples/second. The measured
waveform shows two noise bursts, due to the rising and falling
edges of the Clock signal, respectively.
Figure 5 shows an FFT of the previous waveform for different
clock frequencies (fClock). The amplitude of the impulses of the
substrate noise spectrum increases proportionally to the square of
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:32 from IEEE Xplore. Restrictions apply.
fClock and its separation increases proportionally to fClock. The later
characteristic is one of the strategies suggested in [2] to reduce
the effects of substrate noise in a narrow band circuit integrated
in the same die: by separating the impulses, a clean frequency
band is obtained between the impulses, where the RF or analog
circuit can safely operate. This requires usually a high frequency
digital clock.
Fig. 4. Substrate noise waveform measured by the substrate noise
sensor of NOISE_GEN test chip.
100/0.3
Vout
30/0.3
Fig. 5. Substrate noise spectrum of NOISE_GEN test chip for three
different clock frequencies.
B. DAC test chip results
Little attention has been devoted in previous works to the
continuous term of substrate noise spectrum, which is present
between the impulses. A second experiment is performed with
the DAC circuit to investigate it. A long pseudo-random
sequence of input vectors is applied to the DAC input decoder at
different data rates (fDATA). Substrate noise is measured as
explained previously. The results plotted in Fig. 6 clearly show
the two terms of the substrate noise spectrum. As the data rate is
increased, the discrete term impulses are separated in frequency
and their level increases proportionally to the square of fDATA,
creating frequency bands free of impulses as anticipated by
earlier works. Meanwhile, the continuous term level increases
proportionally to fDATA. Consequently, the frequency bands
between the impulses are really filled with more noise as the data
rate is raised.
C. Discussion
The variation of the clock frequency or data rate has been
proposed in the literature as a technique to reduce substrate noise
impact on RF circuits in mixed-signal ICs [2]. Increasing the
clock frequency creates wider frequency bands between the
impulses observed in the substrate noise at multiples of the clock
or data rate frequency. The amplitude of the impulses increases
4274
proportionally to the square of the clock frequency (or data rate).
We have shown that between these impulses there is a continuous
term whose level increases linearly with the clock or data rate
frequency, what may limit the usefulness of this technique.
Moreover, package resonances (observed for the DAC test chip at
75 MHz but especially at 190 MHz) have an important impact on
substrate noise, since they raise the level of the continuous term
to levels comparable to the discrete term impulses. In our
experiments we have shown that creating wider bands free of
noise impulses at high frequencies is useless at low frequencies
because the resonances of the package raise significantly the
level of the continuous term (which usually is 20 to 30 dB lower
than the discrete impulse train term at other frequencies).
Fig. 6. DAC decoder substrate noise spectrum.
IV. DIGITAL SWITCHING CURRENT WAVESHAPING
The second substrate noise reduction technique considered is
based in the shaping of the digital switching current waveform.
Substrate noise is mainly due to dI/dt noise, and therefore, an
increase of the switching current rising time (or reduction of the
slope) would reduce substrate noise. A way of doing this is
introducing intentional skew in different clock domains forcing
the several blocks of a digital circuit to switch slightly displaced
in time between themselves instead of very synchronously. This
was done traditionally in output buffers [6] and has been recently
proposed for core logic also [7]. Another way of explaining the
same concept is to consider the skewing as a change in the circuit
operation or architecture from strictly parallel to more serial. In
this section we investigate the impact of this technique in the
substrate noise spectrum.
A. NOISE_GEN test chip results
The delay control signal of the digital noise generator circuit
in the NOISE_GEN test chip allows delaying a different amount
of time the switching for each of the four blocks of the inverter
chains, which modifies the overall digital circuit switching
current rise time. When the signal is at its maximum (3.3 V), the
four blocks switch simultaneously. By decreasing the voltage, the
switching of each block is slightly delayed respect each other in a
progressive way, as indicated in Table 1. Although it is not
possible to directly measure the digital switching current, its
rising slope is directly related with the staggering of the four
4275
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:32 from IEEE Xplore. Restrictions apply.
blocks switching times. The results shown in the table indicate
that the rise time of the switching current (estimated by the
slowest block delayed switching time) is multiplied by 3 for the
rising clock edge noise burst, and by 2.74 for the falling clock
edge noise burst, when the delay control signal is changed from
3.3 V to 0.6 V.
TABLE I
NOISE_GEN BLOCKS DELAYED SWITCHING TIMES (RISING/FALLING)
MEASURED FROM THE INPUT CLOCK
delay
Block 1 (ns) Block 2 (ns) Block 3 (ns) Block4 (ns)
control
3.3 V 2.92/3.28 2.90/3.24 2.90/3.23 2.82/3.15
0.8 V 3.46/4.44 3.66/4.89 4.04/5.52 4.27/5.63
0.6 V 4.97/6.42 5.86/7.55 7.26/8.18 8.61/8.63
Figure 7 shows the substrate noise voltage waveforms
measured in the NOISE_GEN test chip when the delay control
signal is varied. The increase in the rise time of the switching
current clearly reduces the amplitude of the substrate noise. The
duration of the noise burst is not much affected because it is
dominated by the decay time of the damped oscillation produced
after the switching noise impulse. This decay time depends on the
package and circuit R, L and C parasitics, which do not vary.
Fig. 7. Substrate noise waveforms of NOISE_GEN test chip for
different delay control signal voltages.
The results shown in Fig. 8 for different delay control signal
values indicate that the high-frequency content of the substrate
noise spectrum discrete term is reduced proportionally to the
increase of the switching current rising/falling time. In our expe-
riment, 30dB of reduction is obtained for high frequencies when
the switching current rise time is multiplied by a factor of 3.
Conversely, the low frequency content of the noise is not much
affected (the first 7 harmonics are reduced by less than 10 dB).
B. DAC test chip results
In the DAC test chip an investigation of the skewing effects of
the different input bits has been done. A long pseudorandom
sequence of 12-bits vectors is applied to the input decoder at a
data rate of 8.33 MHz (each 120 ns). In different experiments the
bits of each data vector are switched with different skewing
schemes: 12 bits simultaneously switching at the beginning of
each 120 ns cycle, 6 bits first and 6 bits after 10 ns, 3 bits first, 3
delayed 10 ns, 3 delayed 20 ns and the last 3 delayed 30 ns, and
finally, each of the 12 bits of the data vector switching
individually 10 ns after the previous one. All this is equivalent to
operate the circuit in a progressively more serial way. Results are
shown in Fig. 9.
Fig. 8. Substrate noise in NOISE_GEN test chip for different delay
control signal voltages.
Fig. 9. Substrate noise spectrum of DAC test chip for different input bits
skewing.
C. Discussion
This second substrate noise reduction strategy is based on the
staggering of the switching of several sections of the digital
circuit (it is equivalent to introduce skew in the clock). The
results presented in our investigation indicate that this technique
is useful for high frequencies. However, the low frequency
content of the substrate noise spectrum is not reduced
significantly. Moreover, the continuous term of the spectrum,
which depends on the cycle to cycle variations of the digital
switching current, is not affected by this technique, as shown in
Fig. 9, setting a lower limit for the discrete term impulses
reduction.
4276
Authorized licensed use limited to: University of Central Florida. Downloaded on November 8, 2008 at 21:32 from IEEE Xplore. Restrictions apply.
V. CONCLUSIONS
We have presented substrate noise measurements on two test
chips in both time and frequency domains. The results obtained
allow a better understanding of the characteristics of substrate
noise and its relation with the digital circuits that generate such a
noise. This understanding is very important in order to find
strategies to reduce substrate noise impact on sensitive analog
circuits integrated in the same die and to study its effectiveness.
In this work, two techniques which are claimed to reduce
substrate noise impact in mixed-signal IC’s are analyzed. They
have shown to be useful in reducing the substrate noise content in
the sensitive circuit operating band, that is, at high frequencies,
but not so helpful in reducing it at low frequencies. Non-
linearities found in most analog circuits, specially in RF circuits,
may up-convert substrate noise from low frequencies to the RF or
IF bands or to phase noise sidebands around the local oscillators
frequency. Therefore, substrate noise characteristics at low
frequencies are also very important.
The continuous term of the substrate noise depends on cycle to
cycle variations and not only on the average activity of the digital
circuits. We have shown that it is not reduced by the use of
skewing or architectural solutions, so it should be considered and
predicted efficiently. Package-circuit co-design must predict and
eventually modify the resonances which may raise the substrate
noise content at particular frequencies, making in some cases the
continuous term as important as the impulse train term around
those frequencies.
ACKNOWLEDGMENT
This work has been supported by Spanish MCyT and EU
FEDER funds under project TIC 2001-2337, and CONACYT
grant 128878.
REFERENCES
[1] Paul van Zeijl, et al, “A Bluetooth Radio in 0.18-µm CMOS,” IEEE
J. of Solid-State Circuits, Vol. 37, No. 12, pp. 1679-1687, December
2002.
[2] Min Xu, David K. Su, Derek K. Shaeffer, T.H. Lee, and Bruce A.
Wooley, “Measuring and Modeling the Effects of Substrate Noise on
the LNA for a CMOS GPS Receiver,” IEEE J. of Solid-State
Circuits, Vol. 36, No. 3, pp. 473-485, March 2001.
[3] Robert C. Frye, “Integration and Electrical Isolation in CMOS
Mixed-Signal Wireless Chips,” Proceedings of the IEEE, Vol. 89,
No. 4, pp. 444-454, April 2001.
[4] Ferran Martorell, “Aportació a la modelació i anàlisi de l'acoblament
a través del substrat en circuits integrats CMOS,” PCS Thesis, U.
Politècnica de Catalunya, 2001.
[5] Miquel Albiol, Eduard Alarcón, and José Luis González, “Improved
Design Methodology for High-Speed High-Accuracy Current
Steering D/A Converters,” Proceedings of DATE Conference, pp.
636-641, February 2003.
[6] R. Senthinathan, and J.L. Prince, “Application Specific CMOS
Output Driver Circuit Design Techniques to Reduce Simultaneous
Switching Noise”, IEEE J. of Solid-State Circuits, Vol. 28, No. 12,
pp. 1383-1388, Dec. 1993.
[7] M. Badaroglu1, P. Wambacq1, G. Van der Plas, S. Donnay, G.
Gielen, and H. De Man, “Digital Ground Bounce Reduction by Phase
Modulation of the Clock,” Proceedings of DATE Conference, pp. 88-
93, February 2004.