CH8 DAC ADC Fundamrntal

DAC & ADC Testing Fundamental
2009/6/2
MSIC D&T Lab., Dept. of El. Eng., NYUST ~ CW Lin
2
Outline
Specifications of DAC
Specifications of ADC
Test methodology
Static specification
Histogram method
Transfer (and compare) method
Dynamic specification
FFT
Polynomial Fitting
2009/6/2
3
Resolution and Accuracy
Resolution is a design parameter rather than a performance
specification. It only indicates what the theoretical accuracy
can be, it does not imply accuracy to a given level
Accuracy is used to describe how close a converter comes to
meeting its theoretical resolution
Accuracy in a converter is limited by
Theoretical quantization noise
Non-linearity in the transfer function
Additional sources of noise in the converter circuitry
Digital
codes
input
Analog
signal
output
D/A
Analog
signal
input
Digital
codes
output
A/D
2009/6/2
4
Introduction of DAC
Characteristic curve
7
6
5
4
3
2
1
0
000 001 010 011 100 101 110 111
Analog Output
Digital Code
=
n
i
i
i
S F out
D
V A
1
. .
2
, where D
i
is input code
2009/6/2
5
FSR and LSB Size
FSR (Full Scale Range)
The maximum extremes of output signal for a DAC
Current or voltage
Devices whose output does not cross through 0 are
called unipolar, while those with output polarities are
bipolar
LSB (Least Significant Bit) size
Ideal LSB is calculated from the specified FSR
When testing, an LSB is an expected average value
based on the actual length of the transfer curve
] [ ] [
.
Scale Zero Output Measure Scale Full Output Measure FSR Actual
Specs by Specified FSR Ideal
=
=
2009/6/2
6
General Specifications of DAC
Static specifications
Offset error
Gain error
Differential non-linearity (DNL)
Integral non-linearity (INL)
Monotonicity
Dynamic specifications
Settling time
Maximum conversion rate
Rising/Falling Time
Clock Feedthrough
Power Supply Rejection Ratio (PSRR)
2009/6/2
7
Specifications of Special DAC
For current output DAC
Compliance test
For video DAC
Glitch Impulse test
For high resolution DAC
SNR/THD/SFDR test
For multi-DACs
Crosstalk/Match test
2009/6/2
8
Offset Error
Difference between the ideal and actual DAC output values when
the zero or null level digital input code is presented to the device
Caused by comparator input offset voltage or current

Expressed in %FS or in fractional LSB
Output Scale Zero Ideal Output Scale Zero Measured Error Offset =
7
6
5
4
3
2
1
0
000 001 010 011 100 101 110 111
Analog Output
Digital Code
Offset
Error
2009/6/2
9
Gain Error
Difference between the measured output when full scale
input code is presented and the ideal full scale output
Caused by errors in reference voltage, ladder resistor

values, or amplifier gain,
FSR Ideal Error Offset Output ull Scale Measured F Gain Error =
7
6
5
4
3
2
1
0
000 001 010 011 100 101 110 111
Analog Output
Digital Code
Scale Factor Error
2009/6/2
10
Differential Non-Linearity (DNL)
DNL is defined as the difference in the output voltage at a
specific input as compared to the output at the previous
input minus 1 device LSB
( ) ( ) [ ]
1 2 0 1
1
=
=
n
real real
i
, i
LSB
i - V i V
DNL K
7
6
5
4
3
2
1
0
000 001 010 011 100 101 110 111
Analog Output (LSB)
Digital Code
DNL
1
=1LSB
DNL
5
=-0.5LSB
( ) ( ) 1 2 0 = =
n
i i
, i DNL Max DNL Sign DNL K
2009/6/2
11
Integral Non-Linearity (INL)
The deviation of the actual converter output from a straight
line drawn between the end points of the converters input-
output transfer function
7
6
5
4
3
2
1
0
000 001 010 011 100 101 110 111
Analog Output (LSB)
Digital Code
INL
1
=1LSB
INL
6
=-1LSB
( ) ( ) [ ] ( )
1 2 0 = = =
n
real ideal real
i
i, i
LSB
i V
LSB
i - V i V
INL K
( ) ( ) 1 2 0 = =
n
i i
, i INL Max INL Sign INL K
2009/6/2
12
Monotonic
A monotonic curve has no change in sign of the slope
LSB DNL monotonic Non

Monotonic LSB DNL
1
1
<

7
6
5
4
3
2
1
0
000 001 010 011 100 101 110 111
Analog Output (LSB)
Digital Code
Non-monotonic
2009/6/2
13
Settling Time (I)
Input code from 0 to full scale (dependent on devices)
Output settles to within settling band, e.g. 0.5 LSB
Settling time = T
2
- T
1
DAC speed = (Settling time)
-1
Full
Scale
50%
0
Analog Output
Time
Settling Band
Settling Time
T
1
T
2
2009/6/2
14
Settling Time (II)
If slew rate not list in specification
Settling time = Delay time + Slew time + Ring time
Else Settling time = Ring time
[Alternative definition]
2009/6/2
15
Maximum Conversion Rate
Ramp code (0 to 2
n-1
to 0) test with maximun DAC
operating frequency, e.g. 135MHz DAC
Most likely the inverse of time required to change
from zero scale to full scale output
settle
t
Rate Conversion Maximum
1
=
Full
Scale
0
0
Analog Output
Digital Code
2
n
-1
0
2009/6/2
16
Rise/Fall Time
Input code from 0 to full scale,
Rising time = T
2
- T
1
Input code from full scale to 0,
Falling time = T
4
- T
3
Full
Scale
90%
10%
0
Analog Output
Time
Settling Value
Rising Time
T
1
T
2
Falling Time
T
3
T
4
2009/6/2
17
Clock Feedthrough
A measurement of clock transition affects output value
Input code = Full Scale
Clock feedthrough = peak-to-peak value of V
out
, e.g., 2mV
pp
or
Full
Scale
Analog Output
Time
V
pp_out
30dB - e.g. , dB in log 20
_
_
out FS
out pp
V
V
2009/6/2
18
PSRR Test
A measurement of immunity of IC to power noise
V
DD
Vout: Full Scale
1
:
:
1
Input code
ex. 100mV
pp
, 20KHz sine wave
ex. 5mV
pp
, like noise
DAC
DD
V pp
out FS
out pp
V
V
V
V
PSRR
DD
_
_
_
=
2009/6/2
19
Compliance Voltage Test
Caused by the increasing of output voltage
Test setup
Load
V
out
DAC
V
out
I
out
F.S.
Current
0.5 LSB
Compliance Voltage
x
Voltage
Source,V
V
out
DAC
+
-
Code
Full Scale
Current
Meter, I
2009/6/2
20
Glitch
Caused by asynchronous switching
I 2I 4I 8I
Code 1000
Load
Vout
I 2I 4I 8I
Code 0111
Load
Vout
-8
-7
Time
Vout
2009/6/2
21
Glitch Test
Input code:
Glitch impulse =
Summation is used in DSP-based ATE
0 100 1 11 0 K K
8 mv
4mv
2mv
0
-5mv
Time
Vout
Settling value
+ 1 LSB
- 1 LSB
2ns 2ns 1.5ns
Area1
Area2
Area3
( )( ) ( )( ) ( )( ) sec 5 . 2 2 5 . 1
2
1
3 2
2
1
6 2
2
1
= + pV mV ns mV ns mV ns
2009/6/2
22
Frequency Domain Analysis
(a) SFDR (spurious-free dynamic rang)
(b) SNR (Signal to noise ratio)
(c) SNDR (signal to noise and distortion ratio)
(d) Dynamic range
(e) Average noise level
Digitizer
Vout:
sine wave
digitized
sine wave
FFT
A
m
p
l
i
t
u
d
e
(
d
B
)
Frequency
(a) (b) (c) (d) (e)
Fundamental
Harmonic
Noise
2009/6/2
23
THD and THD+N
THD (Total Harmonic Distortion)
A ratio of the sum of the amplitude at all harmonic
frequencies to the one at the fundamental frequency
In practice the sum is limited to seven or nine harmonic
terms
A negative quantity
THD+N (Total Harmonic Distortion plus Noise)
Combine the power of noise and the harmonic
frequencies
2009/6/2
24
Dynamic Range
A measure of the capability of detecting small input
signal
For an audio DAC, it indicates the ability to
reproduce low level signals
It is calculated by inverting the polarity of the
THD+N (-60dB input) and adding 60dB
dB) : (unit

=
Power Detectable Minimum
Power Signal
Maximum ge DynamicRan
2009/6/2
25
SNR and SNDR
SNDR (signal to noise and distortion ratio)
A ratio of the amplitude at the fundamental frequency to
the sum of the ones components at all other frequencies
Include noise and distortion
SNR (Signal to noise ratio)
A subset of SNDR, in which the components for
harmonic distortion are not included
For an audio DAC, it can be measured with all input data
set to zero (no fundamental and harmonic frequencies)
(ref: EIAJ CD-DA Std.)
2009/6/2
26
SNR/THD/SFDR Test
Input code: digitized sine wave code
111
100
000
V
out
: sine wave
Full Scale
DAC
Digitized and FFT
2009/6/2
27
Inter Modulation Distortion (IMD)
A test for non-harmonic product terms that appear
in a device signal due to undesired modulation of
two frequency components of a signal
The test is performed by putting a summed two
sinusoid tone into a device and looking for
frequency components in the sum and difference
frequency
Second IMD product terms
are found at (f
1
f
2
)
2009/6/2
28
Crosstalk
V1out: Full Scale
Crosstalk=
V1out
V2out
or
DAC1
DAC2
dB in log 20
_
_
out FS
out pp
V
V
2009/6/2
29
Match
V1out = V2out = Full Scale
Match=
V1out
V2out
DAC1
DAC2
2
2 1
2 1
_ _
_ _
out FS out FS
out FS out FS
V V
V V
+
2009/6/2
30
Introduction of ADC
Characteristic curve
111
110
101
100
011
010
001
000
0 1/8 2/8 3/8 4/8 5/8 6/8 7/8
output code
input level
(1lsb) (2lsb) (3lsb) (4lsb) (5lsb) (6lsb) (7lsb)
F.S.(full scale)
offset
n
i
i
i
S F in
V
D
V A +
=

=1
. .
2
, where D
i
is output code
2009/6/2
31
FSR and LSB Size
FSR (Full Scale Range)
The maximum extremes of output signal for a ADC
Current or voltage
Devices whose output does not cross through 0 are
called unipolar while those with output polarities are
bipolar
LSB (Least Significant Bit) size
( ) ( )
2 2
: 1 Def.
=
N
in
ZST V FST Vin
LSB
N
FSR
LSB
2
: 2 Def. =
V
in
(FST) is the full scale transition point
V
in
(ZST) is the zero scale transition point
2009/6/2
32
Static Specifications of ADC
Offset error
Gain error
Differential non-linearity (DNL)
Integral non-linearity (INL)
Missing codes
Static noise
Hystersis error
2009/6/2
33
Offset Error
The difference between the ideal zero point value
and the calculated zero point value
Usually expressed as LSBs, volts or percentage
of full-scale range (%FSR)
( ) ( )
( ) 0 nt Offset Poi if Ideal LSB ZST Vin
Point Offset Ideal Vin Scale Zero Vin Error Offset
Device
= =
=
5 . 0

2009/6/2
34
Gain Error
It is dominated by errors in the converters
reference voltage
ideal Device
FSR FSR Error Gain =
ideal
real
111
110
101
100
011
010
001
000
0 1/8 2/8 3/8 4/8 5/8 6/8 7/8
output code
input level
F.S.(full scale)
2009/6/2
35
Differential Non-Linearity (DNL)
DNL is the difference between adjacent transition
points in an actual ADC and an ideal one
ideal
real
111
110
101
100
011
010
001
000
0 1/8 2/8 3/8 4/8 5/8 6/8 7/8
output code
input level
F.S.(full scale)
real width
ideal
width
DNL
i
( ) ( ) 1 2 0 = =
n
i i
, i DNL Max DNL Sign DNL K
1 2 0 , 1 = =
=
n
i
i
i
i i
i
i
h ideal widt
real width
h ideal widt
h ideal widt real width
DNL K
2009/6/2
36
Integral Non-Linearity (INL)
A measure of maximum deviation of the actual
transition points in an A/Ds transfer function from
the ideal curve
111
110
101
100
011
010
001
000
0 1/8 2/8 3/8 4/8 5/8 6/8 7/8
output code
input level
F.S.(full scale)
align
INL
1
INL
2
INL
3
INL
4
INL
5
INL
6
( ) ( ) 1 2 0 = =
n
i i
, i INL Max INL Sign INL K
1 2 0 ,
1
1
= = + =

=
n
i
j
i i i i
i DNL DNL INL INL K
2009/6/2
37
Histogram test for DNL and INL
Uses a linearly increasing or decreasing signal as
the input to the ADC under test
A 14 bit ADC
ramp histogram
2009/6/2
38
Missing Code Test
Test Steps: 1. Count the number of each code: n
i
2. Check n
i
> n
th
111
110
101
100
011
010
001
000
output code
Clock Timing
Input Signal: Ramp
Full Scale
2009/6/2
39
Static Noise
Definition
Little concern in high-speed applications
Output
h L
Input
k
Sampling
A/D
2009/6/2
40
Hysteresis Error
Hysteresis Error in an ADC causes the voltage at
which a code transition occurs to be dependent
upon the direction from which the transition is
approached
It is usually caused by hysteresis in the comparator
2009/6/2
41
Dynamic Specifications of ADC
SNR and SNDR
Total harmonic distortion (THD)
Inter-modulation distortion (IMD)
Spurious-free dynamic range (SFDR)
Effective number of bits (ENOB)
Dynamic Deviation
2009/6/2
42
SNR and SINAD
SNR is a ratio of the signal amplitude to the noise
level
When the harmonics are included, the S/N
specification is referred to as the Signal-to-(Noise +
Distortion) or SINAD
Both signal-to-noise specifications exclude any DC
offset from the noise component
resolution of bits of number n where

dB n SNR
,
) ( 76 . 1 02 . 6
=
+ =
2009/6/2
43
Total Harmonic Distortion (THD)
THD relates the RMS sum of the amplitudes of the
signal's harmonics to the amplitude of the signal
ADCs produce harmonics of an input signal
because an ADC is an inherently nonlinear device
The THD will decrease if the transfer curve of the
ADC more closely resembles a straight line
2 / 1
2
1
2
3
2
2
+ +
=
f
f f
V
V V
THD
L
where V
f1
is the amplitude of the fundamental
and V
fi
is the amplitude of the i-th harmonic
( ) ( ) ( ) L + + + + =
3
3
2
2 1 0 in in in OUT
V a V a V a a V
( )
2
2 cos 1
cos
2
t
t

+
=
If the output of an ADC is fed to a perfect DAC
2009/6/2
44
Inter-Modulation Distortion (IMD)
IMD results when two frequency components in a
signal interact through the non-linearities in the
ADC to produce signals at additional frequencies
An input signal with frequency components at 600Hz and 1kHz (left)
suffers severe IMD after A/D conversion (right)
2009/6/2
45
Dynamic Range and Spurious-Free Dynamic
Range (SFDR)
Dynamic range is defined as the ratio (usually in dB)
of the maximum signal size to the minimum signal
size
For an ideal ADC, it is 20log(2
bits
-1)
SFDR is the ratio of signal amplitude to amplitude
of the highest harmonic or spurious noise
component
2009/6/2
46
Effective Number of Bits (ENOB)
ENOB is a specification that is closely related to the SNR
The ENOB specification combines the effects of many of the
other dynamic specifications
Errors resulting from dynamic differential and integral non-linearity
missing codes
total harmonic distortion
aperture jitter
02 . 6
76 . 1
=
SNR
ENOB
Some manufacturers define the ENOB
using the SINAD instead of the SNR
ENOB generally decreases at high
frequencies
2009/6/2
47
Dynamic Deviation
Definition
Be used to evaluate dynamic performance of ADC
Output
h L
Input
k
Sampling
A/D
2009/6/2
48
Histogram Test
A statistical number of samples of the input
sinusoid are taken and stored as a record
The frequency of code occurrence in the record is
plotted as a function of code
For an ideal ADC, the shape of the plot would be
the PDF of a sine wave
2 2
1
) (
V A
V P
The PDF of a sine wave

is given by
A is the sine wave amplitude
V is the input voltage
2009/6/2
49
Histogram Test -- DNL
Differential non-linearity
The ideal probability of occurrence
1
) (
(
=
code nth P ideal
nth code) P actual
Linearity Non al Differenti
actual P(nth code) is the measured probability of occurrence and
ideal P(nth code) is the ideal probability of occurrence for code bin n
( ) ( )

N
N
N
N
A
n B
A
n B
n P
2
2 1
sin
2
2
sin
1
) (
1
1
1
1
n is the code bin number

B is the full-scale range of the ADC
A is sine wave amplitude
N is the number of ADC bits
2009/6/2
50
Histogram Test -- Input Frequency and
Example
The input and sample frequencies must be
relatively independent
In realistic, using an input frequency that has a
large common divisor with the sample frequency,
Ideally, the period of the greatest common divisor
should be as long as the record length
Example
A 100,000-sample histogram
for a 9.85MHz sine wave input
All discontinuities are less than
1LSB
2009/6/2
51
Histogram Test -- Examples
Large differential non-linearities and numerous
missed codes are apparent
2009/6/2
52
Histogram Test -- Input Waveform
Sinusoidal waveform is easier to generate
accurately and stably with most signal generator
t
Code
Bin
255
0
1
Code
Bin
255
0
1
t
t
Code
Bin
255
127
Code
Bin
255
t
127
Code
Number of
Occurence
Number of
Occurence
Code
0 255
0 255
2009/6/2
53
FFT Test -- Setup
Basic principle
Evaluation system
2009/6/2
54
FFT Test -- Spectrum Interpretation
Fundamental
Non-linear Distortion
from A/D C
Quantization Error
form A/D C or digitizer
Random Noise
Uncertainty:
Timing J itter
Phase Noise
Aperature Error
FFT Spectrum obtained
from A/D C output
2009/6/2
55
FFT Test -- Example
FFT plots for 0.85MHz data quantized by perfect (a)
10-bit and (b) 6-bit ADCs
SNR = 6.02n + 1.76
(a) (b)
2009/6/2
56
FFT Test -- Example (cont.)
Distortion increases with increasing frequency
FFT plots for the input frequencies of (a) 9.85MHz
and (b) 0.95MHz
(a) (b)
2009/6/2
57
Case Study
3.3V 8bit 135MHz Video D/A C
HI5741-14bit DAC
2009/6/2
58
Test Circuit
Vcca
Gnda
Out
Out
D 7
.
.
.
D 0
Vddd
Gndd
Clk
Vref
Vcomp
DPS2_GND DPS1_GND
10
PMU2
0.1
DPS1_P(3.3V)
0.1 10
DPS1_GND(0V)
MEASURE1_1
VHFMEAS1_1
Digital
Pin
DPS2_GND(0V)
DPS2_P(3.3V)
3
.
3
V

1
3
5
M
H
z

8
b
i
t

D
/
A

C
?
?
?
1
2
3
Digital
Pins
2009/6/2
59
Linearity Test
D/A C output for digital ramp code input
DNL = -0.172 lsb
INL = -1.228 lsb
2009/6/2
60
Timing Test
Settling, Rising, Falling time
Rising time = 2.5ns
Falling time = 3 ns
Settling time = 20 ns
with 1lsb settling band
2009/6/2
61
Clock Feed Through Test
Impedance unmatching
Clock feed through Vp-p = 25mV
Clock feed through = -31.66 dB
2009/6/2
62
Glitch Impulse Test
Glitch impulse
= 0.51 pVsec.
Since this is a
Segment D/A C
0.25 lsb
2009/6/2
63
PSRR Test
Vp-p = 7.33 mV
Vout = 718mV
PSRR = 0.337 %/%Vdd
Power supply modulated by
20KHz, 100mVp-p sine wave
2009/6/2
64
SNR/THD/SFDR Test
Input code: digitized sine wave code
FFT
SFDR: 62.11dB
SNR: 49.45 dB
THD: -58.38 dB
Fin = Data rate x cycles / #points
Fin/Fs = M cycles / 2
n
2009/6/2
65
18.43
18.44
18.45
18.46
18.47
18.48
18.49
18.50
18.51
0.00 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60
Output Voltage
O
u
t
p
u
t

C
u
r
r
e
n
t

(
m
A
)
Full_I = 18.5 mA
Compliance Voltage
=1.7 V
2009/6/2
66
Case Study
3.3V 10bit 30MHz A/D C
AD9240-14bit ADC
2009/6/2
67
Test Circuit
AGND
DRVDD
D0
:
:
D9
(MSB)
DRGND
DGND
CLK
AVDD
VIN
VRLS
VRLF
VRHF
VRHS
DVDD
10
DPS1_GND
Digital
Pins
0.1
DPS1(3V)
DPS2(3V)
Source 1-1
DPS1(3V)
Digital Pin
PMU2(2V)
PMU1(0V)
10 0.1
Source 3-1
DPS2_GND DPS1_GND
10 0.1
3
.
3
V

1
0
b
i
t

3
0
M
H
z

A
/
D

C
2009/6/2
68
Linearity Test
A/D C output for Triangle wave input
Overflow
Underflow
2009/6/2
69
DNL Test
Statistic Analysis
#148
DNL
2009/6/2
70
INL Test
INL
2009/6/2
71
SNR/THD/ENOB Test
1MHz sine wave (with socket)
FFT
SNR :57.98583
THD :65.46822
SINAD:54.92447
ENOB :8.831307
#cycle = 69, #point = 2048
2009/6/2
72
SNR/THD/ENOB Test (contd)
4.43MHz sine wave (with socket)
FFT
SNR :56.50523
THD :63.06194
SINAD:53.15846
ENOB :8.537950
#cycle = 303, #point = 2048
.
2009/6/2
73
SNR/THD/ENOB Test(contd)
10MHz sine wave (with socket)
FFT
SNR :53.77202
THD :74.38521
SINAD:52.99816
ENOB :8.511322
#cycle = 683, #point = 2048
.
2009/6/2
74
Reference (1/2)
Specifying A/D and D/A Converters,National Semiconductor Corp. Application Note
(AN-156), February 1976
Scott Wayne, Getting the Most from High Resolution D/A Converter,Analog Devices
Inc. Appliction Note (AN-313), 1983
The Fundamentals of Mixed Signal Testing,Soft Test Inc.
Larry Gaddy and Hajima Kawai, Dynamic Performance Testing of Digital Audio D/A
Converters,Burr-Brown Corp. Application Bulletin (AB-104), May 1997
J im Williams, Component and Measurement Advances Ensure 16-Bit DAC Settling
Time,Linear Technology Corp. Application Note 74, J uly 1998
Using the Analog to Digital Converter,Microchip Technology Inc. Application Note (AN-
546), 1994
Larry Gaddy, Selecting an A/D Converter,Burr-Brown Corp. Application Bulletin (AB-
098), April 1995
Mark Sauerwald, Designing with High-Speed Analog-to-Digital Converter,National
Semiconductor Corp. Application Note (AD-01), May 1988
Leon G. Melkonian, Dynamic Specifications for Sampling A/D Converters,National
Semiconductor Corp. Application Note (AN-769), May 1991
IEEE Standard for Performance Measurements of A/D and D/A Converters for PCM
Television Video Circuits,ANSI/IEEE Standard 746-1984
2009/6/2
75
Reference (2/2)
Dynamic Tests for A/D Converter Performance,Burr-Brown Corp. Application Bulletin
(AB-072)
Walt Kester, J ames Bryant, Grounding in High Speed Systems,Analog Devices Inc.
William C. Rempfer, The Care and Feeding of High Performance ADCs: Get All the Bits
You Paid For,Linear Technology Corp. Application Note (AN-71), J uly 1997
Bill Travis, EDN Hands-On Project: Demystifying ADCs,EDN, pp.26, March 27, 1997
Bill Travis, Remystifying ADCsEDN, October 9, 1997
David A. J ohns and Ken Martin, Analog Integrated Circuit Design,J ohn Wiely & Sons,
Inc. 1997
R. W. Stewart and E. Pfann, Oversampling and Sigma-Delta Strategies for Data
Conversion,Electronics & Communication Engineering J ournal, February 1998
Brian Black, Analog-to-Digital Converter Architectures and Choices for System Design,
Analog Devices Inc. Analog Dialogue 33-8, 1999

CH8 DAC ADC Fundamrntal

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

CH8 DAC ADC Fundamrntal

Uploaded by

Copyright:

Available Formats

DAC & ADC Testing Fundamental

Caused by comparator input offset voltage or current

Caused by errors in reference voltage, ladder resistor

LSB DNL monotonic Non

resolution of bits of number n where

The PDF of a sine wave

n is the code bin number

You might also like