Chapter 4: Memory Built In Chapter 4: Memory Built-In

Self-Test Self Test

J in-Fu Li J in Fu Li
Dept. of Electrical Engineering
National Central University National Central University
J hongli, Taiwan
Outline
ROM BIST
RAM BIST
Serial BIST for RAMs Serial BIST for RAMs
Processor-Based RAMBIST Processor Based RAM BIST
RAM BISTs in SOCs
References
2 Jin-Fu Li EE, National Central University
Introduction
Characteristics of todays SOC designs
Typically more than 30 embedded memories on a
hi chip
Memories scattered around the device rather than
concentrated in one location concentrated in one location
Different types and sizes of memories
Memories doubly embedded inside embedded cores Memories doubly embedded inside embedded cores
Test access to these memories from only a few chip
I/O pins p
Built-in self-test (BIST) is considered the best
solution for testing embedded memories within solution for testing embedded memories within
SOCs
It offers a simple and low-cost means without
3 Jin-Fu Li EE, National Central University
It offers a simple and low cost means without
significantly impacting performance
General BIST Architecture
Circuit Under Test
(CUT)
Test
Generator
Response
Verification
Test Controller Test Controller
4 Jin-Fu Li EE, National Central University
ROM Functional Block Diagram
Inputs
Buffer
NOR/NAND NOR/NAND
(ROM Array)
Decoder
Buffer
O t t
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Outputs
An Example of ROM BIST
ROM
C
o
u
ROM
n
t
e
r
MISR MISR
Controller
Status Go/No-Go
6 Jin-Fu Li EE, National Central University
Typical RAM BIST Architecture
Normal I/Os
T t C t ll
RAM
T
e
s
t

C
Test Controller
RAM
C
o
l
l
a
r
Test Pattern
Generator
Comparator
Go/No-Go
Comparator
7 Jin-Fu Li EE, National Central University
RAM BIST
In general, two BIST approaches have been
proposed for the RAMs
FSM-based RAM BIST
ROM-based RAM BIST
Controller
Generate control signals to the test pattern Generate control signals to the test pattern
generator & the memory under test
Test pattern generator (TPG) Test pattern generator (TPG)
Generate the required test patterns and Read/Write
signals g
Comparator
Evaluate the response
8 Jin-Fu Li EE, National Central University
Evaluate the response
ROM-Based RAM BIST
The features of ROM-based BIST scheme
The ROM stores test procedures for generating test
patterns
Self-test is executed by using BIST circuits controlled
by the microprogramROM by the microprogram ROM
A wide range of test capabilities due to ROM
programming flexibility p g g y
The BIST circuits consists of the following
functional blocks functional blocks
Microprogram ROM to store the test procedure
Programcounter which controls the microprogram Program counter which controls the microprogram
ROM
TPG
9 Jin-Fu Li EE, National Central University
Comparator
ROM-Based RAM BIST Architecture
Normal I/Os
Mi
Normal I/Os
E d
T
e
s
t

Microprogram
ROM
End
RAM
C
o
l
l
a
r
TPG
Go/No-Go
Comparator
10 Jin-Fu Li EE, National Central University
March-9N Test Procedure & Microcodes
M h 9N March-9N:
CLEAR
STEP
MICROCODE
0 0 0 0 0 0 0 0 1 0
OPERATION
CLEAR
WRITE(D), INC AC, IF AC=MAX THEN INC PC
READ(D)
WRITE(D), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC
READ(D)
0 0 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 1 0 0
0 0 0 0 0 0 0 1 0 0
1 1 1 0 0 1 0 1 0 0
0 0 0 0 0 1 1 0 0 0
READ(D )
DEC AC
READ(D)
WRITE(D), INC AC, IF AC=MAX THEN INC PC ELSE DEC PC
WRITE(D) DEC AC IF AC=0 THEN INC PC ELSE DEC PC
0 0 0 0 0 1 1 0 0 0
1 1 1 0 0 0 0 1 0 0
0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 0 1 0 0 0
1 1 0 1 0 1 0 1 0 0
STOP
WRITE(D), DEC AC, IF AC=0 THEN INC PC ELSE DEC PC
READ(D)
WRITE(D), DEC AC, IF AC=0 THEN INC PC ELSE DEC PC
1 1 0 1 0 1 0 1 0 0
0 0 0 0 0 1 1 0 0 0
1 1 0 1 0 0 0 1 0 0
0 0 0 0 0 0 0 0 0 1
IF AC=MAX/0
ELSE DEC PC
INCREMENT AC
DECREMENT AC DECREMENT AC
EXCLUSIVE OR
INVERT/NORMAL
COMPARE/MASK
WRITE/READ
11 Jin-Fu Li EE, National Central University
WRITE/READ
CLEAR
TEST END
FSM-Based RAM BIST
Normal I/Os Normal I/Os
E d
T
e
s
t

FSM
End
RAM
C
o
l
l
a
r
TPG
Go/No-Go
Comparator
12 Jin-Fu Li EE, National Central University
FSM-Based RAM BIST
A l f h di f ll An example of the state diagram of controller
S
0
W0
NOT last address?
S
1
R0
NOT last address?
S
2
W1
S R1 S
3
S
4
R1
W0
NOT last address?
S
5
R0
NOT last address?
S
4
W1
S End
13 Jin-Fu Li EE, National Central University
S
4
End
Programmable RAM BIST
A l f h bl RAMBIST An example of the programmable RAM BIST
T
Normal I/Os
CMD
C
o
n
T
P
G

&

C
T
e
s
t

C
RAM
BSI
BSC
CMD
TGO
n
t
r
o
l
l
e
r

C
o
m
p
a
r
C
o
l
l
a
r
RAM
BSC
BRS
ENA
r
a
t
o
r

BGO
DONE
CLK
BNS
CLK
14 Jin-Fu Li EE, National Central University
FSM State Diagram of the Controller
Idle
BRS=1
Shift d
BSC=1
Shift_cmd
BSC=0
DONE=1
Get_cmd
Apply ENA=1
DONE=0
15 Jin-Fu Li EE, National Central University
Programmability
Th bili b hi d b i The programmability can be achieved by using
test command
The test command format

U/D OP Data background

U/D: ascending/descending address
sequence
U/D OP Data background
sequence
OP: test operations
For example, wa, rawa, rawara, warawara, etc. o e a p e, a, a a , a a a, a a a a , etc.
Data backgrounds
Th idth f h fi ld ff t th The width of each field affects the
programmability of the BIST design
F l if 4 bit d f OP th l 16
16 Jin-Fu Li EE, National Central University
For example, if 4 bits are used for OP, then only 16
possible test operations can be generated
FSM State Diagram of the TPG
Idle
ENA=0
Init DONE/GO
ENA=1
Ifetch
Null=1
Null=0
Ifetch
Exec
Dfetch
Compare No-Go
Error=0
Error=1
17 Jin-Fu Li EE, National Central University
Serial BIST
Todays telecommunication ICs often have a
variety if multiport memories on one chip
Typical RAM BISTs evaluate all the bits of a
memory word in parallel as it is read memory word in parallel as it is read
We can encounter significant problems when
applying these BIST schemes to chips that have applying these BIST schemes to chips that have
multiple embedded RAMs of varying sizes and
port configurations port configurations
The area cost of these BIST designs would be
unacceptably high unacceptably high
One better solution is a serial BIST technique
T h BIST d i l RAM
18 Jin-Fu Li EE, National Central University
To share BIST design among several RAMs
Benefits of Serial BIST
Only a small amount of additional circuitry is
required required
Only a few lines are needed to connect the RAM
to the test controller to the test controller
Several RAM blocks easily share the BIST y
controller hardware
The serial-access mode does not compromise The serial access mode does not compromise
the RAM cycle time
E i ti d i d t d Existing memory designs do not need any
modification to use the serial interface
19 Jin-Fu Li EE, National Central University
Serial-Data-Path Connection
C
i
C
i+1
R
o
w

d
e
C
i
C
i+1
e
c
o
d
e
r
Column decoder
Latch Latch
Write
Read
BIST
Latch Latch
BIST on
From previous output
or serial input
To next test input
or serial input
20 Jin-Fu Li EE, National Central University
O
i
O
i+1
I
i
I
i+1
Serial Shift Operation
An example of serial shift operations for the
match element (R0W1)
Time Operation Serial Word Serial
0 0 0 0
Time Operation Serial
in
Word
content
Serial
out
0 X
X
0 0 0 0
1 0 0 0
1 R0 X
2 W1 1
0
0
0 0 0 0
0 0 0 0
1 0 0 0 1 0 0 0
1 0 0 0
1 1 0 0
1 0 0 0
3 R0 1
4 W1 1
0
0
0 0 0 0
0 0 0 0
1 0 0 0 1 0 0 0
1 1 0 0
1 1 0 0
1 1 1 0
6 W1 1
5 R0 1
0
0
0
0 0 0 0 0 0 0 0 1 0 0 0
1 1 1 0
1 1 1 0
1 1 1 1
8 W1 1
7 R0 1 0
0
X
X
X
0
1
0 1 0
21 Jin-Fu Li EE, National Central University
8 W1 1
Serial March (SMarch)
Assume that a RAM has Wwords, and each
word contains C bits
A Read operation is denoted by R0, R1, or Rx,
depending on the expected value at the serial depending on the expected value at the serial
output (x=dot care)
For a write operation the terms W0 or W1 are For a write operation, the terms W0 or W1 are
used and only the serial input is forced to the
value indicated value indicated
The SMarch modified from March C- is as
f ll follows

C C C C
C C C C
W R W R W R W R
W R W R W R RxW
) 1 , 1 ( ) 1 , 0 ( ; ) 0 , 0 ( ) 0 , 1 (
) 1 , 1 ( ) 1 , 0 ( ; ) 0 , 0 ( ) 0 (

c
22 Jin-Fu Li EE, National Central University
C C C C
W R W R W R W R ) 0 , 0 ( ) 0 , 0 ( ; ) 0 , 0 ( ) 0 , 1 (
Serial BIST Architecture
BIST GO Done
Controller
Timing
generator
SO SI
Counters
Control
Data out
Data in
msb lsb
Multiplexer Multiplexer Multiplexer
Data in
Address
C-1
Multiplexer Multiplexer Multiplexer
C C
RAM (Wwords of C bits)
Address Data in Data out Control
23 Jin-Fu Li EE, National Central University
Sharing BIST in Daisy-Chain Style
BIST GO Done
Controller
Timing
generator
SO SI
Counters
g
SO SI
R d/W it Add Read/Write Address
Test Collar Test Collar Test Collar
RAM1 RAM2 RAM3
Test Collar Test Collar Test Collar
Serial Interface
SI SO
Serial Interface
SI SO
Serial Interface
SI SO
24 Jin-Fu Li EE, National Central University
Sharing BIST in Parallel Style
BIST
GO
Done
DeMux
Timing
SO SI
C t
Controller
g
generator
Counters
Read/Write Address
Test Collar Test Collar Test Collar
RAM1 RAM2 RAM3
Test Collar Test Collar Test Collar
Serial Interface
SI SO
Serial Interface
SI SO
Serial Interface
SI SO
25 Jin-Fu Li EE, National Central University
BIST Using Data Decoding/Encoding
n
m wire
n
n
m wire e
26 Jin-Fu Li EE, National Central University
Processor-Based RAM BIST
Normal I/Os Normal I/Os
T
e
s
t

Processor
RAM
C
o
l
l
a
r
TPG
Go/No-Go
Comparator
27 Jin-Fu Li EE, National Central University
NTHU Processor-Programmable BIST
ADDR
ADDR_cpu
DATAO
ADDR_bist
Embedded On-chip Embedded
BIST core
DATAO
DATAO_sys
Clock_cpu
DATAO_bist
Mux_sel
CPU bus Memory
BIST core
control
Ctrl_cpu
Ctrl_bist
DATAI DATAI_sys
DATAI_bist
DATAI_cpu
Source: Prof. C. W. Wu, NTHU
28 Jin-Fu Li EE, National Central University
NTHU Processor-Programmable BIST
BIST core
R
BG
DATAO_cpu
L t/hi h t dd
DATAO_bist
Address
decorder
R
AL
R
AH
R
EA
Address
counter
ADDR_cpu
Lowest/highest addr
ADDR_bist
Up/down
R
ME
R
IR
R
FLAG
R
ED
Controller
Read/Write
Control
Up/down
DATAI_bist
DATAI sys
Match/unmatch
Comparator
Data background
DATAI_sys
29 Jin-Fu Li EE, National Central University
Source: Prof. C. W. Wu, NTHU
NTHU Processor-Programmable BIST
Data registers
Register Function
R
BG
Store background data
R
AL
R
AH
Store lowest address
Store highest address
R
ME
R
IR
Store current March element
Instruction register of BIST circuit
R
FLAG
R
ED
Status register of BIST circuit
Erroneous response of defective cell
R
EA
Address of defective cell
30 Jin-Fu Li EE, National Central University
Source: Prof. C. W. Wu, NTHU
NTHU Processor-Programmable BIST
Source: Prof. C. W. Wu, NTHU
BIST procedure
Test programwrite data background to R
BG
Test program write data background to R
BG
Test program write lowest/highest address to R
AL
/R
AH
Performed by
test program
Test program write March instructions to R
ME
Test program write START to R
IR
(Wa) (Ra,Wa) (Ra,Wa) (Ra,Wa) (Ra,Wa) (Ra)
Compare
Data error
Write ERROR to R
FLAG
Write error response to R
ED
Write faulty addr to R
EA
Performed by
BIST circuit
yes
No
March element
complete
yes
No
31 Jin-Fu Li EE, National Central University
Write FINISH to R
FLAG
Test program
take over
SOC Testing
A typical SOC chip
FPGA
Flash Memory
ADC
Wrapper
DSP
CPU
y
UDL
Sink
Wrapper
Source
Sink
Test Access Mechanism (TAM)
TAM
MPEG SRAM SRAM
DRAM
Source: Y. Zorian, et al.-ITC98
32 Jin-Fu Li EE, National Central University
SOC Test Access
FPGA
Flash
Memory
UDL
ADC
Wrapper
Off-chip Source/Sink
1. Pins determine bandwidth
DSP
CPU
UDL
Source
Sink
TAM
TAM
2. More TAM area
3. Requires expensive ATE
MPEG
SRAM SRAM
DRAM
FPGA
Flash
Memory
ADC
Wrapper
On chip Source/Sink
DSP
CPU
Memory
UDL
Sink
Wrapper
Sink
On-chip Source/Sink
1. Close to Core-under-test
2 Less TAMarea
MPEG
SRAM SRAM
DRAM
Source
Source
2. Less TAM area
3. BIST IP area
4. Requires lightweight ATE
33 Jin-Fu Li EE, National Central University
Source: Y. Zorian and E.J . Marinissen
1500 Scalable Test Architecture
User Defined Parallel TAM Source
Sink
1500 W
TAM-out TAM-in
1500 W
TAM-out TAM-in
Core1
1500 Wrapper
CoreN
1500 Wrapper
Fin
Fout
Fin Fout
Core1
WIR
CoreN
WIR
WSI
WSI WSO WSO
WIR WIR
WSI
WSI WSO WSO
WIP
User-Defined
Test Controller
34 Jin-Fu Li EE, National Central University
1500 Test Wrapper
WW
Test stimuli
Test response
WPI
WPO
Core
W
B
R
W
B
R
Functional
data
Functional
data
WBY
data
data
WIR
WSO
WSI
WSC
35 Jin-Fu Li EE, National Central University
Memories in SOCs
FPGA ADC
DSP
CPU
Flash Memory
UDL DSP
CPU
UDL
SRAM
DRAM
SRAM SRAM
BIST
BIST
MPEG SRAM SRAM
DRAM
BIST BIST
BIST d N BIST
36 Jin-Fu Li EE, National Central University
BIST-ready memory cores Non-BIST memory cores
RAM BIST in SOCs
Memory cores in an SOC can be categorized
into two types in term of testability
BIST-ready memory cores
Non-BIST memory cores
An SOC can contain tens or even hundreds of
memory cores e o y co es
Although a BIST usually have only about 8
controlling pins
The total BIST controlling pins is huge if each BIST-
ready memory cores has its own BIST controlling pins
The BIST controlling pins should be shared
One solution is using memory BIST interface
37 Jin-Fu Li EE, National Central University
g y
Sharing BIST Controlling Pins
FPGA ADC
DSP
CPU
Flash Memory
UDL
DSP
DRAM
SRAM
SRAM SRAM
BIST
BIST
MBI
MBI
MBI
MPEG
SRAM
SRAM
DRAM
BIST
BIST
MBI
MBI
SRAM
38 Jin-Fu Li EE, National Central University
Memory BIST Interface (MBI)
39 Jin-Fu Li EE, National Central University
Memory BIST Interface (MBI)
Instruction Register
Store the instructions
RUN_BIST, RUN_DIAGN, EXPORT_STATUS, TAM_CONTROL
Bypass Register yp g
It is selected if the corresponding memory core is not
tested
Monitor Register
Monitor the error flag (indicating whether a memory o to t e e o ag ( d cat g et e a e o y
fault is detected or not)
Status Register Status Register
Record the key status values, such as Fail output from
the BIST
40 Jin-Fu Li EE, National Central University
Testing Multiple Memories with MBI
Using RUN_BIST instruction, we can test multiple
memory cores concurrently memory cores concurrently
When one or more BIST circuits detect faults, the primary
MSO_N will be high after N-K clock cycles if the concurrent
output of the (K+1) through the N memory cores are fault free
41 Jin-Fu Li EE, National Central University
output of the (K+1) through the N memory cores are fault free
Sharing BIST Hardware
BIST controlling signals
BIST Controller
TPG &
Comparator
BIST C ll BIST C ll BIST C ll
RAM 1
BIST Collar
RAM N
BIST Collar
RAM 2
BIST Collar
42 Jin-Fu Li EE, National Central University
RAM BIST Compiler
S P f C W W NTHU
43 Jin-Fu Li EE, National Central University
Source: Prof. C. W. Wu, NTHU
1500-Compilant BIST
T
RAM
W
r
a
T
A
P

C
o
n
T
A
P
RAM
BIST
p
p
e
r
n
t
r
o
l
l
e
r
P
44 Jin-Fu Li EE, National Central University
Programmable BISD for RAMs in SOCs
General test architecture
ATE ATE
TAP controller
SOC
TAM
Processor + Test Program Memory
Wrapper
TAM
Embedded Memory Core
S A ll D l ITC03
45 Jin-Fu Li EE, National Central University
Source: Appello D., et. al. ITC03
Programmable BISD for RAMs in SOCs
Test Processor
Processor
Control
Unit
Wrapper
P1500
Instructions
Test Program
Memory
Adapter
P1500
Output Data
Address Bus
Data Bus
Control Signals
S A ll D l ITC03
g
46 Jin-Fu Li EE, National Central University
Source: Appello D., et. al. ITC03
Programmable BISD for RAMs in SOCs
Control Unit
Manage the test programexecution Manage the test program execution
Include an Instruction Register (IR) and
ProgramCounter (PC) Program Counter (PC)
The control unit allows the correct update of
some registers located in Memory Adapter some registers located in Memory Adapter
This part simplifies the processor reuse in
different applications without the need for any different applications without the need for any
re-design
47 Jin-Fu Li EE, National Central University
Programmable BISD for RAMs in SOCs
Memory Adapter
Control Address registers (Current address) g ( _ )
Control Memory registers
Current_data
R i d d t Received_data
Control Test registers
Dbg index, Step, Direction flag, and Timer registers g_ , p, g, g
Result registers
Status, Error, and Result registers
Some constant value registers
Add_Max, Add_Min, DataBackGround, Dbg_max
48 Jin-Fu Li EE, National Central University
Programmable BISD for RAMs in SOCs
Processor instruction set
I t ti M i Instruction Meaning
SET_ADD
Current_address Add_Max
Direction flag BACKWARD Direction flag BACKWARD
RST_ADD
Current_address Add_Min
Direction flag FORWARD g
STORE_DBG
Current_data DataBackGround[Dbg_index]
Dbg_index Dbg_index+1
INV_DBG Current_data NOT (Current_data)
READ Current data Memory[Current address] READ Current_data Memory[Current_address]
WRITE Memory[Current_address] Current_data
49 Jin-Fu Li EE, National Central University
Source: Appello D., et. al. ITC03
Programmable BISD for RAMs in SOCs
Wrapper
WSI
T
A
P

c
W
W
W
C
D
R
W
M
e
WRCK
WRSTN
ShiftWR c
o
n
t
r
o
l
l
e
r
W
I
R
W
B
D
R
R
B
R
e
m
o
r
y
Processor
Test
UpdateWR
CaptureWR
SelectWIR
B
Y
Test
Program
SelectWIR
WSO
CORE
Wrapper
50 Jin-Fu Li EE, National Central University
Source: Appello D., et. al. ITC03
Summary
ROM BIST has been presented p
ROM-based and FSM-based RAM BIST have
been introduced been introduced
Serial BIST methodology for embedded
i h l t d memories has also presented
BIST approaches for testing multiple RAMs in an pp g p
SOC have also been addressed
51 Jin-Fu Li EE, National Central University
References
[1] A. K. Sharma,Semiconductor memories technology, testing, and
li bilit IEEE P 1997 reliability, IEEE Press, 1997.
[2] B. Nadeau-Dostie, A. Silburt, and V. K. Agarwal,Serial interfacing for
embedded-memory testing, IEEE D&T, pp.52-63, apr. 1990.
[3] C. W. Wu,VLSI testing & design for testability II: Memory built-in self-
test, http://larc.ee.nthu.edu.tw/~cww/
[4]C.-H. Tsai and C.-W. Wu, ``Processor-programmable memory BIST for [4]C. H. Tsai and C. W. Wu, Processor programmable memory BIST for
bus-connected embedded memories'', in Proc. Asia and South Pacific
Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2001, pp. 325-330
[5]C -W Wang C -F Wu J -F Li C -W Wu T Teng K Chiu and H -P Lin ``A [5]C. W. Wang, C. F. Wu, J. F. Li, C. W. Wu, T. Teng, K. Chiu, and H. P. Lin, A
built-in self-test and self-diagnosis scheme for embedded SRAM'', in Proc.
9th IEEE Asian Test Symp. (ATS),Taipei, Dec. 2000, pp. 45-50
[6]D Appello F Corno M Giovinetto M Rebaudengo and M S ReordaA [6]D. Appello, F. Corno, M. Giovinetto, M. Rebaudengo, and M. S. Reorda, A
P1500 compliant BIST-Based approach ro embedded RAM diagnosis,
pp.97-102, MTDT, 2001.
[7]J F Li H J H J B Ch C P S C W W C Ch S I Ch C Y [7]J. F. Li, H. J. Huang, J. B. Chen, C. P. Su, C. W. Wu, C. Cheng, S. I. Chen, C. Y.
Hwang, and H. P. Lin,A hierarchical test methodology for systems on chip,
IEEE Micro, pp. 69-81, Sep./Oct., 2002.
f
52 Jin-Fu Li EE, National Central University
[8]S. Mourad and Y. Zorian,Principles of Testing Electronic Systems, John
Wiley & Sons, 2000.