Arsitektur dan Organisasi Komputer

Memory System (1)

Lecture 15 (05 May 2014)
Henry Novianus Palit
hnpalit@petra.ac.id
Basic Concepts (1)
Programs and the data they operate on are held in the
memory of the computer
The execution speed of programs is highly dependent on the
speed with which instructions and data can be transferred
between the processor and the memory
It is important to have sufficient memory to facilitate
execution of large programs having large amounts of data
Ideally, memory should be fast, large, and inexpensive, but
increased speed and size are achieved at increased cost; much
work has gone to develop structures that improve effective
speed & size of the memory, yet keep the cost reasonable
Computers memory comprises a hierarchy, including a cache,
the main memory, and secondary storage
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Basic Concepts (2)
The maximum size of the memory is determined by the
addressing scheme, e.g., computers that generate 16-bit
addresses are capable of addressing up to 2
16
= 64K (kilo)
memory locations, those with 32-bit addresses have 2
32
= 4G
(giga) locations, whereas those with 64-bit addresses have 2
64

= 16E (exa) locations
The memory is usually designed to store and retrieve data in
word-length quantities, e.g., for a byte-addressable computer
with 32-bit addresses, the high-order 30 bits determine the
word to be accessed whereas the low-order 2 bits specify the
byte location involved
The connection between the processor and its memory
consists of address, data, and control lines
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Basic Concepts (3)
Address lines are used
to specify the memory
location involved in a
data transfer operation
Data lines are used to
transfer the data
Control lines carry the
command indicating a
Read or a Write oprn
and whether a byte or
a word is transferred
Control lines also provide the necessary timing information and are used
by the memory to indicate when it has completed the requested oprn
(i.e., asserting the MFC signal); when MFC is asserted, the processor
proceeds to the next step in its execution sequence
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Basic Concepts (4)
Memory access time the time that elapses between the
initiation of an operation to transfer a word of data and the
completion of that operation
Memory cycle time the minimum time delay required
between the initiation of two successive memory operations,
e.g., the time between two successive Read operations;
the cycle time is usually slightly longer than the access time
A memory unit is called a random-access memory (RAM) if
the access time to any location is the same, independent of
the locations address; this distinguishes such memory units
from serial (or, partly serial) access storage devices such as
magnetic and optical disks, the access time of which depends
on the address or position of the data
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Basic Concepts (5)
Cache memory a small, fast memory inserted between the
larger, slower main memory and the processor; it holds the
currently active portions of a program & their data and is used
to reduce the memory access time (which is slower than the
processors speed in processing instructions and data)
Virtual memory a memory organization concept in which
only the active portions of a program are stored in the main
memory, and the remainder is stored on the much larger
secondary storage, and data are transferred back and forth
between the main memory & the secondary storage device
transparently; using this technique, the application program
sees a much larger memory than the computers physical
main memory
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Basic Concepts (6)
Data move frequently between the main memory & the cache
and between the main memory & the disk

Data are always transferred in contiguous blocks involving
tens, hundreds, or thousands of words

A critical parameter for the performance of the main memory
is its ability to read or write blocks of data at high speed
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Semiconductor RAMs (1)
Semiconductor RAMs are available in a wide range of speeds,
from 100 ns to less than 10 ns
Memory cells are usually organized in the form of an array, in
which each cell is capable of storing one bit of information
Each row of cells
constitutes a memory
word; all cells of a
row are connected to
a common word line
(driven by the
address decoder)
Cells in each column
are connected to a
Sense/Write circuit
by two bit lines, and
the Sense/Write
circuits are connected
to the data i/o lines
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Semiconductor RAMs (2)
The memory circuit above stores 128 bits and requires 16
external connections for address (4), data (8), and control (2)
lines, plus power supply & ground
A 1K (1024) bit memory circuit can be organized as a 128 8
memory, requiring a total of 19 external connections;
alternatively, it can
be organized into a
1K 1 format, with
15 extl connections
The 10-bit address is
divided into 2 groups
of 5 bits to form the
row & column addrs
A row addr selects a
row of 32 cells, but
only one cell is
connected to the extl
data line, based on
the column addr
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Static Memories (SRAMs) (1)
Static memories consists of circuits capable of retaining their
state as long as power is applied
A static RAM (SRAM) cell may be implemented using bipolar
or CMOS circuits
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Static Memories (SRAMs) (2)
In a bipolar SRAM cell, two inverters are cross-connected to
form a latch, and the latch is connected to two bit lines by
transistors T
1
and T
2
acting as switches that can be opened or
closed under control of the word line
When the word line is at ground level, the transistors are turned off
and the latch retains its state
To read the state of the SRAM cell, the word line is activated to close
switches T
1
and T
2
; if the cell is in state 1, the signal on bit line b is high
and that on bit line b is low, and the opposite is true if the cell is in
state 0; the Sense/Write circuit at the end of the two bit lines monitors
their state and sets the corresponding output accordingly
During a Write operation, the Sense/Write circuit drives bit lines b and
b (with the appropriate value on b and its complement on b) as the
word line is activated; this forces the cell into the corresponding state,
which is retained when the word line is deactivated
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Static Memories (SRAMs) (3)
In a CMOS realization of the cell, transistor pairs (T
3
, T
5
) and
(T
4
, T
6
) form the inverters in the latch
The state of the cell is read or written as just explained (in bipolar
circuits)
In state 1, the voltage at point X is maintained high by having
transistors T
3
and T
6
on, while T
4
and T
5
are off; the opposite is true to
maintain state 0
In state 1, if T
1
and T
2
are turned on, bit lines b and b will have high
and low signals, respectively
A major advantage of CMOS SRAMs is their very low power
consumption, because current flows in the cell only when the
cell is being accessed; otherwise, T
1
, T
2
, and one transistor in
each inverter are turned off, ensuring that there is no
continuous electrical path between V
supply
and ground
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Static Memories (SRAMs) (4)
Continuous power is needed for the cell to retain its state
If power is interrupted, the cells contents are lost
When power is restored, the latch settles into a stable state, but not
necessarily the same state the cell was in before the interruption
Hence, SRAMs are said to be volatile memories

Static RAMs can be accessed very quickly, with access times
on the order of a few nanoseconds, and are used in
applications where speed is of critical concern
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