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= ,
ON DD
I
C
V V
C
=
(3)
where C is (Cs
+
-Cs
-
)/2. The circuit is capable of convert-
ing sensing capacitance from -2p to 2p with a nonlinearity
distortion less than 0.9 as shown in Fig.7(b), and with a
V-C gain of 0.315mV/fF. The minimum detectable capa-
citance of the readout circuitry reaches 8.3aF within 100Hz
sensor bandwidth, and the linearity range is 119dB. 1
and 2 are non_overlap clock, the 1d and 2d are the
delay of the 1 and 2 respectively.
5. CONCLUSION
This work presents a wide dynamic range and high preci-
sion FPAA for intelligent sensory applications which em-
ploys fat-tree interconnection network and high perfor-
mance IO interfaces. The coarse grained CABs combined
fine-grained reconfigurable core amplifier in this FPAA
can work under continuous-mode and discrete-mode to
maximize the flexibility and efficiency of the FPAA. In
order to achieve large dynamic range in the discrete mode,
FPAA adopted the CDS techniques and full differential
configuration for the high accurate capacitive sensing cir-
cuits. Through the above application demonstration, this
FPAA has been validated that it is an efficient solution for
the fast prototyping of intelligent sensory applications. The
FPAA can also process most of basic analog signal
processing functions on demand.
Fig.7. (a) Mapping of the micro capacitor sensing inter-
face circuit into two CABs
Fig.7. (b) Linearity performance of the capacitive
sensing interface circuit.
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