Hdl circuits digital verilog vhdl uvm verification

Hardware description languages such as Verilog differ from software programming languages because
they include ways of describing the propagation time and signal strengths (sensitivity). There are two
types of assignment operators; a blocking assignment (=) and a non!blocking ("=) assignment. The
non!blocking assignment allows designers to describe a state!machine update without needing to
declare and use temporary storage variables. #ince these concepts are part of Verilog$s language
semantics designers could %uickly write descriptions of large circuits in a relatively compact and
concise form. &t the time of Verilog$s introduction ('()*) Verilog represented a tremendous
productivity improvement for circuit designers who were already using graphical schematic capture
software and specially written software programs to document and simulate electronic circuits.
The designers of Verilog wanted a language with synta+ similar to the , programming language which
was already widely used in engineering software development. -ike , Verilog is case!sensitive and
has a basic preprocessor (though less sophisticated than that of &.#/ ,0,11). /ts control flow
keywords (if0else for while case etc.) are e%uivalent and its operator precedence is compatible with
,. #yntactic differences include2 re%uired bit!widths for variable declarations demarcation of
procedural blocks (Verilog uses begin0end instead of curly braces 34) and many other minor
differences. Verilog re%uires that variables are given a definite si5e. /n , these si5es are assumed from
the $type$ of the variable (for instance an integer type may be ) bits).
& Verilog design consists of a hierarchy of modules. 6odules encapsulate design hierarchy and
communicate with other modules through a set of declared input output and bidirectional ports.
/nternally a module can contain any combination of the following2 net0variable declarations (wire reg
integer etc.) concurrent and se%uential statement blocks and instances of other modules (sub!
hierarchies). #e%uential statements are placed inside a begin0end block and e+ecuted in se%uential order
within the block. However the blocks themselves are e+ecuted concurrently making Verilog a dataflow
language.
Verilog$s concept of $wire$ consists of both signal values (*!state2 7' 8 floating undefined7) and
strengths (strong weak etc.). This system allows abstract modeling of shared signal lines where
multiple sources drive a common net. 9hen a wire has multiple drivers the wire$s (readable) value is
resolved by a function of the source drivers and their strengths.
& subset of statements in the Verilog language are synthesi5able. Verilog modules that conform to a
synthesi5able coding style known as :T- (register!transfer level) can be physically reali5ed by
synthesis software. #ynthesis software algorithmically transforms the (abstract) Verilog source into a
netlist a logically e%uivalent description consisting only of elementary logic primitives (&.; <:
.<T flip!flops etc.) that are available in a specific =>?& or V-#/ technology. =urther manipulations
to the netlist ultimately lead to a circuit fabrication blueprint (such as a photo mask set for an &#/, or a
bitstream file for an =>?&).