SD1 VHDL

Sistemes Digitals I
Versi 3.10 Febrer 2012

J uan A. Chvez
J oan Pons
Departament dEnginyeria Electrnica
Universitat Politcnica de Catalunya
Tema 1 part 2
El Llenguatge VHDL
Sistemes
Digitals I
Previ T1 - 2
Bibliografia addicional recomenada :
Mdul 1 de Teoria ATENEA
Aprendre VHDL a base de feina de laboratori, classes de teoria i
treball personal.
Comenar llegint els documents del Tema 1 de teoria i provant els
exemples en el Quartus II.
The VHDL Cookbook, Peter J . Ashenden, 1990.
A VHDL Primer, J . Bhasker, Ed. Prentice Hall, third edition,1999.
VHDL and AHDL digital system implementation, F. Scarpino,
Ed. Prentice Hall, 1998.
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T1 - 3
1 Introduction
2 Data Communication
3 Design Units
4 Dataflow Modelling
5 Behavioural Modelling
6 Structural Modelling
Outline
1.1 What is a HDL?
1.2 Introduction to VHDL
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1.1 What is a HDL? T1 - 4
Prototype
Fabrication & Test
Final Product
Fabricacion & Test
Technology
independent
steps
Technology
dependent
steps
System Conception
Functional / Logic
design
Physical Design
Expected behaviour
& features (cost,
speed, size, ...)
Functional
simulation
System conception
Design entry
Logical
Synthesis
Digital Design process flow
Physical
Synthesis
Physical
simulation
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Hardware description languages (HDL) are text
based languages for formal description of
electronic circuits and systems
Most common HDLs used for digital circuit design:
Standard: VHDL, Verilog.
Specific or propietary: ABEL, AHDL.
HDLs are always associated with programs that can understand
and simulate the systems described.
Most common uses of HDLs:
Modeling.
Synthesis.
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Abstract steps: system conception and
functional / logic design.
A simulation program allows testing the
functional behavior of the design.
All HDL statements & resources can be
used for modeling purposes.
Technology independent.
Both abstract & technological steps.
The synthesis tools generates a netlist of
hardware components that implements the
specified design.
Physical simulator allows checking system
behavior and performance (i.e. time).
Only a reduced set of the HDL statements
& resources can be used for synthesis.
Functional
simulation
Design entry
Logic
synthesis
HDL for
modeling
Logic & physical
simulation
Design entry
Logic & Physical
Synthesis
T
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HDL for
synthesis
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1.2 Introduction to VHDL T1 - 7
VHDL main features
VHDL stands for VHSIC Hardware Description Language. VHSIC
(Very High Speed Integrated Circuits) was a program of the U.S.
Department of Defense in the early 80s.
Adopted as a standard description tool by the Institute of Electrical
and Electronic Engineers (IEEE).
Powerful description language, but very rigorous and demanding
from the formal point of view.
VHDL describes digital systems, so it is not a programming
language, i.e. it is not a series of instructions that are executed one
after the other.
Main focus in VHDL for synthesis.
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1.2 Introduction to VHDL T1 - 8
Describing is not programming
entity adder is
port (A,B,Cin : in bit;
S, Cout : out bit);
end adder;
architecture gates of adder is
signal X,Y,Z : bit;
begin
X <= A xor B;
Y <= A and B;
Cout <= Y or Z;
Z <= X and Cin;
S <= X xor Cin;
end gates;
Declaration of input and
output ports.
Logical description of the design.
Statements execution is
concurrent in time, so their order
is irrelevant.
Example
Schematic and partial
VHDL description of a
1-bit full adder
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T1 - 9
1 Introduction
3 Design Units
Outline
2.1 Introduction
2.2 Data types
2.3 Data objects
2.4 Operators
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2.1 Introduction T1 - 10
As any language, VHDL manages data through types and operators.
Data is stored within objects that contain values of a given type. The
most common objects are signals, variables and constants.
All objects must be declared before use.
A type includes all possible data values plus associated operators.
VHDL has a reduced set of predefined (or standard) types and
operators, stored in libraries and packages.
Libraries and packages must be declared and made visible prior to
their use in VHDL descriptions. The only exception is a default
predefined library named std.
VHDL basics
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2.2 Data types T1 - 11
Data values are from a finite set.
Most common predefined types:
Boolean. From std library. Values: false, true.
Bit. From std library. Values: 0, 1.
Std_logic. It must be previously declared(ieee library,
std_logic_1164 package). It allows realistic modelling of digital
signals through 9 possible values:
Enumerate types
U -- Not initialized W -- Unknown (weak)
X -- Unknown (strong) L -- Logic 0 (weak)
0 -- Logic 0 (strong) H -- Logic 1 (weak)
1 -- Logic 1 (strong) - -- Dont care
Z -- High impedance
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The most common are natural, integer, real , ...
Integer is from the std library. Values are encoded in twos
complement with 32 bits, so synthesis tools may generate large
networks. To minimize size, integer objects with reduced ranges are
used (i.e. from 0 to 7 is synthetized with 3 bits).
Numeric types
Array types
n-dimensional set of elements of the same type.
The most common predefined 1D array types are bit_vector (std
library) and std_logic_vector (ieee library, ieee.std_logic_1164
package).
Strings are defined as character arrays.
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Designers can define specific enumerate and array types:
Specific types
Examples
type colours is (red, green, blue);
type machine_states is (idle, init, run, stop);
type boolean is (true, false); -- this type already exists!
-- description of a 128x8 bit memory
type data_word is array (7 downto 0) of bit;
type my_memory is array (0 to 127) of data_word;
type i dent i f i er is ( l i st of val ues) ;
type i dent i f i er is array ( i ndex) of t ype;
syntax
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2.3 Data objects T1 - 14
name
value
Examples
A constant has a value that can not be modified.
type
constant n: integer := 8;
constant m: integer := n-1; -- value is 7
constant p: integer := n/2; -- value is 4
constant vcc: std_logic := '1';
constant xx: std_logic_vector(7 downto 0) := "01010101";
constant yy: std_logic_vector(7 downto 0) := X"55"; -- same as xx
constant i dent i f i er : t ype : = expr essi on;
syntax
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Examples
Signals model the behaviour of signals transmitted through wires.
Signals hold a current value and a set of possible future values
(driver). In this way, effects such as delays, concurrency or bandwidth
limits can be modelled.
-- declaration of an 8-element signal array of type std_logic
signal my_bus : std_logic_vector(7 downto 0);
-- declaration of two sub-ranged integer signals
signal n,m : integer range 0 to 15;
signal i dent i f i er : t ype [ : = expr essi on] ;
syntax
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A variable holds a single value. Unlike signals, variable assignments
take effect immediately.
Variables can only be declared and used inside process statements.
Examples
-- declaration of 2 variables of type integer
variable m,n : integer;
-- declaration of a 50-element variable array of string
-- with initial value Good Morning
variable strline : string(0 to 49):= Good Morning;
variable i dent i f i er : t ype [ : = expr essi on] ;
syntax
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2.4 Operators T1 - 17
Assignment operators assign expression values to objects.
:= for constants and variables <= for signals
= -- Equal to /= -- Not equal to
> -- More than >= -- Equal to or more than
< -- Less than <= -- Equal to or less than
Comparison operators give boolean results (t r ue or f al se).
The concatenate operator (&) is used to concatenate arrays.
It cannot be used on the left side of assignments.
Examples
signal X : std_logic_vector(1 downto 0);
signal Y,Z : std_logic_vector(3 downto 0);
Y <= X & 10; -- OK, Y=[X(1),X(0),'1','0']
Z <= 1 & Y(3 downto 1); -- OK, Z=['1',Y(3),Y(2),Y(1)]
X & 10 <= Y; -- wrong use of &
Z <= 1 & Y; -- wrong: type widths mismatch
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Logic operators are or, nor, and, nand, xor, not.
They define one-to-one operations when applied to array
objects.
Unlike in Boolean algebra, in VHDL precedence of logic
operations goes from left (highest priority) to right (lowest
priority).
Examples
signal x,y,w,z : std_logic;
signal zout,yin,xin : std_logic_vector(3 downto 0);
z <= x and y;
zout <= not (xin nor yin);
zout <= xin(1 downto 0) and yin(3 downto 2); -- wrong type widths
z <= x nor y nor w; -- not a 3 input nor
z <= x nor (y nor w); -- not a 3 input nor, but different than previous
z <= not (x or y or w); -- three input nor
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By default arithmetic operators only work with numeric types.
Although std_logic and std_logic_vector are not numeric types, we
can do arithmetic operations with them making visible the ieee
library and
the std_logic_unsigned package for positive unsigned (i.e.
binary) operations.
the std_logic_signed package for signed (i.e. two's
complement) operations.
- -- Sign change mod -- Module
+ -- Addition rem -- Remainder of integer division
* -- Multiplication ** -- Exponentiation
/ -- Division abs -- Absolute value
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T1 - 20
1 Introduction
3 Design Units
Outline
3.1 Introduction
3.2 Entity Declaration
3.3 Architecture Body
3.4 Packages and Libraries
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3.1 Introduction T1 - 21
Desi gn Ent i t y
I/O
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Architecture Body 1
Architecture Body 2
Architecture Body N
Configuration
Package 1
Body
Decla-
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Package M
Body
Decla-
ration
A system or a subsystem described in VHDL is a design entity, which is
the main unit of abstraction.
A design entity is composed of several different design units:
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3.2 Entity Declaration T1 - 22
Desi gn Ent i t y
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Architecture Body 1
Architecture Body 2
Architecture Body N
Configuration
Package 1
Body
Decla-
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Package M
Body
Decla-
ration
Entity declaration: describes interface signals between design
entity and external world. It includes ports declaration.
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A port is a signal that interfaces the entity with its external environment.
Three port types:
in (input): It can only be read.
out (output): It can only be written.
inout (bidirectional): it can be read and written.
entity i dent i f i er is
[ generic( gener i c const ant s) ; ]
{port( {i npor t name: in t ypei n; }
{out por t name: out t ypeout ; }
{i opor t name: inout t ypei o; }) ; }
end [ entity] [ i dent i f i er ] ;
syntax
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Equivalent Schematic
i n
in
A[numbits-1..0]
B[numbits-1..0]
S[numbits..0]
i n
in
out
out
i n
in
A[numbits-1..0]
B[numbits-1..0]
S[numbits..0]
i n
in
out
out
entity adder is
generic( numbi t s: nat ur al ) ;
port( A: in bi t _vect or ( numbi t s- 1 downto 0) ;
B: in bi t _vect or ( numbi t s- 1 downto 0) ;
S: out bi t _vect or ( numbi t s downto 0) ) ;
end entity adder ;
Example
Entity adder has two input ports and one output port.
Generic parameter numbits allows external parametrization of
ports width.
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3.3 Architecture Body T1 - 25
Architecture body: statements describing the entity. Such description
may be not unique and several models can be specified in different
architecture bodies.
Desi gn Ent i t y
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Architecture Body 1
Architecture Body 2
Architecture Body N
Configuration
Package 1
Body
Decla-
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Package M
Body
Decla-
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Configuration declaration: specifies some parameters for the compiler. It can
be used to select one architecture body. Quartus II does not support
configuration declarations: for a given device, it automatically selects the
architecture body that assures the best device performance.
Desi gn Ent i t y
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Architecture Body 1
Architecture Body 2
Architecture Body N
Configuration
Package 1
Body
Decla-
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Package M
Body
Decla-
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The first section is the declaration of the types, objects and
components used in the logical description.
The concurrent_statements section describes the internal structure
or the operation of the entity. Dataflow, structural and behavioural
modelling styles are supported.
All statements within the architecture are concurrent. Therefore,
statements order is irrelevant.
architecture i dent i f i er of ent i t y_name is
[ decl ar at i on of t ypes]
[ decl ar at i on of const ant s and si gnal s]
[ decl ar at i on of component s]
begin
concur r ent st at ement s
end [ architecture] [ i dent i f i er ] ;
siyntax
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Example
VHDL description of a bus-splitter: an 8-bit
input bus is splitted into two 4-bit output
buses.
library ieee;
use ieee.std_logic_1164.all;
entity bus_split is
port(b_in : in std_logic_vector(7 downto 0);
b_inh,b_inl : out std_logic_vector(3 downto 0));
end bus_split;
architecture a of bus_split is
begin
b_inh <= b_in(7 downto 4);
b_inl <= b_in(3 downto 0);
end a;
-- equivalent to
b_inh(3) <= b_in(7);
b_inh(2) <= b_in(6);
b_inh(1) <= b_in(5);
b_inh(0) <= b_in(4);
b_inl(3) <= b_in(3);
b_inl(2) <= b_in(2);
b_inl(1) <= b_in(1);
b_inl(0) <= b_in(0);
b_in[7:0]
b_inh[3:0]
b_inl[3:0]
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library ieee;
entity adder is
port (A,B,Cin : in std_logic;
S, Cout : out std_logic);
end adder;
architecture gates of adder is
signal X,Y,Z : std_logic;
begin
X <= A xor B;
Y <= A and B;
Cout <= Y or Z;
Z <= X and Cin;
S <= X xor Cin;
end gates;
3.3 Architecture Body

1 1 1 1 1
1 0 1 0 1
1 0 1 1 0
0 1 1 0 0
1 0 0 1 1
0 1 0 0 1
0 1 0 1 0
0 0 0 0 0
Cout S Cin B A
Outputs Inputs
Equivalent Truth Table
1 1 1 1 1
1 0 1 0 1
1 0 1 1 0
0 1 1 0 0
1 0 0 1 1
0 1 0 0 1
0 1 0 1 0
0 0 0 0 0
Cout S Cin B A
Outputs Inputs
Equivalent Truth Table
T1 - 29
Example
VHDL description of
a 1-bit full adder and
its corresponding
schematic and truth
table
A
S
Cout
B
Cin
X
Y
Z
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3.4 Packages and Libraries T1 - 30
Package declaration: types, constants, components or subprograms.
Packages must be declared only once and used globally.
Package body: logical descriptions of declarations which have been
included in the package declaration.
Desi gn Ent i t y
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Package M
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Decla-
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3.4 Packages and Libraries T1 - 31
Packages can be grouped and stored as design libraries.
To use them in design entities, libraries and packages must be
previously declared, according to the following syntax:
item indicates what package components are to be used. When item is
replaced by all, all package components are imported.
After compilation, intermediate forms of all design units are stored in a
library named work, which is always visible.
There are some standard VHDL libraries (see next slide). std is always
visible, but ieee must be imported and made visible.
library l i br ar y_name;
use l i br ar y_name. package_name. i t em;
syntax
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3.4 Packages and Libraries
Library Package Contains
std
standard
Basic VHDL types (bool ean, bi t , bi t _vect or , char act er ,
st r i ng, i nt eger , r eal , t i me, ...) plus associated operators.
textio
Other types such as l i ne and t ext and procedures to read
and write text files.
work
Default library which contains all user design entities after
compilation.
ieee
std_logic_1164
st d_l ogi c and st d_l ogi c_vect or types plus basic
associated operators.
std_logic_arith
Si gned and unsi gned types plus associated arithmetic
operators.
std_logic_signed
Signed artihmetic operations, conversion functions and
comparison operators for the st d_l ogi c_vect or type.
std_logic_unsigned
Unsigned artihmetic operations, conversion functions and
comparison operators for the st d_l ogi c_vect or type.
std_logic_textio
Data types and procedures to read & write files for the
st d_l ogi c and st d_l ogi c_vect or types.
T1 - 32
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T1 - 33
1 Introduction
3 Design Units
Outline
4.1 Concurrent Signal Assignments
4.2 Signal Assignment
4.3 Conditional Signal Assignment
4.4 Selected Signal Assignment
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4.1 Concurrent signal assignments T1 - 34
Data flow through an entity is primarily expressed by using signals
and concurrent signal assignment statements.
Concurrent assignment statements are executed whenever events
occur on signals that appear in their expressions.
Some examples of concurrent assignment statements follow
x <= F(a,b);
y <= G(x,c);
F(m,n)
x
m
n
G(s,t)
s
t
a
z
b
c
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4.2 Signal assignment T1 - 35
Value of waveform is computed and assigned to signal_identifier.
Waveform includes a logical expression, but it can also include delay
information. VHDL has two delay mechanisms, called transport and
inertial, to model time behaviour.
Anyway, no delay information should be specified in Quartus II for
synthesis purposes, because the compiler automatically inserts this
information according to the devices used.
si gnal _i dent i f i er <= wavef or m;
syntax
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4.2 Signal assignment T1 - 36
Example
The first assignment is executed any time an event occurs on
signals a, b or c.
The second assignment is executed after any events on b or c.
The (transport) delay will be overridden by Quartus II.
library ieee;
entity pse is
port (a,b,c : in std_logic;
y : out std_logic_vector(1 downto 0));
end pse;
architecture arc of pse is
begin
y(1) <= a and (b or c);
y(0) <= b xor c after 10 ns;
end arc;
a
y[1:0]
b
c
y[1]
y[0]
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4.3 Conditional signal assignment T1 - 37
The waveform that
corresponds to the first
condition evaluated as true
is assigned to the signal.
Example
library ieee;
entity mux_2 is
port (x0,x1 : in std_logic_vector(3 downto 0);
sel : in std_logic;
end mux_2;
architecture arc1 of mux_2 is
begin
y <= x0 when sel = '0'
else x1;
end arc1;
si gnal _i dent i f i er <=
{wavef or m_i when condi t i on_i else}
wavef or m_N [ when condi t i on_N] ;
x1[3:0]
y[3:0]
sel
0
1
x0[3:0]
Mux
syntax
Conditions should not be exclusive.
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library ieee;
entity mux_2 is
port (x0,x1 : in std_logic_vector(3 downto 0);
sel : in std_logic;
y : out std_logic_vector( downto 0));
end mux_2;
architecture arc2 of mux_2 is
begin
with sel select
y <= x0 when '0',
x1 when others;
end arc2;
Example
4.4 Selected signal assignment T1 - 38
The waveform that corresponds
to the choice matching up with
the value of expression, is
assigned to the signal.
with expr essi on select
si gnal _i dent i f i er <=
{wavef or m_i when choi ce_i , }
wavef or m_N when choi ce_N;
x1[3:0]
y[3:0]
sel
0
1
x0[3:0]
Mux
syntax
Choices must be exclusive.
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library ieee;
entity even_det is
port( num : in integer range 0 to 15;
y : out std_logic );
end even_det;
architecture a of even_det is
begin
with num select
y <= '1' when 0|2|4|6|8|10|12|14,
'0' when others;
end a;
Vertical bars mean or
choices.
others =none of the
previous.
Even numbers detector for the 0 to 15 range.
Example
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library ieee;
use ieee.std_logic_signed.all;
entity mini_ALU is
port (a,b : in std_logic_vector(7 downto 0);
sel : in integer range 0 to 3;
end mini_ALU;
architecture arc1 of mini_ALU is
begin
y <= a+b when sel=0
else a-b when sel=1
else a when sel=2
else b;
end arc1;
a[7:0]
y[7:0]
sel[1:0]
0
1
2
3
b[7:0]
Mux
architecture arc2 of mini_ALU is
begin
with sel select
y <= a+b when 0,
a-b when 1,
a when 2,
b when 3;
end arc2;
Example
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T1 - 41
1 Introduction
3 Design Units
Outline
5.1 Process Statement
5.2 Sequential Assignment Statements
5.3 If Statement
5.4 Signal Attributes
5.5 Case Statement
5.6 Loop Statement
5.7 Wait Statement
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5. Behavioural modelling T1 - 42
A description of the behaviour of a system says nothing about
the structure or the components that make up the system.
A behavioural model is composed by a set of concurrent
processes. The behaviour of each process is described using
sequential statements.
Process
A
Process
B
Process
C
Process
D
Process
F
Process
E
Process
G
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5.1 Process Statement T1 - 43
A process statement describes an independent sequential behaviour of
some portion of the design.
When an event on any of the signals included in the sensitivity_list
occurs, the statements within the process are executed sequentially (in
the order they appear). When execution ends, the process is
suspended and waits for new events.
If no sensitivity_list is present, then the process is executed repeatedly.
Items declared in the declarative_part are available for use only within
the process.
[ l abel : ] process [ (sensi t i vi t y_l i st )] [is]
[ decl ar at i ve_sect i on]
begin
sequence_of _st at ement s
end process;
syntax
This may hang the compiler
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5.1 Process Statement T1 - 44
2-input xor gate described with as a process statement. Process is
executed each time an event occurs on any of the signals a or b.
entity pr ocst at ement is
port( a, b: in bi t ;
y: out bi t ) ;
end entity pr ocst at ement ;
architecture a of pr ocst at ement is
begin
process ( a, b)
begin
if b='0' then y <= a;
else y <= not a;
end if;
end process;
end architecture a;
Example
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5.2 Sequential assignment statements T1 - 45
Variables can be declared and used only inside processes.
A new value is assigned to variable_identifier when the variable
assignment statement is executed.
The term expression may contain signals, but both sides of the
assignment must be of the same type.
Variables may be hard to synthesize!
var i abl e_i dent i f i er := expr essi on;
syntax
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The syntax for both sequential and concurrent signal assignment
statements is identical.
A sequential signal assignment is executed when an event occurs on
a signal present in the sensitivity list of the process.
Sequential signal assignments are effective only at the end of process
execution.
Signals are used to exchange data between processes.
si gnal _i dent i f i er <= wavef or m;
syntax
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Example
Case 1: A, B, C and D are variables that
have been declared inside a process
which contains this set of sequential
assignment statements:
A : = B+C;
D : = A+C;
A : = C+D;
When the process is suspended after
one execution, variable values are:
A=7, B=1, C=2, D=5
Case 2: A, B, C and D are signals that
have been declared outside a process
which contains this set of sequential
assignment statements:
A <= B+C;
D <= A+C;
A <= C+D;
When the process is suspended after
one execution, signal values are:
A=5, B=1, C=2, D=2
We have four integer objects with the following initial values:
A=0, B=1, C=2, D=3
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5.3 If Statement T1 - 48
Selects for execution one or none of the sequences of statements.
Conditions are evaluated successively until the first true condition is
found or all conditions are evaluated as false.
If a true condition is found the corresponding sequence_of_statements is
executed. Otherwise, if the else clause is present and all previous
conditions are false then sequence_of_statements_N is executed.
if condi t i on_1 then
sequence_of _st at ement s_1
{elsif condi t i on_i then
sequence_of _st at ement s_i }
[ else
sequence_of _st at ement s_N]
end if;
syntax
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5.3 If Statement T1 - 49
library i eee;
use i eee. st d_l ogi c_1164.all;
use i eee. st d_l ogi c_si gned.all;
entity i f st at ement is
port( a, b : in st d_l ogi c_vect or ( 7 downto 0) ;
op : in bi t ;
y : out st d_l ogi c_vect or ( 8 downto 0) ) ;
end i f st at ement ;
architecture a of i f st at ement is
begin
process ( op, a, b)
variable aa, bb : st d_l ogi c_vect or ( 8 downto 0) ;
begin
aa: =' 0' &a; -- 9 bit bus
bb: =' 0' &b; -- 9 bit bus
if op=' 0' then y <= aa + bb;
else y <= aa;
end if;
end process;
end a;
Example
a[7:0]
y[8:0]
op
0
1
b[7:0]
Mux
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5.4 Signal Attributes T1 - 50
Attributes are values, functions, types, ranges, signals or constants
associated with data objects that provide additional information about
those objects.
Example (event attribute): sevent (being s a signal identifier) returns
t r ue when an event occurs in s.
Time s sevent
t
1
0 f al se
t
2
1 true
t
3
1 f al se
t
4
1 f al se
t
5
1 f al se
t
6
1 f al se
t
7
0 true
t
8
0 f al se
(s=1) and (sevent) =t r ue
RISING EDGE
(s=0) and (sevent) =t r ue
FALLING EDGE
s
t
t
2
t
1
t
4
t
3
t
6
t
5
t
8
t
7
0
1
EVENT EVENT
An event attribute can be used
to specify rising or falling
edges on signals.
obj ect _i dent i f i er 'at t r i but e
syntax
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library i eee;
entity event at t r i but e is
port( cl k, nr st : in st d_l ogi c;
xi n : in st d_l ogi c_vect or ( 7 downto 0) ;
yout : out st d_l ogi c_vect or ( 7 downto 0) ) ;
end event at t r i but e;
architecture a of event at t r i but e is
begin
process( cl k, nr st )
begin
if nr st = ' 0' then
yout <= "00000000";
elsif cl k=' 1' and cl k'event then
yout <= xi n;
end if;
end process;
end architecture;
Example
8-bit register with asynchronous reset
rising edge
detection
yout will be assigned only after a
rising edge in clk is detected
asynch.
reset
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library i eee;
entity event at t r i but e2 is
port( cl k, nr st , e: in st d_l ogi c;
xi n : in st d_l ogi c_vect or ( 7 downto 0) ;
yout : out st d_l ogi c_vect or ( 7 downto 0) ) ;
end event at t r i but e2;
architecture a of event at t r i but e2 is
begin
process( cl k, nr st )
begin
if nr st = ' 0' then
yout <= "00000000";
elsif cl k=' 1' and cl k'event then
if e=' 1' then
yout <= xi n;
end if;
end if;
end process;
end architecture;
Example
8-bit register with asynchronous reset and synchronous enable
out will be assigned only after a rising edge on
clk is detected, being e equal to 1
out will be assigned only after a rising edge on
clk is detected, being e equal to 1
synchronous enable synchronous enable
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5.5 Case statement T1 - 53
A sequence_of_statements is selected from a set of choices; the value of
an expression defines the chosen alternative.
expression must be of an enumerate type or of a 1D character array type.
choices may be expressed as single values, as value ranges or as a
values list (using a vertical bar).
An others choice is allowed for the last alternative, then it covers all
values not previously evaluated.
case expr essi on is
when choi ce_1 => sequence_of _st at ement s_1
{when choi ce_i => sequence_of _st at ement s_i }
[ when others => sequence_of _st at ement s_N]
end case;
syntax
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library i eee;
entity casest at ement 1 is
port( a, b, c, d : in st d_l ogi c_vect or ( 7 downto 0) ;
sel : in st d_l ogi c_vect or ( 1 downto 0) ;
end casest at ement 1;
architecture a of casest at ement 1 is
begin
process( sel , a, b, c, d)
begin
case sel is
when "00" => y <= a;
when "01" => y <= b;
when "10" => y <= c;
when others => y <= d;
end case;
end process;
end a;
Example 4-to-1 multiplexer
a[7:0]
y[7:0]
sel[1:0]
0
1
2
others
b[7:0]
Mux
c[7:0]
d[7:0]
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library i eee;
entity casest at ement 2 is
port( num: in i nt eger range 0 to 15;
y : out st d_l ogi c) ;
end casest at ement 2;
architecture a of casest at ement 2 is
begin
process( num)
begin
case numis
when 0| 2| 4| 6| 8| 10| 12| 14 => y <= ' 1' ;
when ot her s => y <= ' 0' ;
end case;
end process;
end a;
Example
Even numbers detector
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5.6 Loop statement T1 - 56
Loop statements execute repeatedly a sequence of statements.
There are several loop iteration schemes, but only the one shown
above is supported by Quartus II.
discrete_range specifies the number of iterations. identifier is a
constant within the sequence of statements; it is not allowed as the
target of an assignment statement.
Loop statements may be hard to synthesise.
for i dent i f i er in di scr et e_r ange loop
sequence_of _st at ement s
end loop;
syntax
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library i eee;
use i eee. st d_l ogi c_unsi gned.all;
entity l oopst at ement 1 is
port( x : in st d_l ogi c_vect or ( 7 downto 0) ;
end l oopst at ement 1 ;
architecture a of l oopst at ement 1 is
begin
process( x)
variable yy : st d_l ogi c_vect or ( 31 downto 0) ;
variable zz : st d_l ogi c_vect or ( 39 downto 0) ;
begin
yy : = ( 0=>' 1' , others=>' 0' ) ; -- yy:="0...01"
for i in 0 to 3 loop
zz : = yy*x;
yy : = zz( 31 downt o 0) ;
end loop;
y <= yy;
end process;
end a;
5.6 Loop statement T1 - 57
Example Implementation of the 4-th power function
POF/Device I/O Pins Logic Elements
l oopst at ement 1
EPM5707144C3 40/ 116( 34%) 534/ 570( 94%)
Report file
The process described
with this statement may
be not synthesizable or
may have an inefficient
implementation
Signal stabilization time
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5.7 Wait statement T1 - 58
A wait statement suspends the execution of a process. This
statement is an alternative way to sensitivity lists.
Process execution is suspended until expression becomes
true. When an event occurs on any signal contained in
expression, then expression is evaluated.
wait until expr essi on;
syntax
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5.7 Wait statement T1 - 59
Example
as a process with wait statement
library i eee;
entity wai t st at ement is
port( d: in st d_l ogi c_vect or ( 7 downto 0) ;
cl k, e, cl r : in st d_l ogi c;
q: out st d_l ogi c_vect or ( 7 downto 0) ) ;
end wai t st at ement ;
architecture b of wai t st at ement is
begin
r : process
begin
wait until ( cl k'event and cl k=' 1' ) ;
if cl r = 1' then q<=( others=>' 0' ) ;
elsif e=' 1' then q<=d;
end if;
end process;
end b;
library i eee;
entity wai t st at ement is
port( d: in st d_l ogi c_vect or ( 7 downto 0) ;
cl k, e, cl r : in st d_l ogi c;
end wai t st at ement ;
architecture a of wai t st at ement is
begin
r : process ( cl k)
begin
if cl k'event and cl k=' 1' then
if cl r = 1' then q<=( others=>' 0' ) ;
elsif e=' 1' then q<=d; end if;
end if;
end process;
end a;
8-bit register with
synchronous reset and
synchronous enable
as a process with sensitivity list
sync_reg
d[7..0]
q[7..0]
e
clr
clk
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T1 - 60
1 Introduction
3 Design Units
Outline
6.1 Component declaration
6.2 Component instantiation statement
6.3 Recursive generation statement
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6. Structural modelling T1 - 61
Top-l evel desi gn Ent i t y
Component 1 Component 1
Desi gn Ent i t y
Component 2
Desi gn Ent i t y
Component L
Desi gn Ent i t y
D
e
c
l
a
r
a
t
i
o
n

E
n
t
i
t
y
Top-level
Architecture
Body
Conc ur r ent St at ement s of Top-l evel
Ar chi t ec t ur e
Structural descriptions are
equivalent to schematic
descriptions.
VHDL hierarchical design:
entities may be used as
components in higher-level
entity descriptions.
Components and
concurrent statements are
interconnected through
signals.
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6.1 Component declaration T1 - 62
Component declarations must be in the declarations section of
architecture bodies. They declare entity interfaces that may be used in
component instantiation statements.
Components must be associated with design entities from a library or
must be bound to entities.
ports_definition is similar to an entity declaration: it specifies a name,
mode and type for each port of the component.
Component declarations may also appear in packages and become
visible through library and use clauses.
component i dent i f i er [ is]
{port( por t s_def i ni t i on) ; }
end component [ i dent i f i er ] ;
syntax
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6.2 Component instantiation statement T1 - 63
It defines an individual component and associates its ports with
signals of the current design entity.
label is the name of the instance. It is used to individualize
different components of the same kind.
component_name is the identifier used in the component
declaration.
association_list associates one-by-one entity signals with
component ports.
l abel : comp_name [ port map ( associ at i on_l i st ) ] ;
syntax
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T1 - 64
Example
library i eee;
use i eee. st d_l ogi c_1164. all;
entity st r uct desi gn is port(
cl k, bi t i n, cl r n : in st d_l ogi c;
end entity st r uct desi gn ;
architecture a of st r uct desi gn is
component df f port(
d, cl k, cl r n : in st d_l ogi c;
pr n : in st d_l ogi c :=1';
q : out st d_l ogi c) ;
end component;
signal x: st d_l ogi c_vect or ( 3 downto 0) ;
signal vcc: st d_l ogi c;
begin
f f 0: df f port map ( d=>bi t i n, cl k=>cl k, cl r n=>cl r n, q=>x( 0) ) ;
f f 1: df f port map ( cl k=>cl k, d=>x( 0) , cl r n=>cl r n, q=>x( 1) ) ;
f f 2: df f port map ( x( 1) , cl k, cl r n, vcc, x( 2) ) ;
f f 3: df f port map ( cl k=>cl k, d=>x( 2) , cl r n=>cl r n, pr n=>vcc, q=>x( 3) ) ;
q <= x; vcc <= 1 ;
end architecture a;
dff is a primitive
included in a
specific Quartus
II library.
4-bit serial-to-parallel shift register
D flip-flop
declaration
Different
instantiation
styles
6.2 Component instantiation statement
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6.2 Component instantiation statement T1 - 65
Example
begin
f f 0: df f port map ( d=>bi t i n, cl k=>cl k, cl r n=>cl r n, q=>x( 0) ) ;
f f 1: df f port map ( cl k=>cl k, d=>x( 0) , cl r n=>cl r n, q=>x( 1) ) ;
f f 2: df f port map ( x( 1) , cl k, cl r n, vcc, x( 2) ) ;
f f 3: df f port map ( cl k=>cl k, d=>x( 2) , cl r n=>cl r n, pr n=>vcc, q=>x( 3) ) ;
q <= x; vcc <= 1 ;
end architecture a;
4-bit serial-to-parallel shift register
If a component port has a default value then it is not necessary to
include its signal assignment in the instantiation statement.
Labels (ff0, ff1 ...) allow
component
individualisation.
A component is
created when an
instantiation
statement is used.
Whenever the name of a port is not used, all
signals must appear in the instantiation, even
those with default values.
Constant values can not be used in
component instantiation statements.
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6.3 Recursive generation statement T1 - 66
Generate is used to replicate concurrent statements.
A for generation scheme can describe structures with iterative patterns. The
concurrent_statements are generated repeatedly using the values of identifier
An if generation scheme selects whether the concurrent_statements are
generated or not. Selection is based on the value of expression.
l abel : for i dent i f i er in di scr et e_r ange generate
[ bl ock decl ar at i ons
begin]
concur r ent _st at ement s
end generate;
syntax
l abel : if expr essi on generate
[ bl ock decl ar at i ons
begin]
concur r ent _st at ement s
end generate;
syntax
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6.3 Recursive statement generation T1 - 67
Example n-bit serial-in parallel-out shift register
Serial input
Generate statements are not executed, but expanded as a set of
concurrent statements.
This can provide compact descriptions of regular structures such as
memories, registers and counters.
Parallel output
Serial
output
D flip-flop
whith enable
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6.3 Recursive statement generation T1 - 68
library i eee;
use i eee. st d_l ogi c_1164. all;
entity gener at ex is
generic ( n: i nt eger : =8) ;
port( cl k, nr st , s_i n, e : in st d_l ogi c;
p_out : out st d_l ogi c_vect or ( n- 1 downto 0) ;
s_out : out st d_l ogi c ) ;
end entity gener at ex ;
architecture a of gener at ex is
component df f e
port( cl k, cl r n, ena, d : in st d_l ogi c;
pr n : in st d_l ogi c :='1'; q : out st d_l ogi c) ;
end component;
signal x: st d_l ogi c_vect or ( n- 1 downto 0) ;
begin
r eg: for i in 0 to n- 1 generate
d0: if ( i =0) generate
cmp0: df f e port map ( cl k=>cl k, cl r n=>nr st , ena=>e, d=>s_i n, q=>x( 0) ) ;
end generate;
di : if ( i >0 and i <=n- 1) generate
cmpi : df f e port map ( cl k=>cl k, cl r n=>nr st , ena=>e, d=>x( i - 1) , q=>x( i ) ) ;
end generate;
p_out ( i ) <= x( i ) ;
end generate;
s_out <= x( n- 1) ;
end architecture a;
Parameterised register length.
The default value is n=8
Component
declaration
Generation loops
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6.3 Recursive statement generation
cmp0: df f e port map( cl k=>cl k, d=>i nput , cl r n=>vcc, ena=>e, q=>x( 0) ;
par al l el out ( 0) <= x( 0) ;
cmpi : df f e port map( cl k=>cl k, d=>x( 0) , cl r n=>vcc, ena=>e, q=>x( 1) ) ;
par al l el out ( 1) <= x( 1) ;
par al l el out ( 2) <= x( 2) ;
par al l el out ( 3) <= x( 3) ;
par al l el out ( 4) <= x( 4) ;
par al l el out ( 5) <= x( 5) ;
par al l el out ( 6) <= x( 6) ;
par al l el out ( 7) <= x( 7) ;
T1 - 69
Example
The compiler expands the generate statements as follows:

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