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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 9, SEPTEMBER 2003

Nanoscale Silicon MOSFETs: A Theoretical Study

Victor A. Sverdlov, Thomas J. Walls, and Konstantin K. Likharev, Member, IEEE

AbstractWe have carried out extensive numerical modeling of

double-gate, nanoscale silicon -metal oxide semiconductor field
effect transistors (MOSFETs) with ultrathin, intrinsic channels
connecting bulk, highly doped electrodes. Our model takes into account two most important factors limiting the device performance
as the gate length is reduced, namely the gate field screening by
source and drain, and quantum mechanical tunneling from source
to drain. The results show that the devices with small but plausible
values of gate oxide thickness ox and channel thickness (both of
the order of 2 nm) may retain high ON current, good saturation
and acceptable subthreshold slope even if the gate length is as
small as
nm, with voltage gain above unity all the way down
nm (channel length
nm). However,
to
ox
as soon as is decreased below
nm, specific power (per unit
channel width) starts to grow rapidly. Even more importantly,
threshold voltage becomes an extremely sensitive function of
, and ox , creating serious problems for reproducible device
fabrication.

= +2
10

Index TermsCMOS, double-gate transistors, dynamic and

static power, future prospects, MOSFET, parameter variation
sensitivity, ultrathin undoped channel.

I. INTRODUCTION

ECENT spectacular demonstrations of silicon metal oxide

semiconductor field effect transistors (MOSFETs) with
gate lengths below 20 nm [1][8] illustrate a rapid acceleration
in aggressive scaling of such devices (for recent reviews, see,
e.g., [9][11]). Prospects of the scaling beyond the 2001 ITRS
[12] projections, i.e., into the sub-10-nm region, are of primary
importance for future electronics. The goal of this work was to
explore possible properties of the most scalable variety of these
devices, double-gate MOSFETs with ultrathin, intrinsic channels and highly doped (degenerate) bulk electrodes. In such transistors, short-channel effects typical for their bulk counterparts
[9] are minimized, while the absence of dopants in the channel
maximizes the effective mobility and hence ON current density,
that may approach its maximum determined by carrier supply
from the source [13][15]. To summarize, this model is a close
approximation to what may be called the ultimate MOSFET,
still allowing practical implementation using either planar, or
fin-type, or vertical geometry [9], [10].
Several important theoretical studies of nanoscale
double-gate MOSFETs have been published (see, e.g.,
[13][27]); however, most of them cannot be used for predictions of device performance below 10 nm. For example, the
Manuscript received November 4, 2002; revised June 10, 2003. This
work was supported by the Semiconductor Research Corporation and Grant
TFF-2.2-244 from the Russian Ministry of Education. The review of this paper
was arranged by Editor H. Sakaki.
The authors are with the State University of New York, Stony Brook, NY
11794-3800 USA.
Digital Object Identifier 10.1109/TED.2003.816523

pioneering works [13], [14] were based on a one-dimensional

(1-D) model that could not describe the device degradation as
its gate length is decreased. The further studies have shown
that two major fundamental effects are responsible for this
degradation:
i) increasingly poorer electrostatic control of the potential
profile in the channel by the gate voltage, due to its
screening by the source and drain;
ii) rapidly increasing quantum tunneling of carriers from
source to drain, under the maximum of the potential
profile in the channel.
The former effect was the subject of an early semi- analytical
study [15]; however, it was based on the so-called parabolic approximation for electrostatic potential that has only asymptotic
validity [16]. This drawback was avoided in several later studies
by using two-dimensional (2-D) Poisson solvers; however, they
have not taken into account the latter effect (source-to-drain
tunneling). The first quantitative analysis of that effect has been
described in [18]. However, it was based on the WKB approximation that becomes increasingly inaccurate for sub-10 nm
MOSFETs where the tunneling becomes more intensive.
In this work we have not only overcome this problem by
using a full quantum mechanical description of the transistor,
but also considerably expanded the calculation scope, following
the model described in [18] in all other aspects. Briefly, we
consider a double-gate MOSFET with ultrathin, undoped,
Si
[001]-oriented channel connecting elevated (bulk)
source and drain (Fig. 1). A drawback of such device is a
poor controllability of the electrostatic potential of the parts of
channel adjacent to the source and drain, because of the gate
field screening by the electrodes. In this aspect, electrostatic
properties of MOSFETs with thin source and drain extensions,
that allow the gates to overlap all the channel length, are better.
However, in the latter devices the carrier backscattering from
the drain may be rather substantial [28]. On the other hand,
in the device shown in Fig. 1, with a sufficiently thin channel
, the backscattering is negligible, because of a large
mismatch of phase space between the 2-D channel and three-dimensional (3-D) electrodes [29]. Recently, we have carried out
[30] a critical comparison of these two MOSFET devices, and
concluded that their scaling is comparable if the gate length of
the transistor with thin extensions is somewhere between the
of the
gate length and the channel length
device with elevated source and drain (Fig. 1). This means that
the total length of the transistor with extensions is larger; in this
sense the current model seems preferable.
Recent experimental results [31], [32] have shown that electron mobility in undoped 2.5-nm-thick SOI layers may be as
high as at least 250 cm /V-s, equivalent to the mean free path
nm. (This is consistent with theoretical estimates [30],
of

0018-9383/03$17.00 2003 IEEE

SVERDLOV et al.: NANOSCALE SILICON MOSFETs

1927

Fig. 2. Drain IV curves of double-gate MOSFET in the 1-D approximation

for t
2 nm (E
0:1 eV), t = 1:5 nm, and N = 3 10 cm
(Fermi energy E in the electrodes is close to 0.15 eV). Numbers show the gate
voltage values.

tion

with the effective potential energy

, and

, where

Fig. 1. Model of a double-gate MOSFETs with ultrathin intrinsic channel,

explored in this work.

(2)
[31].) Since the carrier scattering is most important in a relaof the channel near the maximum
tively short section
of the potential profile, and our goal is to study ultimate performance of sub-10-nm MOSFETs, we believe we can neglect
scattering. This allows us to use Schrdinger equation for the
electron transport description.
Recently, a more general approach based on nonequilibrium
(Keldysh) Greens functions was used to calculate some
characteristics of nanoscale MOSFETs [24], [25], [27]. However, since the possible elastic scattering (due to impurities
and interface roughness) has been neglected in these works as
well, that approach, being much more complex, is equivalent to
the Schrdinger equation solution. (The mean free path due to
inelastic electron-phonon scattering in Si at room temperature
is above 50 nm [28], [33], [34], and is evidently negligible for
sub-10-nm devices.) Indeed, we have checked [30] that this
simple approach allows to reproduce virtually perfectly the
results shown in Fig. 2 of [25].
For transistors with ultrathin channels, we had to take into
account strong lateral confinement in the direction (in Fig. 1,
axis ) perpendicular to the channel plane. As a result of this
confinement, only the first subband is populated by electrons
from two of six conduction valleys of silicon (with
, and
). The wavefunction
of these electrons is taken in the form

(1)
that is an accurate approximation for our range of channel thicknm) [35]. Substitution of (1) into the Schrdinger
ness (
equation leads to an effective 1-D equation for the wave func-

Due to weak backscattering from the source and drain, this

equation may be solved with the completely absorbing
. The electrostatic potenboundary conditions [13] at
is found from the 2-D Poisson equation with the
tial
fixed- boundary conditions deep inside the silicon electrodes
(source, drain, and gate). Charge density inside the electrodes
is derived from the uniform Fermi distribution, ensuring the
ThomasFermi screening of electric field just beneath the
electrode surfaces.
We have carried out our calculations within a broad range of
, and ; illustrations below are for
geometrical parameters
their most interesting values which allow to reach high transistor performance, but still may be implemented in practice.
, was kept a the conOne more parameter, electrode doping
cm ; this is close to the minimum doping
stant level of
still allowing relatively low device-to-device variations due to
dopant position randomness [15], [18].
II. 1-D APPROXIMATION
In the limit of sufficiently long channel
, all variables are independent on in the largest part of the channel. Assuming that this part presents the bottleneck for the current, the
transistor analysis may be significantly simplified. Such analysis was first carried out by Natori [13] (see also [17] and [21]).
Fig. 2 shows typical drain IV curves calculated within
the Natori theory corrected to take into account the effective
quantum capacitance of the 2-D electron gas inside the channel
[21]. One can see that the current saturation is perfect, and
saturation current density is very high: above 2000 A/ m even
V. Also, in
for very modest voltage swing
this limit the subthreshold characteristics have perfect slope (at
300 K, close to 60 mV/decade) and there is no drain-induced

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 9, SEPTEMBER 2003

(a)
(a)

(b)

(b)

0 h i

Fig. 3. Effective 1-D potential profile U (x) = E

e 8 numerically
calculated using the model shown in Fig. 1, for the case L = 5 nm, t = 2 nm,
t
= 1:5 nm, N = 3 10 cm ; T = 300 K, for (a) zero drain-to-source
voltage V and several values of gate voltage V and (b) for several values of
V , for fixed V
= +0:3 V. The horizontal dashed and dotted lines show the
potential plateau values calculated from the 1-D approximation, for voltages
0:026 V.
V , respectively much lower and much higher than k T =e

barrier lowering (DIBL). Unfortunately, numerical modeling indicates that for our transistor model (Fig. 1) the 1-D approximation does not always give the correct result even in the limit
. The reason for this discrepancy is that the profile of the
typically features a hump near
effective 1-D potential
the source, at positive gate voltages (Fig. 3). It is created by uncompensated space charge of electrons injected from the electrodes into the undoped channel, in the region where the gate
field is effectively screened by bulk source and drain. (In this
sense our model is not a well-tempered MOSFET [36].) It is
rather this hump, than the following long potential plateau, that
provides the real electron transport bottleneck and therefore de.
termines the transport at

(c)
Fig. 4. Drain IV curves of double-gate, ballistic MOSFETs for three values
of gate length L. Besides L, all the parameters are the same as for Fig. 2. The
drain-to-source voltage is 0.5 V, the gate voltage V is changed with a step of
0.05 V.

III. CALCULATION RESULTS

Fig. 4 shows three typical families of drain I-V curves for a
few different values of gate voltage, for gradually reduced gate

SVERDLOV et al.: NANOSCALE SILICON MOSFETs

1929

(a)

Fig. 6. Voltage gain G

@ V =@ V
of nanoscale MOSFETs as a
function of V for V = 0:5 V and several values of gate length L and oxide
thickness t .

perfect current saturation. It becomes less perfect for

nm,
nm the saturation is very weakly pronounced.
while for

(b)

(c)
Fig. 5. Subthreshold curves of nanoscale MOSFETs for the same three values
of gate length L as in Fig. 4, each for ten values of drain-source voltage V (with
a step of 0.05 V). Transistor parameters are the same as for Fig. 2, besides a
thicker oxide (t
2:5 nm). Dotted lines show the ideal slope of the curves
(60 mV/decade). Dashed lines show the estimated gate oxide leakage current.

length . The 10 nm device shows values of ON current not too

far from those given by the 1-D model (cf. Fig. 2), and an almost

The degradation is visible in Fig. 5 showing subthreshold

nm. (The
curves of almost similar devices, but with
is necessary to prevent gate oxide leakage in memory
larger
applications, for which the subthreshold curves are the most important characteristic.) For the 10-nm device the curves have
a nearly perfect slope indicated by the dashed line, negligible
DIBL, and more than nine orders of magnitude of channel curnm, the slope becomes considerrent modulation. For
ably lower than the perfect, thermally determined value, and
shows increasing DIBL as . Here, source-to-drain tunneling
along the channel becomes visible as an upward bend of the
curves (plotted on semi-log scale) at negative gate voltages. For
nm, the tunneling current dominates the subthreshold
current at almost all negative , so that the device works essentially as a tunnel transistor.
The degradation of both ON and OFF currents can be charactaken at
terized by voltage gain, i.e., derivative
at satua fixed drain current . In good MOSFETs,
ration, so this is not a very popular engineering figure-of-merit.
However, as the transistor degrades, the voltage gain becomes an
important characteristic, since digital logic circuits fundamenfor their operation. Fig. 6 shows
as
tally require
, at fixed drainsource voltage
a function of the gate voltage
V, for three different values of
. One can see that
as the gate length is decreased,
rapidly decreases, dropping
nm, i.e., at the channel length
below 1 at
about 5 nm.
A detailed analysis of our results shows that for the parameters we have used, the loss of electrostatic control of the bottleby the gate voltage , and source-to-drain
neck potential
tunneling along the channel contribute comparably to the device
.
degradation as

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Fig. 7. Threshold voltage roll-off as a function of gate length L, i.e., the

magnitude of its (negative) change relative to that for L
, for all
combinations of three values for oxide thickness t and three values for
channel thickness t. The drain-to-source voltage V is 0.5 V.

(a)

!1

At this point we have to acknowledge that as becomes comparable with channel thickness (as it does for
nm), the
of electron quantum constep-like increase of the energy
finement in the direction perpendicular to the channel plane,
that follows from our 1-D version of the Schrdinger equation
and is visible in Fig. 3, does not exactly reflect the real situation.
, leading to
In reality, this step is smoothed by a distance
a slight reduction of the potential bump and hence reducing the
transport bottleneck. This is why our results for this value of
for
may be not completely accurate. We plan to explore
this effect, using the 2-D version of the Schrdinger equation,
in the near future.
IV. PARAMETER SENSITIVITY
From the point of view of the present-day CMOS technology,
the results presented above seem very optimistic: to summarize,
they indicate that physics allows the MOSFET gate length to be
nm, still retaining the high perforscaled down to at least
mance necessary for most logic and memory circuits. However,
these results also show two major challenges on the way to approaching these physical limits in practice.
The first problem is the rapidly increasing sensitivity of
transistor characteristics to unavoidable random spreads of their
geometrical parameters, due to fabrication uncertainties. For
example, Fig. 7 shows the magnitude of decrease (roll-off)
(defined as the value of
of the threshold gate voltage
providing a certain small drain current) with a reduction of the
gate length. The plot shows that a small uncertainty in gate
dimension may lead to a large variation of . In practically
due to random fluctuations
useful devices, the variations of
should be small in comparison with the power supply
of
necessary for driving the device. For example,
voltage
for
nm, in order to keep fluctuations of
below a
reasonable limit of 50 mV, the critical dimension should be

(b)
Fig. 8. Threshold voltage dependence on (a) the channel thickness t and (b) the
oxide thickness t .

controlled better than

nm, much tighter than the farthest
ITRS projection of 0.7 nm for the critical dimension control
levelsee, e.g., Table 57 in [12].
accuracy at the
is even more sensitive to
Moreover, Fig. 8(a) shows that
variations of the channel thickness . The dependence for short
is even stronger than that expected from the dependence
on [see (2)] and
of the quantum confinement energy
reflects the loss of electrostatic control over the channel with
shrinking. For
nm, in order to keep fluctuations of
at the same level (below 50 mV), should be controlled better
nm, a very hard task indeed.
than
to the oxide thickness variations is
The sensitivity of
shown in the Fig. 8(b). It is interesting to note that the depennm. The reason for this effect is
dence changes sign at
leads mostly to a change of
that for larger a change of
device electrostatics, while for shorter devices the main effect
of the oxide thickness change is a variation of the channel

SVERDLOV et al.: NANOSCALE SILICON MOSFETs

1931

Fig. 9. Typical dependences of the total (dynamic plus static) power P ,

normalized by the total ON current I
(solid lines), and its static (dotted
lines) and dynamic (dashed line) components, on the voltage swing V , for
several values of gate length L.

(a)

length
and the corresponding change of the
source-to-drain tunneling. This crossover leads also to the
for various tox (Fig. 7).
crossing of the plots

V. POWER SCALING
Another problem arising at
nm is the growing power
consumption. In order to analyze this effect we have used a
simple model [37] for the total power in a CMOS circuits, where
the total power is a sum
(3)
of dynamic (first term) and static (second term) power dissipation. Here is the switching activity factor of the -th circuit
is its total effective capacitance including that of all
block,
the interconnects and input capacitance of transistors, is the
is the total OFF current of all transisclock frequency, and
. In contrast with
tors biased by the power supply voltage
, the on-current
participates in (3) indirectly, via the speed requirement
(4)
is the fraction of the clock period
taken
where
by the capacitance recharging constant .
The model expressed by (3) and (4) is of course rather approximate; however, it captures the basic balance between static
and dynamic power. A major advantage of this model is that the
minimum value of the specific power per unit transistor width
, on just two parameters
depends, besides
(5)

(b)
Fig. 10. Minimum total power (solid lines) and optimum V
(dashed lines)
as functions of gate length L, for several values of the ON current and two values
of the parameter  defined by (5).

where
is the total width of logic transistors in the -th ciris the total width of all transistors providing
cuit block, and
. In fact, combining (3)(5) we get
leakage current
(6)
, this ratio (i.e., the specific power per unit
For a fixed
channel width) may be readily found from the transistor charfrom fixed
we deteracteristics
necessary to sustain it.
mine the gate voltage value
is then determined as
, i.e., a result of gate
.
voltage reduction by the voltage swing equal to
Fig. 9 shows a typical dependence of the resulting power concalculated for several values of . At small
sumption on
voltages it is dominated by static power, because transistors
dynamic power domcannot be shut well, while at large
inates and leads to the growth of total power. As a result, as a

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 9, SEPTEMBER 2003

function of
displays a clear minimum. Fig. 10 shows this
minimum value of power, as well as the corresponding optimal
, as a function of gate length , for two relatively
value of
large values of . (For smaller , the plots are virtually similar
, with
and
.)
to those for
The most important features of these results are that both the
and the optimum
increase
minimum specific power
nm, due to transistor performance degradation: as
below
is decreased, the MOSFET requires larger and larger voltage
to avoid the fast growth of static power if the device
swing
leads, of course,
has not been shut well. This increase of
to the growth of dynamic power and hence of the total .
The growth of specific power in sub-10-nm transistors may
considerably exacerbate the problem of total power consumption in silicon integrated circuits that is very serious even
without account of this effectsee, e.g., [38], [39].
VI. CONCLUSION
Calculations using a simple model of quasiultimate silicon
MOSFETs (Fig. 1) show that these devices with small but plaunm) may
sible values of gate oxide and channel thickness (
retain performance acceptable for both logic and memory applinm. However,
cations even if the gate length is reduced to
nm, power per unit channel
as soon as is decreased below
width starts to grow rapidly (Fig. 10). Even more importantly,
threshold voltage becomes an extremely sensitive function of
, and
(Figs. 7 and 8), creating very serious problems for
reproducible device fabrication.
Our recent work [30] shows that both these effects are more
general than this specific model transistors with thin source
and drain extensions show virtually the same behavior if their
.
channel length is in-between values and
ACKNOWLEDGMENT
The authors wish to thank D. Antoniadis, S. Cristoloveanu, S.
Datta, B. Doyle, D. Frank, C. Hu, Z. Krivokapic, M. Lundstrom,
P. Solomon, S. Tiwari, and Y. Taur, for numerous discussions
and valuable suggestions.
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Victor A. Sverdlov received the Ph.D. degree in

physics from St. Petersburg State University, St.
Petersburg, Russia, in 1989.
From 1989 to 1999, he was a Staff Scientist at St.
Petersburg State University. He also spent a few years
as a Visiting Scientist in leading European research
centers. In 1999, he became a Staff Scientist at the
State University of New York at Stony Brook. He is
an author/co-author of over 45 original publications.
He has worked in the fields of solid-state physics,
computational physics, and nanoelectronics.

1933

Thomas J. Walls received the B.S. degree in physics

from the College of William and Mary, Williamsburg,
VA, in 1999 and the M.A. degree in physics from the
State University of New York at Stony Brook in 2002,
where he is currently pursuing the Ph.D. degree.
His current research interests span the study of
fundamental noise sensitivity of superconducting
circuits to the physical properties of MOSFET
devices at the nanometer scale.

Konstantin K. Likharev (M89) received the Ph.D.

degree in physics from Moscow State University,
Moscow, Russia, in 1969.
He is a Professor of physics at the State University
of New York at Stony Brook. From 1969 to 1988, he
was a Staff Scientist with Moscow State University,
and, from 1989 to 1991, the Head of the Laboratory
of Cryoelectronics. In 1991, he assumed his current
position. During his research career, he worked in the
fields of nonlinear classical dynamics, low-temperature solid-state physics and electronics, and nanoelectronics. He is the author/co-author of two monographs, 47 review papers
and book chapters, over 220 original publications, and 18 patents.