Document About AMLogic

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/div><div class="html_text plain"><h1> AML8726M3QuickReferenceManual</h1><p>Revision1.0
</p><p>
</p><p>
</p><p>
</p><p>D is
</p><p>Amlogic,Inc.
</p><p>tr
</p><p>ib u
</p><p>Revision:0.7 Releasedate:10/31/2010 Printingdate:7/6/2011
</p><p>te
</p><p>QuickReferenceManual
</p><p>to
<br />
</p><p>AML8726M3
</p><p>P
<br /> 1/37 AMLOGIC,Inc.Proprietary
</p><p>ro m
</p><p>as te r!
</p><p> AML8726 M3QuickReferenceManual
</p><p>Revision1.0
</p><p>D is
</p><p>tr
</p><p>ib u
</p><p>COPYRIGHT 2010Amlogic,Inc. All rights reserved. No part of this document
Transmitted, transcribed, or translated into any language inanyformorbyanymeansw
issionofAmlogic,Inc. TRADEMARKS AMLOGIC is a trademark of Amlogic, Inc. All ot
registered trademarks are property of their respective companies. DISCLAIMER Amlogi
ay make improvements and/or changes in this document or in the product described
nt at any time. Thisproductisnotintendedforuseinmedical,lifesaving,orlife
t diagrams and other information relating to products of Amlogic Inc. are included
illustrating typical applications. Consequently, complete information sufficient for
uction design is not necessarily given. Amlogic makes norepresentationsorwarrantie
otheaccuracyorcompletenessofthecontentspresentedinthisdocument. REVISIONHISTO
ate Changes Number 0.7 2011/06/17 Initialdraft 1.0 2011/06/30 RevisePinout CON
Amlogic,Inc. 3930FreedomCircle,Suite101 SantaClara,CA95054 U.S.A. www.amlogic.com
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</p><p>AMLOGIC,Inc.Proprietary
</p><p>Revision1.0
</p><p>Contents
<br />1. 2. 3. GeneralDescription....................................................
.......................................................................... 4 Featu
resSummary........................................................................
........................................................5 PinOutSpecification........
................................................................................
.................................... 9 PinOutDiagram(topview)..........................
................................................................................
............ 9 3.1PinAssignments.....................................................
...........................................................................10
</p><p>4. 5.
<br />
</p><p>OperatingConditions .......................................................
................................................................... 35 MechanicalDi
mensions.........................................................................
............................................. 36
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<br />AMLOGIC,Inc.Proprietary
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</p><p>3.2PinMultiplexingTables ....................................................
................................................................. 21
</p><p>Revision1.0
</p><p>1. GeneralDescription
<br />AML8726M3 is an advanced connected multimedia processor designed for Tablet/MI
op Box (STB), TV and highend media player applications. It integrates powerful CP
ateoftheart video decoding engine with all major peripheralstoformtheultimatelo
. TheintegratedprocessorisanARMCortexA9CPUwith32KBL1instructionand32Kdatacach
che to improve system performance. In addition, the CortexA9 CPU includes the NEO
sor to improve software media processing capability. The ARM CortexA9 CPU can run
as a wide bus connecting to the memorysubsystem.
</p><p>The graphic subsystem consists of two graphic engines and a flexible video/g
tput pipeline. The ARM Mali400 GPU handles all the OpenGL ES 1.1/2.0 and OpenVG
s, while the 2.5D graphics processor handles additional scaling, alpha, rotation an
ace conversion operations. The video output pipeline can perform advanced image cor
nd enhancements. Together, the CPU and GPU handle all operating system, networking,
face and
</p><p>Three additional processors offload the CortexA9 CPU by handling all audio
coding processing the MediaCPU and two MediaDSPs with a dedicated hardware video
MediaCPU is audio optimized and handles all audio decoding tasks. The dual MediaDS
ware decoder can decode all HD video formats including H.264, MVC, MPEG withnosi
</p><p>AML8726M3integratescompleteaudio/videoinput/outputinterfacesincludingLVDS/mini
anelinterfacewithTCON, RGB888 TTL panel interface with TCON, an HDMI1.4a transmitt
pport, CEC and PHY, four video DAC supporting composite, CVBS, YPbPr and VGA outp
audio CODEC with headphone PA and microphone bias, I2S and SPDIF digitalaudioinpu
face,aPCMaudiointerfaceandanITU601/656camerainputinterface. AML8726M3 integrates
nal blocks for digital TV broadcasting streams. The buildin three demux can proce
ms from three transport stream input interfaces, which can connect to tuner/demodul
SO7816 smart cardinterfaceandacryptoprocessorbuildintohelphandlingencryptedtraff
. The processor has rich advanced network and peripheral interfaces, including a 1
thernet MAC with RMII interface, dual USB 2.0 high speed ports (one OTG and one
th multistandard memory card controller, fourUARTinterface,fourI2Cinterface,twohi
faceandtwoPWMs. Standard development environment utilizing GNU/GCC Android tool cha
orted. Please contact your AMLOGIC sales
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</p><p>1/2/4, VC1/WMV, AVS, RealVideo and MJPEG streams. The video decoding engine
able of decoding JPEG pictures
</p><p>ro m
</p><p>gamingrelatedtasks.
</p><p>as te r!
</p><p>Revision1.0
</p><p>2. FeaturesSummary
<br />
</p><p>ro m
<br /> CPUSubsystem ARMCortexA9CPUupto1GHzfrequencyand2500DMIPS ARMv7instru
scalar,outoforderarchitecture 32KBinstructioncacheand32KBdatacache 128KBUnifi
ONandVFPcoprocessor MemoryManagementUnit Applicationbasedtrafficoptimizationus
edswitchingfabrics 3DGraphicsProcessingUnit ARMMali400GPU,250MHz Unified32K
tabandwidth 250Mpix/secand25Mtri/sec Fullsceneoversampled4Xantialiasingengine
dwidthusage OpenGLES1.1/2.0andOpenVG1.1support 2.5DGraphicsProcessor
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</p><p>Audio IF
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<br />Enhancement De-interlacer Scalar
</p><p>Revision1.0
</p><p>Fastbitbltenginewithdualinputsandsingleoutput Programmablerasteroperations(
mmablepolyphasescalingfilter Supportsmultiplevideoformats4:2:0,4:2:2and4:4:4andmu
mats(8/16/24/32bitsgraphicslayer) Fastcolorspaceconversion Advancedantiflickeringf
</p><p> CryptoEngine SupportsAESblockcipherwith128/192/256bitskeys,standard16by
eaming SupportsDES/3DESblockcipherwithElectronicCodeBook(ECB)andCipherBlockCha
nmode Supportsstandard64bitskeyforDESand192bitskeyfor3DES Supportstreaming
cksize BuildinLSFRRandomnumbergenerator Video/PictureDecoder Dualprogrammable
ithDSPinstructions Dedicatedhardwarevideodecoder H.264HP@L4.1upto1080P,MVCat
P(ISO144962) WMV/VC1SP/MP/APupto1080P AVSJiZhunProfileupto1080P MPEG2
80P(ISO11172) RealVideo8/9/10upto720P WebMuptoVGA Multiplelanguageandmult
ort Supports*.mkv,*.wmv,*.mpg,*.mpeg,*.dat,*.avi,*.mov,*.iso,*.mp4,*.rmand*.jpgf
EGandJPEGunlimitedpixelresolutiondecoding(ISO/IEC10918) SupportsJPEGthumbnail,sc
nandtransitioneffects VideoPostProcessingController Motiveadaptive3Dnoisereduc
cedmotionadaptiveedgeenhancingdeinterlacingengine 3:2pulldownsupport Programma
rforbothhorizontalandverticaldimensionforzoomandwindowing Programmablecolormana
hanceblue,green,red,faceandothercolors) Chromacoringandblackextensionprocessing
umafilter Programmablecolormatrixpipeline Videomixer:2videoplanesand2graphic
lOutput TTLandLVDS/miniLVDSpanelsupporting SingleportLVDS/miniLVDSwithTCONsu
ualgatepanelsupto1366x768resolution RGB888TTLinterfacewithTCONsupportingdigital
esolution LEDBLPWMandVGHLPWMbuildin ThreeindependentGammatableforLCDpanelt
pingtodifferentLCDpanelcolordepth
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</p><p>Revision1.0
</p><p> VideoOutput BuildinHDMI1.4atransmitterwithCEC,bothcontrollerandPHY
peedvideoDACsforanalogvideooutputincludingCVBS,SVideo,YPbPrandVGA Supportsa
ormats:480i/p,576i/p,720pand1080i/p SupportsdualvideooutputwithcombinationofLC
BS+HDMI AudioDecoderandInput/Output MediaCPUwithDSPaudioprocessing SupportsMP
ggandprogrammablewith7.1downmixing Buildin2channelsaudioDACwithheadphonepower
honeoutputandmonospeakeroutput I2S,SPDIF/IEC958andPCMserialdigitalaudiooutput
alaudiostereochanneloutputwithcombinationofAnalog+PCMorI2S+PCM OtherDigitalAudi
tputInterfaces ITU601/656parallelvideoinputwithdownscalar Supportscamerainput
itrawRGB,16bitRGBorJPEG MemoryandStorageInterface SupportsDDR31066SDRAMwith
BDDR3memory SupportsSLC/MLC/TLCNANDFlashwith4chipenablepinswithBCH60 Support
erface BuildinOneTimeProgrammingROMforkeystorage SDIOwithmemorycardcontrolle
ngSD/SDHC/SDXC/MMC/MS/MSPromemorycards Network IntegratedIEEE802.310/100FastEth
erwithRMIIinterface 50MHzclockoutputtoFastEthernetPHY WiFi/IEEE802.11supportin
talTelevisionInterface Threetransportstream(TS)inputinterfaceswiththreebuildinde
rconnectingtoexternaldigitalTV tuner/demodulatorandoneoutputTSinterface Buildin
acestocontroltuneranddemodulator CI+PCMCIAcontrollerandinterface IntegratedISO
oller IntegratedI/OControllersandInterfaces DualUSB2.0highspeedUSBI/O,oneUSB
ARTInterfacewithRTS/CTSoneinAOdomain 4xI2Cmaster/slaveinterface2xinAOdomain
Iinterfacewith3slaveselectsignals 2xPWMchannelwithfeedbackcontrollogicand4xs
ableIRremotecontroller Buildin10bitSARADCwith8inputchannelswithresistivetouch
neralPurposeIOinterfaces
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</p><p> System,PeripheralsandMisc.Interfaces Multiplepowerdomain Dedicatedalways
aintocommunicatewithexternalPMIC Integratedgeneralpurposetimers,counters,DMAcont
ratedRTCwithbatterybackupoption Single24MHzcrystaloscillatorinput Embeddeddeb
/JTAG AMPOWERpowermanagementcircuitssupportingmultiplesleepandsuspendoperatingmod
SupportsAndroidandLinuxoperatingsystems SupportsAdobeFlashPlayer10.x GNU/GCCAn
ackage 445ballLFBGA,RoHScompliant,17x17mm
</p><p>as te r!
</p><p>Revision1.0
</p><p>3. PinOutSpecification
<br />
</p><p>PinOutDiagram(topview)
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</p><p>Revision1.0
</p><p>3.1PinAssignments
<br />TheAML8726M3A/Vprocessorpinassignmentisdescribedinthefollowingtable.
</p><p>Table1.PinNameassignments
<br />BGA Ball A5 B5 C4 B4 D4 A3 B3 A2 A1 B2 B1 C3 F12 E15 C1 C2 D3 D2 E3
GPIOA_0 GPIOA_1 GPIOA_2 GPIOA_3 GPIOA_4 GPIOA_5 GPIOA_6 GPIOA_7 GPIOA_8 GPIOA_9
GPIOA_10 GPIOA_11 VDD33_EE VDD12_CPU GPIOA_12 GPIOA_13 GPIOA_14 GPIOA_15 GPIOA_1
6 GPIOA_17 GPIOA_18 GPIOA_19 Group GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GP
PIOA GPIOA GPIOA Power Power GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIOA GPIO
PIOA GPIOA GPIOA GPIOA GPIOA Pull up/down PU PU PU PU PU PU PU PU PU PU P
U PU PU PU PU PU Description General purpose input/output bank A signal 0. Pleas
ing Table2forfunctionalmultiplexinformation. General purpose input/output bank A sig
lease refer to following Table2forfunctionalmultiplexinformation. General purpose i
put bank A signal 2. Please refer to following Table2forfunctionalmultiplexinforma
al purpose input/output bank A signal 3. Please refer to following Table2forfuncti
exinformation. General purpose input/output bank A signal 4. Please refer to follow
2forfunctionalmultiplexinformation. General purpose input/output bank A signal 5. P
er to following Table2forfunctionalmultiplexinformation. General purpose input/outpu
A signal 6. Please refer to following Table2forfunctionalmultiplexinformation. Gen
e input/output bank A signal 7. Please refer to following Table2forfunctionalmulti
tion. General purpose input/output bank A signal 8. Please refer to following Table
onalmultiplexinformation. General purpose input/output bank A signal 9. Please refer
owing Table2forfunctionalmultiplexinformation. General purpose input/output bank A s
0. Please refer to following Table2forfunctionalmultiplexinformation. General purpo
output bank A signal 11. Please refer to following Table2forfunctionalmultiplexinf
ype I/O I/O I/O
</p><p>ro m
</p><p>P
</p><p>to
</p><p>3.3Vpower 1.2Vpower
</p><p>GPIOA_20
</p><p>GPIOA_21 GPIOA_22 GPIOA_23 GPIOA_24
</p><p>GPIOA_25 GPIOA_26 GPIOA_27
</p><p>General purpose input/output bank A signal 12. Please refer to following Tabl
ctionalmultiplexinformation. General purpose input/output bank A signal 13. Please r
following Table2forfunctionalmultiplexinformation. General purpose input/output bank
nal 14. Please refer to following Table2forfunctionalmultiplexinformation. General
put/output bank A signal 15. Please refer to following Table2forfunctionalmultipl
on. General purpose input/output bank A signal 16. Please refer to following Table2
nalmultiplexinformation. General purpose input/output bank A signal 17. Please refer
owing Table2forfunctionalmultiplexinformation. General purpose input/output bank A s
output bank A signal 19. Please refer to following Table2forfunctionalmultiplexinf
eneral purpose input/output bank A signal 20. Please refer to following Table2forf
ltiplexinformation. General purpose input/output bank A signal 21. Please refer to
g Table2forfunctionalmultiplexinformation. General purpose input/output bank A signa
ease refer to following Table2forfunctionalmultiplexinformation. General purpose inp
put bank A signal 23. Please refer to following Table2forfunctionalmultiplexinform
ral purpose input/output bank A signal 24. Please refer to following Table2forfunc
plexinformation. General purpose input/output bank A signal 25. Please refer to fol
ble2forfunctionalmultiplexinformation. General purpose input/output bank A signal 26
e refer to following Table2forfunctionalmultiplexinformation. General purpose input
ank A signal 27. Please refer to following
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</p><p>as te r!
<br />I/O I/O I/O I/O I/O I/O I/O I/O I/O P P I/O I/O I/O I/O I/O I/O I/O I/
I/O
</p><p>Revision1.0
</p><p>Table2 forfunctionalmultiplexinformation. F2 G3 H5 G2 H3 H2 J3 J1 F15 F17
6 L5 L4 M4 J2 K3 K2 L3 F18 L1 L2 M3 M2 F6 GPIOB_0 GPIOB_1 GPIOB_2 GPIOB_3 GPIOB_
B_6 GPIOB_7 VDD12_EE VDD12_CPU VDD33_EE GPIOB_8 GPIOB_9 GPIOB_10 GPIOB_11 GPIOB_
12 GPIOB_13 GPIOB_14 GPIOB_15 GPIOB_16 GPIOB_17 GPIOB_18 GPIOB_19 VDD12_CPU GPIO
B_20 GPIOB_21 GPIOB_22 GPIOB_23 GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB Power
er Power GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB GPIOB
PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD PD General purpose input/
fer to following Table2forfunctionalmultiplexinformation. General purpose input/outp
B signal 1. Please refer to following Table2forfunctionalmultiplexinformation. Gen
ose input/output bank B signal 2. Please refer to following Table2forfunctionalmult
rmation. General purpose input/output bank B signal 3. Please refer to following Tab
nctionalmultiplexinformation. General purpose input/output bank B signal 4. Please re
o following Table2forfunctionalmultiplexinformation. General purpose input/output ba
ignal 5. Please refer to following Table2forfunctionalmultiplexinformation. General
nput/output bank B signal 6. Please refer to following Table2forfunctionalmultiplex
on. General purpose input/output bank B signal 7. Please refer to following Table2
almultiplexinformation. 1.2Vpower 1.2Vpower 3.3Vpower General purpose input/output
gnal 8. Please refer to following Table2forfunctionalmultiplexinformation. General
put/output bank B signal 9. Please refer to following Table2forfunctionalmultiplexi
on. General purpose input/output bank B signal 10. Please refer to following Table2
nalmultiplexinformation. General purpose input/output bank B signal 11. Please refer
lowing Table2forfunctionalmultiplexinformation. General purpose input/output bank B
12. Please refer to following Table2forfunctionalmultiplexinformation. General purp
/output bank B signal 13. Please refer to following Table2forfunctionalmultiplexin
General purpose input/output bank B signal 14. Please refer to following Table2forf
lmultiplexinformation. General purpose input/output bank B signal 15. Please refer t
wing Table2forfunctionalmultiplexinformation. General purpose input/output bank B sig
/output bank B signal 17. Please refer to following Table2forfunctionalmultiplexinf
. General purpose input/output bank B signal 18. Please refer to following Table2fo
almultiplexinformation. General purpose input/output bank B signal 19. Please refer
owing Table2forfunctionalmultiplexinformation. 1.2Vpower General purpose input/outpu
signal 20. Please refer to following Table2forfunctionalmultiplexinformation. Gene
se input/output bank B signal 21. Please refer to following Table2forfunctionalmul
mation. General purpose input/output bank B signal 22. Please refer to following Ta
ctionalmultiplexinformation. General purpose input/output bank B signal 23. Please
following Table2forfunctionalmultiplexinformation. 3.3Vpower General purpose input/o
ank D signal 0. Please refer to following Table3forfunctionalmultiplexinformation.
rpose input/output bank D signal 1. Please refer to following Table3forfunctionalm
ormation. General purpose input/output bank D signal 2. Please refer to following T
nctionalmultiplexinformation. General purpose input/output bank D signal 3. Please r
al 4. Please refer to following Table3forfunctionalmultiplexinformation. General p
t/output bank D signal 5. Please refer to following Table3forfunctionalmultiplexin
I/O I/O I/O I/O I/O I/O I/O I/O
</p><p>ro m
</p><p>P
</p><p>to
</p><p>te
</p><p>ib u
</p><p>
</p><p>GPIOB GPIOB GPIOB GPIOB Power
</p><p>PD PD PD PD
</p><p>tr
</p><p>D is
</p><p>VDD33_EE GPIOD_0 GPIOD_1 GPIOD_2 GPIOD_3 GPIOD_4 GPIOD_5 GPIOD_6
</p><p> PD PD PD PD PD PD PD
</p><p>N3 N1 N2 P2 P3 R3 R4
</p><p>GPIOD GPIOD GPIOD GPIOD GPIOD GPIOD GPIOD
</p><p>General purpose input/output bank D signal 6. Please refer to following I/O
</p><p> 11/37
</p><p>as te r!
<br />P P P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P I/O I/O I/O I
</p><p>Revision1.0
</p><p>Table3 forfunctionalmultiplexinformation. R2 T3 T2 M5 N5 N6 P5 P4 R1 R5 T6
2 U3 V6 U4 U6 Y2 W5 V3 V4 W3 U5 W2 Y5 Y4 Y3 GPIOD_7 GPIOD_8 GPIOD_9 GPIOC_0 GPI
OC_3 GPIOC_4 GPIOC_5 GPIOC_6 GPIOC_7 GPIOC_8 GPIOC_9 VDD12_CPU RTC_VBAT RTC_XOUT
RTC_XIN RTC_AVSS RTC_GPO GPIOAO_0 GPIOAO_1 GPIOAO_2 GPIOAO_3 VDD12_AO VDD12_AO
GPIOAO_4 GPIOAO_5 GPIOAO_6 GPIOAO_7 GPIOD GPIOD GPIOD GPIOC GPIOC GPIOC GPIOC GPIOC GP
C GPIOC GPIOC GPIOC GPIOC Power RTC RTC RTC RTC RTC GPIOAO GPIOAO GPIOAO PD PD
D PD PD PU PU Z General purpose input/output bank D signal 7. Please
unctionalmultiplexinformation. General purpose input/output bank D signal 8. Please
o following Table3forfunctionalmultiplexinformation. General purpose input/output ba
put/output bank C signal 0. Please refer to following Table3forfunctionalmultiplexi
on. General purpose input/output bank C signal 1. Please refer to following Table3
almultiplexinformation. General purpose input/output bank C signal 2. Please refer
ing Table3forfunctionalmultiplexinformation. General purpose input/output bank C sig
lease refer to following Table3forfunctionalmultiplexinformation. General purpose i
put bank C signal 4. Please refer to following Table3forfunctionalmultiplexinformat
ral purpose input/output bank C signal 5. Please refer to following Table3forfunct
lexinformation. General purpose input/output bank C signal 6. Please refer to follo
e3forfunctionalmultiplexinformation. General purpose input/output bank C signal 7.
fer to following Table3forfunctionalmultiplexinformation. General purpose input/outp
C signal 8. Please refer to following Table3forfunctionalmultiplexinformation. Ge
se input/output bank C signal 9. Please refer to following Table3forfunctionalmulti
mation. I/O I/O I/O I/O I/O I/O I/O I/O
</p><p>ro m
</p><p>1.2Vpower
</p><p>RTCbatterypowersupplyinput RTC32Kcrystaloutput RTC32Kcrystalinput
</p><p>P
</p><p>RTCanalogpowerground
</p><p>to
</p><p>RTCtimercontrolledoutput
</p><p>te
</p><p>GPIOAO Power Power
</p><p>Z
</p><p>General purpose input/output bank AO signal 0. Please refer to following Table
nctionalmultiplexinformation. General purpose input/output bank AO signal 1. Please r
to following Table4forfunctionalmultiplexinformation. General purpose input/output b
signal 2. Please refer to following Table4forfunctionalmultiplexinformation. Gener
e input/output bank AO signal 3. Please refer to following Table4forfunctionalmulti
mation. 1.2Vpower 1.2Vpower General purpose input/output bank AO signal 4. Please r
llowing Table4forfunctionalmultiplexinformation. General purpose input/output bank AO
ut/output bank AO signal 6. Please refer to following Table4forfunctionalmultiplexi
on. General purpose input/output bank AO signal 7. Please refer to following Table4
onalmultiplexinformation. 3.3Vpower
</p><p>ib u
</p><p>
</p><p>GPIOAO
</p><p>PU
</p><p>GPIOAO
</p><p>PU Z Z PU PU PU PU PD
</p><p>tr
</p><p>GPIOAO
</p><p>D is
</p><p>GPIOAO
</p><p>VDD33_AO GPIOAO_8 GPIOAO_9
</p><p>Power GPIOAO GPIOAO GPIOAO GPIOAO System Power USB
</p><p>V5
</p><p>AA3 AA1 AA2 AB3 F16 AB2
</p><p>GPIOAO_10 GPIOAO_11 TEST_N RESET_N VDD12_EE USBA_ID
</p><p>General purpose input/output bank AO signal 8. Please refer to following Table
nctionalmultiplexinformation. General purpose input/output bank AO signal 9. Please r
se input/output bank AO signal 11. Please refer to following Table4forfunctionalmul
ormation. Masterresetinput 1.2Vpower USBOTGminireceptacleidentifierbetweenminiA
</p><p> 12/37
</p><p>as te r!
<br />I/O I/O I/O I/O I/O P AP AO AI AP OD I/O I/O I/O I/O P P I/O I/O I/O
</p><p>Revision1.0
</p><p>AB4 AC1 AA5 AC2 AD1 W6 AA4 AB5 AE1 AD2 AE2 AC3 AE3 AD3 AC4 AD4 AC5 AE5
7 AA7 AA8 W7 AD7 AC8 AB8 AB9 AD8 AC9 AE9 Y8 Y7 AA9 AA10 Y6 AD9 AC10 AC11 AC
D12 AD10
</p><p>USBA_VBUS USBA_DP USBA_VSSA USBA_DM USBA_TXRTUNE USB_VDD25 USB_VDD33 USBB_
VSSA USBB_TXRTUNE USBB_DM USBB_DP USBB_VBUS LED_CS0 VGHL_CS1 SARADC_CH7 SARADC_C
H6 SARADC_CH5 SARADC_CH4 SARADC_CH3 SARADC_CH2 SARADC_CH1 SARADC_CH0 AVDD25_ADC
AVSS25_ADC LVDS_AVSS25 LVDS_5N LVDS_5P LVDS_AVDD25 LVDS_4N LVDS_4P LVDS_3N LVDS_3
P LVDS_CKN LVDS_CKP LVDS_AVSS25
</p><p>USB USB USB USB USB USB USB USB USB USB USB USB LCDPanel LCDPanel ADC
C Power Power Power LVDS LVDS Power LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVDS LVD
</p><p>
</p><p>USBOTGcablepowerdetection USBOTGpositivedatasignal USBground USBOTGnegati
rtBexternalcompensationresistorconnection USB2.5Vpower USB3.3Vpower USBground US
ensationresistorconnection USBhostnegativedatasignal USBhostpositivedatasignal US
tection LEDbacklightcurrentfeedback LCDVGHLcurrentfeedback ADCchannel7input ADC
nel5input ADCchannel4input ADCchannel3input ADCchannel2input ADCchannel1inpu
</p><p>AI AIO AP AIO A AP AP AP A AIO AIO AO AO AI
</p><p>ro m
</p><p>AnalogpowergroundforLVDS LVDSdata5negativeoutput LVDSdata5positiveoutput A
ly2.5VforLVDS LVDSdata4negativeoutput LVDSdata3negativeoutput LVDSdata3positive
ativeoutput LVDSClockpositiveoutput AnalogpowergroundforLVDS LVDSportcompensative
in Analogpowersupply2.5VforLVDS LVDSdata5negativeoutput LVDSdata5positiveoutput
orLVDS LVDSdata1negativeoutput LVDSdata1positiveoutput LVDSdata0negativeoutput
put AnalogpowergroundforHDMI HDMITMDSdata2+ HDMITMDSdata2 Analogpowersupply3.3
HDMITMDSdata1 HDMIExternalresisterreference AnalogpowergroundforHDMI HDMITMDSda
</p><p>P
</p><p>AnalogpowergroundforADC
</p><p>to
</p><p>LVDSdata4Positiveoutput
</p><p>LVDS_REXT_600 LVDS_AVDD25 LVDS_2N LVDS_2P
</p><p>LVDS_AVSS25 LVDS_1N LVDS_1P LVDS_0P
</p><p>tr
</p><p>ib u
</p><p>LVDS LVDS LVDS LVDS HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI HDMI LVDS
</p><p>te
</p><p>
</p><p>D is
</p><p>
</p><p>LVDS_0N
</p><p>HDMI_AVSS33 HDMITX_2P HDMITX_2N
</p><p>AD14
</p><p>HDMI_AVDD33 HDMITX_1P HDMITX_1N HDMIREXT_5K HDMI_AVSS33 HDMITX_0P
</p><p> 13/37
</p><p>as te r!
<br />AI AI AI AI AI AI AI AI AP AP AP AO AO AP AO AO
</p><p><b>AO AO AO AO AP A AP AO AO
</b><br />AP
</p><p><b>AO AO AO AO
</b><br />AP AO AO AP AO AO A AP AO
</p><p>Revision1.0
</p><p>AC12 Y11 AD11 AE11 AA11 AA12 Y12 R6 G7 AE15 AD15 AB11 AB12 AA13 AA14 AB1
6 J6 AE17 W19 AD17 AC18 R20 AD18 AC22 R21 AD21 AE21 U20 AC24 AC25 AB22 V20 AD
1 AD22 AC23 AE23 AD23 AE25 AD24
</p><p>HDMITX_0N HDMI_AVDD33 HDMITX_CKP HDMITX_CKN PLLS_EXFIL PLLS_EXT_IREF HDMI
_PLL_AVDD33 VDD12_EE VDD33_EE XTAL24_IN XTAL24_OUT BSD_EN GPIOC_10 GPIOC_11 GPIO
C_12 GPIOC_13 GPIOC_14 GPIOC_15 AVSS25_DPLL AVDD25_DPLL VDD12_EE DDR3_DQ_4 SSTL_V
DD DDR3_DQ_6 DDR3_DQ_2 SSTL_VDD DDR3_DQ_0 DDR3_DM_0 SSTL_VDD DDR3_DQS_N_0 DDR3_DQ
S_0 SSTL_VDD DDR3_DQ_5 DDR3_DQ_7 DDR3_DQ_3 SSTL_VDD
</p><p>HDMI HDMI HDMI HDMI HDMI HDMI HDMI Power Power System System System GPIOC
IOC GPIOC GPIOC Power Power Power DDR Power DDR DDR Power DDR DDR DDR DDR Power
</p><p> Z Z Z Z Z Z
</p><p>HDMITMDSdata0 Analogpowersupply3.3VforHDMI HDMITMDSclock+signal HDMITMDS
ilterforPLL ExternalresisterreferenceforPLL5K_1%toGND Analogpowersupply3.3Vfor
wer 24MHzcrystaloscillatorinput 24MHzcrystaloscillatoroutput TBD
</p><p>AO AP AO AO A A AP P P
</p><p>ro m
</p><p>General purpose input/output bank C signal 10. Please refer to following Table
nctionalmultiplexinformation. General purpose input/output bank C signal 11. Please r
signal 12. Please refer to following Table3forfunctionalmultiplexinformation. Gener
e input/output bank C signal 13. Please refer to following Table3forfunctionalmulti
mation. General purpose input/output bank C signal 14. Please refer to following Tab
nctionalmultiplexinformation. General purpose input/output bank C signal 15. Please r
to following Table3forfunctionalmultiplexinformation. AnalogpowergroundforDigitalP
Analogpowersupply2.5VforDigitalPLL DDR3SDRAMdataBusbit4 DDR3SDRAMpowersupply1
R3SDRAMdataBusbit2 DDR3SDRAMdataBusbit0
</p><p>P
</p><p>to
</p><p>DDR3SDRAMpowersupply1.5V DDR3SDRAMdatamask0 DDR3SDRAMpowersupply1.5V DDR
lementary0 DDR3SDRAMdataStrobe0 DDR3SDRAMdowersupply1.5V DDR3SDRAMdataBusbit
AMdataBusbit3
</p><p>te
</p><p>
</p><p>ib u
</p><p>
</p><p>Power DDR DDR DDR
</p><p>
</p><p>
</p><p>tr
</p><p>Power DDR DDR Power DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR
</p><p>
</p><p>DDR3SDRAMpowersupply1.5V DDR3SDRAMdataBusbit1 DDR3SDRAMdataBusbit11 DD
Mpowersupply1.5V DDR3SDRAMdataBusbit13 DDR3SDRAMdataMask1 DDR3SDRAMdataBusb
RAMdataStrobeComplementary1 DDR3SDRAMdataBusbit12 DDR3SDRAMdataBusbit14 DDR3
taBusbit8
</p><p>DDR3_DQ_1 DDR3_DQ_9
</p><p>D is
</p><p>DDR3_DQ_11
</p><p>SSTL_VDD
</p><p>DDR3_DQ_13 DDR3_DM_1 DDR3_DQ_15 DDR3_DQS_1
</p><p>AD20
</p><p>DDR3_DQS_N_1 DDR3_DQ_12 DDR3_DQ_14 DDR3_DQ_10 DDR3_DQ_8
</p><p> 14/37
</p><p>as te r!
<br />I I/O I/O I/O I/O I/O I/O AP AP P I/O P I/O I/O P I/O O P I/O I/O P
I/O I/O I/O I/O I/O I/O
</p><p>AI AO
</p><p>Revision1.0
</p><p>AC17 Y16 AB23 AB24 AA16 Y17 AA17 M21 AB17 AB18 AA18 Y19 AA19 AA20 AB20 A
1 W21 V21 V22 U22 U21 T21 T20 R22 P22 P21 N21 P20 L22 N20 M22 M24 L23 Y14 A
</p><p>DDR3_VREF DDR3_PZQ DDR3_CK DDR3_CK_B DDR3_RAS_B DDR3_ODT1 DDR3_ODT0 VDD12_EE
DDR3_CAS_B DDR3_CS1_B DDR3_WE_B DDR3_BA_2 DDR3_A_2 DDR3_A_9 DDR3_A_7 DDR3_A_13 DDR3_A_
5 DDR3_A_0 DDR3_A_3 DDR3_BA_0 DDR3_CS0_B DDR3_A_8 DDR3_A_14 DDR3_A_6 DDR3_A_11 DDR3_A
R3_A_4 DDR3_A_12 DDR3_BA_1 DDR3_A_15 DDR3_A_10 DDR3_RST_B DDR3_RET_N DDR3_CKE_0 DDR3_CK
E_1 DDR3_CK_1 VDD12_EE DDR3_DQ_22 DDR3_DQ_18 DDR3_DQ_16 DDR3_DM_2
</p><p>DDR DDR DDR DDR DDR DDR DDR Power DDR DDR DDR DDR DDR DDR DDR DDR DDR
R DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR DDR D
R DDR
</p><p>
</p><p>DDR3SDRAMreferencevoltage ReferencepinforZQcalibration DDR3SDRAMPortAclock
MPortAclockoutputcomplementary RowAddressStrobe Ondietermination1 Ondietermina
ddressStrobe DDR3SDRAMportBchipselectoutput1 WriteEnable DDR3SDRAMbankaddress2
DDR3SDRAMaddressbusbit9 DDR3SDRAMaddressbusbit7 DDR3SDRAMaddressbusbit13 DDR
MaddressBusbit0 DDR3SDRAMaddressBusbit3 DDR3SDRAMbankaddress0
</p><p>A A O O O O O P O O O O
</p><p>ro m
</p><p>DDR3SDRAMportBchipselectoutput0 DDR3SDRAMaddressbusbit8 DDR3SDRAMaddres
ssbusbit6 DDR3SDRAMaddressbusbit1 DDR3SDRAMaddressbusbit4
</p><p>P
</p><p>DDR3SDRAMaddressbusbit11
</p><p>to
</p><p>DDR3SDRAMaddressbusbit12 DDR3SDRAMaddressbusbit15 DDR3SDRAMaddressbusbi
</p><p>DDR3SDRAMbankaddress1
</p><p>te
</p><p>DDR3SDRAMReset.ActiveLOW. DDR3standbycontrolinput.LOWisStandby.HIGHisnorm
nableoutput0 DDR3SDRAMclockenableoutput1 DDR3SDRAMPortBclockoutput DDR3SDRAMP
tary Digitalpowersupply1.2V DDR3SDRAMdatabusbit20 DDR3SDRAMdatabusbit22 DDR3
tabusbit16 DDR3SDRAMdatamask2 DDR3SDRAMdatastrobe2complementary DDR3SDRAMdata
1 DDR3SDRAMdatabusbit23 Digitalpowersupply1.2V DDR3SDRAMdatabusbit19 DDR3SDR
sbit27 DDR3SDRAMdatabusbit25
</p><p>ib u
</p><p>
</p><p>DDR3_CK_1_N DDR3_DQ_20
</p><p>Power
</p><p>tr
</p><p>D is
</p><p>U24 U25 N24 Y15 N25 N23
</p><p>DDR3_DQS_N_2 DDR3_DQS_2 DDR3_DQ_23
</p><p>M23
</p><p>DDR3_DQ_21 VDD12_EE DDR3_DQ_19 DDR3_DQ_17 DDR3_DQ_27 DDR3_DQ_25
</p><p>W23 W25
</p><p> 15/37
</p><p>as te r!
<br />O O O O O O O O O O O O O O O O O O O O I O O O O P I/O I/O
</p><p>Revision1.0
</p><p>W24 V23 V24 T24 R23 R25 R24 P23 P24 L20 L21 K21 M20 J21 J20 K20 H20 G2
23 J25 H23 H22 H24 G23 G25 G24 H21 F23 F24 E23 E25 E24 D23 F20 Y18
</p><p>DDR3_DQ_29 DDR3_DM_3 DDR3_DQ_31 DDR3_DQS_3 DDR3_DQS_N_3 DDR3_DQ_28 DDR3_DQ_30
DDR3_DQ_26 DDR3_DQ_24 EFUSE_VDAC_AVDD25 VDAC_G VDAC_B EFUSE_VDAC_AVDD25 VDAC_R VDA
C_AVSS25 VDAC_AVSS25 VDAC_COMP VDAC_REXT VDAC_CVBS VDD33_SD AUD_LINE_OUT_L AUD_L
INE_OUT_R AUD_AVSS_HS AUD_AVDD25_HS AUD_AVSS AUD_AVDD25 AUD_HS_RIGHT AUD_MIC_BIA
S AUD_HS_LEFT AUD_VCM AUD_VREF_DAC AUD_VREF_ADC AUD_SPK AUD_LINEIN_R_3 AUD_LINEIN_
R_2 AUD_LINEIN_R_1 AUD_LINEIN_L_1 AUD_LINEIN_L_2 AUD_SPK+ VDD12_EE CARD_0 CARD_1
CARD_2 CARD_3 CARD_4 VDD12_CPU
</p><p>DDR DDR DDR DDR DDR DDR DDR DDR DDR Power VideoDAC VideoDAC Power Video
ideoDAC VideoDAC VideoDAC Power Audio Audio Power Power Power Power Audio Audio
Audio Audio Audio Audio Audio
</p><p>
</p><p>DDR3SDRAMdatabusbit29 DDR3SDRAMdatamask3 DDR3SDRAMdatabusbit31 DDR3SD
trobe3complementary DDR3SDRAMdatabusbit28 DDR3SDRAMdatabusbit30 DDR3SDRAMdata
4 Analogpowersupply2.5VforeFuse VideoDACgreenoutputsignal VideoDACblueoutputsi
y2.5VforeFuse VideoDACredoutputsignal VideoDACground VideoDACground VideoDAC
ACvoltagereference 3.3Vpower
</p><p>I/O O I/O I/O I/O I/O I/O I/O I/O
</p><p>
</p><p>VideoDACcompositevideooutputsignal
</p><p>ro m
</p><p>AudioDAClineoutleftchannelanalogoutput AudioDAClineoutrightchannelanalog
oundforheadphonepoweramplifier Analogpowersupply2.5Vforheadphonepoweramplifier An
dforaudioADCandDAC Analogpowersupply2.5VforaudioADCandDAC AudioDACheadphonep
nalogoutput Biasingvoltageoutputformicrophone
</p><p>P
</p><p>to
</p><p>
<br />
</p><p>AudioDACheadphonepoweramplifierleftchannelanalogoutput AudioDACandADCcompe
torconnection AudioDACreferencevoltage AudioADCreferencevoltage AudioDACmonospeak
loutputminus Audiostereolinein3rightchannel Audiostereolinein2rightchannel Au
el Audiostereolinein1leftchannel Audiostereolinein2leftchannel Audiostereolin
ospeakerdifferentialoutputplus 1.2Vpower
</p><p>te
</p><p>ib u
</p><p>tr
</p><p>Audio Audio
</p><p>
</p><p>D is
</p><p>AUD_LINEIN_L_3
</p><p>Audio Audio Power SDIO SDIO SDIO SDIO SDIO
</p><p> PU PU PU PU PU PU
</p><p>G20 C24 F22 B24 E21 F7
</p><p>Card reader multiplexing pin 0. Please refer to following Table7 for functio
ultiplexinformation. Card reader multiplexing pin 1. Please refer to following Table
nctional I/O multiplexinformation. Card reader multiplexing pin 2. Please refer to f
ng Table7 for functional I/O multiplexinformation. Card reader multiplexing pin 3. P
efer to following Table7 for functional I/O multiplexinformation. Card reader multipl
g pin 4. Please refer to following Table7 for functional I/O multiplexinformation.
P
</p><p>Power
</p><p> 16/37
</p><p>as te r!
<br />AP AO AO AP AO AP A AP A P AO AO AP AP AP AP AO AO AO A A A AO AI
</p><p>
</p><p>Revision1.0
</p><p>D21 D20 E20 E19 F8 D24 D22 C25 F21 B25 F14 H6 D14 A24 C23 A23 B23 F9
19
</p><p>CARD_5 CARD_6 CARD_7 CARD_8 VDD12_CPU BOOT_0 BOOT_1 BOOT_2 BOOT_3 BOOT_4
BOOT_5 VDD33_EE BOOT_6 BOOT_7 BOOT_8 BOOT_9 BOOT_10 VDD12_CPU BOOT_11 BOOT_12 BO
OT_13 BOOT_14 BOOT_15 BOOT_16 BOOT_17 GPIOX_0
</p><p>SDIO SDIO SDIO SDIO Power NAND NAND NAND NAND NAND NAND Power NAND NAND NAND
D Power NAND NAND NAND NAND NAND NAND NAND
</p><p>PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PD
</p><p>Card reader multiplexing pin 5. Please refer to following Table7 for functio
ultiplexinformation. Card reader multiplexing pin 6. Please refer to following Table
nctional I/O multiplexinformation. Card reader multiplexing pin 7. Please refer to f
ng Table7 for functional I/O multiplexinformation. Card reader multiplexing pin 8. P
efer to following Table7 for functional I/O multiplexinformation. 1.2Vpower Boot dev
tiplexing pin 0. Please refer to following Table8 for functional multiplexinformati
evice multiplexing pin 1. Please refer to following Table8 for functional multiplex
ion. Boot device multiplexing pin 2. Please refer to following Table8 for functiona
exinformation. Boot device multiplexing pin 3. Please refer to following Table8 for
al multiplexinformation. Boot device multiplexing pin 4. Please refer to following
r functional multiplexinformation. Boot device multiplexing pin 5. Please refer to
Table8 for functional multiplexinformation. P I/O I/O I/O I/O I/O I/O
</p><p>Boot device multiplexing pin 6. Please refer to following Table8 for functio
ltiplexinformation. Boot device multiplexing pin 7. Please refer to following Table
tional I/O multiplexinformation. Boot device multiplexing pin 8. Please refer to f
ble8 for functional I/O multiplexinformation. Boot device multiplexing pin 9. Pleas
following Table8 for functional I/O multiplexinformation.
</p><p>to
</p><p>Boot device multiplexing pin 10. Please refer to following Table8 for I/O f
ltiplexinformation. P Boot device multiplexing pin 11. Please refer to following Ta
I/O functionalmultiplexinformation. Boot device multiplexing pin 12. Please refer t
ng Table8 for I/O functionalmultiplexinformation. Boot device multiplexing pin 13.
er to following Table8 for I/O functionalmultiplexinformation. Boot device multiple
4. Please refer to following Table8 for functionalmultiplexinformation. Boot device
xing pin 15. Please refer to following Table8 for functionalmultiplexinformation.
multiplexing pin 16. Please refer to following Table8 for functionalmultiplexinform
ot device multiplexing pin 17. Please refer to following Table8 for functionalmult
ation. General purpose input/output bank X signal 0. Please refer to following Tab
onalmultiplexinformation. General purpose input/output bank X signal 1. Please refer
owing Table5forfunctionalmultiplexinformation. General purpose input/output bank X s
. Please refer to following Table5forfunctionalmultiplexinformation. General purpos
utput bank X signal 3. Please refer to following Table5forfunctionalmultiplexinfor
eral purpose input/output bank X signal 4. Please refer to following Table5forfunc
plexinformation. General purpose input/output bank X signal 5. Please refer to foll
le5forfunctionalmultiplexinformation. I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P
</p><p>1.2Vpower
</p><p>tr
</p><p>D is
</p><p>D17 B19 C21 B18 C17 Y20 D18
</p><p>GPIOX_1
</p><p>GPIOX_2 GPIOX_3 GPIOX_4 GPIOX_5
</p><p>VDD12_EE GPIOX_6
</p><p>ib u
</p><p>GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX Power GPIOX
</p><p>te
</p><p>PU PU PU PU PU PU PU PU PU PU PU
</p><p> PU
</p><p>1.2Vpower
</p><p>General purpose input/output bank X signal 6. Please refer to following I/O
unctionalmultiplexinformation.
</p><p>P
</p><p> 17/37
</p><p>ro m
</p><p>3.3Vpower
</p><p>as te r!
<br />P
</p><p>Revision1.0
</p><p>B17 C16 B16 C15 A15 C18 M6 E18 A17 E22 A19 E16 A25 D15 A11 Y13 E14 B21
C14 E17 C13
</p><p>GPIOX_7 GPIOX_8 GPIOX_9 GPIOX_10 GPIOX_11 GPIOX_12 VDD12_CPU GPIOX_13 GPI
OX_14 GPIOX_15 GPIOX_16 GPIOX_17 GPIOX_18 GPIOX_19 GPIOX_20 VDD33_EE GPIOX_21 GP
IOX_22 GPIOX_23 GPIOX_24 GPIOX_25 GPIOX_26 GPIOX_27 GPIOX_28 VDD12_CPU GPIOX_29
GPIOX_30 GPIOX_31 GPIOX_32 GPIOX_33 GPIOX_34 GPIOX_35 GPIOY_0 GPIOY_1 GPIOY_2
</p><p>GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX Power1.2V GPIOX GPIOX GPIOX GPIOX GPIOX
GPIOX
</p><p>PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU
</p><p>General purpose input/output bank X signal 7. Please refer to following Table
tionalmultiplexinformation. General purpose input/output bank X signal 8. Please ref
llowing Table5forfunctionalmultiplexinformation. General purpose input/output bank X
l 9. Please refer to following Table5forfunctionalmultiplexinformation. General pu
/output bank X signal 10. Please refer to following Table5forfunctionalmultiplexin
General purpose input/output bank X signal 11. Please refer to following Table5for
ultiplexinformation. General purpose input/output bank X signal 12. Please refer to
ng Table5forfunctionalmultiplexinformation. 1.2Vpower General purpose input/output
nput/output bank X signal 14. Please refer to following Table5forfunctionalmultiple
ion. General purpose input/output bank X signal 15. Please refer to following Table
onalmultiplexinformation. General purpose input/output bank X signal 16. Please refe
lowing Table5forfunctionalmultiplexinformation. General purpose input/output bank X
17. Please refer to following Table5forfunctionalmultiplexinformation. General purp
/output bank X signal 18. Please refer to following Table5forfunctionalmultiplexin
General purpose input/output bank X signal 19. Please refer to following Table5for
ultiplexinformation. General purpose input/output bank X signal 20. Please refer to
ng Table5forfunctionalmultiplexinformation.
</p><p>I/O I/O I/O I/O I/O I/O P
</p><p>ro m
</p><p>Power
<br />GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX
</p><p>3.3Vpower
</p><p>ib u
</p><p>General purpose input/output bank X signal 21. Please refer to following Tabl
ctionalmultiplexinformation. General purpose input/output bank X signal 22. Please r
put/output bank X signal 24. Please refer to following Table5forfunctionalmultiplex
on. General purpose input/output bank X signal 25. Please refer to following Table5
nalmultiplexinformation. General purpose input/output bank X signal 26. Please refer
owing Table5forfunctionalmultiplexinformation. General purpose input/output bank X s
output bank X signal 28. Please refer to following Table5forfunctionalmultiplexinf
</p><p>P
</p><p>to
</p><p>te
</p><p>Power
</p><p>1.2Vpower General purpose input/output bank X signal 29. Please refer to fol
ble5forfunctionalmultiplexinformation. General purpose input/output bank X signal 30
e refer to following Table5forfunctionalmultiplexinformation. General purpose input
ank X signal 31. Please refer to following Table5forfunctionalmultiplexinformation.
urpose input/output bank X signal 32. Please refer to following Table5forfunctional
nformation. General purpose input/output bank X signal 33. Please refer to following
orfunctionalmultiplexinformation. General purpose input/output bank X signal 34. Ple
er to following Table5forfunctionalmultiplexinformation. General purpose input/outpu
einput/outputbankY signal0.PleaserefertofollowingTable6 forfunctionalmultiplexinfo
neralpurposeinput/outputbankY signal1.PleaserefertofollowingTable6 forfunctionalmu
rmation. Generalpurposeinput/outputbankY signal2.PleaserefertofollowingTable6 forf
ltiplexinformation.
</p><p>GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX GPIOX GPIOY GPIOY GPIOY
</p><p>PU PU PU PU PU PU PU
</p><p>tr
</p><p>D is
</p><p>B12 B13 C12
</p><p>A13 C11 B14 B11
</p><p>PU PU PU
</p><p> 18/37
</p><p>as te r!
<br />I/O I/O I/O I/O I/O I/O I/O I/O
</p><p>P
<br />I/O I/O I/O I/O I/O I/O I/O I/O P I/O I/O I/O I/O I/O I/O I/O I/O I/O
</p><p>Revision1.0
</p><p>C10 B10 C9 A9 B9 C8 B8 J5 C7 E9 B7 E10 A7 D9 D8 E8 E7 E6 C6 B6 C5
4 K15 L10 L11 L12 L13 L14 L15 L16 L25 M10 M11
</p><p>GPIOY_3 GPIOY_4 GPIOY_5 GPIOY_6 GPIOY_7 GPIOY_8 GPIOY_9 VDD12_CPU GPIOY_1
0 GPIOY_11 GPIOY_12 GPIOY_13 GPIOY_14 GPIOY_15 GPIOY_16 GPIOY_17 GPIOY_18 GPIOY_
19 GPIOY_20 GPIOY_21 GPIOY_22 SSTL_VDD_RET GND GND GND GND GND GND GND GND GND G
ND GND GND GND GND GND GND GND GND GND
</p><p>GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY Power GPIOY GPIOY GPIOY GPIOY GPI
OY GPIOY GPIOY GPIOY GPIOY GPIOY GPIOY
</p><p>PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU PU
</p><p>1.2Vpower
</p><p>te
</p><p>Power
</p><p>
</p><p>General purpose input/output bank Y signal 10. Please refer to following Tabl
ctionalmultiplexinformation. General purpose input/output bank Y signal 11. Please r
put/output bank Y signal 13. Please refer to following Table6forfunctionalmultiplex
on. General purpose input/output bank Y signal 14. Please refer to following Table6
nalmultiplexinformation. General purpose input/output bank Y signal 15. Please refer
owing Table6forfunctionalmultiplexinformation. General purpose input/output bank Y s
output bank Y signal 17. Please refer to following Table6forfunctionalmultiplexinf
eneral purpose input/output bank Y signal 18. Please refer to following Table6forf
ltiplexinformation. General purpose input/output bank Y signal 19. Please refer to
g Table6forfunctionalmultiplexinformation. General purpose input/output bank Y signa
ease refer to following Table6forfunctionalmultiplexinformation. General purpose in
ut bank Y signal 21. Please refer to following Table6forfunctionalmultiplexinforma
al purpose input/output bank Y signal 22. Please refer to following Table6forfunct
lexinformation. DDR3SDRAMretentiondomainpowersupply
</p><p>ro m
</p><p>P
</p><p>to
</p><p>ib u
</p><p>
</p><p>
</p><p>tr
</p><p>D is
</p><p> 19/37
</p><p>as te r!
<br />P I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O P
</p><p>Generalpurposeinput/outputbankY signal3.PleaserefertofollowingTable6 forfunc
tiplexinformation. Generalpurposeinput/outputbankY signal4.PleaserefertofollowingT
nctionalmultiplexinformation. Generalpurposeinput/outputbankY signal5.Pleasereferto
able6 forfunctionalmultiplexinformation. Generalpurposeinput/outputbankY signal6.Ple
rtofollowingTable6 forfunctionalmultiplexinformation. Generalpurposeinput/outputbank
l7.PleaserefertofollowingTable6 forfunctionalmultiplexinformation. Generalpurposei
tbankY signal8.PleaserefertofollowingTable6 forfunctionalmultiplexinformation. Gen
nput/outputbankY signal9.PleaserefertofollowingTable6 forfunctionalmultiplexinforma
</p><p>I/O I/O I/O I/O I/O I/O I/O
</p><p>Revision1.0
</p><p>M12 M13 M14 M15 M16 N10 N11 N12 N13 N14 N15 N16 P10 P11 P12 P13 P14 P1
15 R16 T11 T12 T13 T14 T15
</p><p>GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND G
ND GND GND GND GND GND GND GND GND GND GND GND GND
</p><p>
</p><p>
</p><p>
</p><p>
</p><p> Abbreviations: I=Digitalinputpin O=Digitaloutputpin I/O=Digitalin
tpin AO=Analogoutputpin AIO=Analoginput/outputpin P=Powerpin AP=Anal
=Pulldown Z=TriState
</p><p>D is
</p><p>tr
</p><p>ib u
</p><p>te
</p><p>to
<br /> 20/37
</p><p>P
</p><p>ro m
</p><p>as te r!
</p><p>Revision1.0
</p><p>3.2PinMultiplexingTables
<br /> Multiple usage pins are used to converse pin consumption for different feat
8726M3 devices can be used in many different applications but each application wi
all the on chip features. As a result, some of the features sharethesamepin.
anbeusedasaGPIOpinalso.
</p><p>Table2.GPIOA_xandGPIOB_xMultiFunctionPin
<br />Pin# A5 B5 C4 B4 D4 A3 B3 A2 A1 B2 B1 C3 C1 C2 D3 D2 E3 E1 E2 F3 D5
J1 H4 J4 K6 K5 L6 L5 L4 M4 J2 K3 K2 L3 PinName GPIOA_0 GPIOA_1 GPIOA_2 GPIOA
6 GPIOA_7 GPIOA_8 GPIOA_9 GPIOA_10 GPIOA_11 GPIOA_12 GPIOA_13 GPIOA_14 GPIOA_15 GPIO
IOA_17 GPIOA_18 GPIOA_19 GPIOA_20 GPIOA_21 GPIOA_22 GPIOA_23 GPIOA_24 GPIOA_25 GPIOA_
IOA_27 GPIOB_0 GPIOB_1 GPIOB_2 GPIOB_3 GPIOB_4 GPIOB_5 GPIOB_6 GPIOB_7 GPIOB_8 GPIOB
B_10 GPIOB_11 GPIOB_12 GPIOB_13 GPIOB_14 GPIOB_15 GPIOB_16 GPIOB_17 GPIOB_18 GPIOB_19
put LCDin_R0 LCDin_R1 LCDin_R2 LCDin_R3 LCDin_R4 LCDin_R5 LCDin_R6 LCDin_R7 LCDin_G0
n_G1 LCDin_G2 LCDin_G3 LCDin_G4 LCDin_G5 LCDin_G6 LCDin_G7 LCDin_B0 LCDin_B1 LCDin_B2
n_B3 LCDin_B4 LCDin_B5 LCDin_B6 LCDin_B7 LCDin_CLK LCDin_HS LCDin_VS LCDin_DE LCD_R0
1 LCD_R2 LCD_R3 LCD_R4 LCD_R5 LCD_R6 LCD_R7 LCD_G0 LCD_G1 LCD_G2 LCD_G3 LCD_G4 LCD
CD_G7 LCD_B0 LCD_B1 LCD_B2 LCD_B3 FEC/ENC FEC_D0_A FEC_D1_A FEC_D2_A FEC_D3_A/ FEC_D0_
EC_D4_A/ FEC_CLK_C FEC_D5_A/ FEC_SOP_C FEC_D6_A/ FEC_D_VALID_C FEC_D7_A/ FEC_FAIL_C
FEC_CLK_A FEC_SOP_A FEC_D_VALID_A FEC_FAIL_A ENC_0 ENC_1 ENC_2 ENC_3 ENC_4 ENC_5 ENC
7 ENC_8 ENC_9 ENC_10 ENC_11 ENC_12 ENC_13 ENC_14 ENC_15 FEC_D0_B FEC_D1_B FEC_D2_B
EC_D4_B FEC_D5_B FEC_D6_B FEC_D7_B FEC_CLK_B FEC_SOP_B FEC_D_VALID_B FEC_FAIL_B FEC_FA
_OUT FEC_D_VALID_OUT FEC_SOP_OUT FEC_CLK_OUT FEC_D0_OUT FEC_D1_OUT FEC_D2_OUT FEC_D3_OU
T
</p><p>D is
</p><p>tr
</p><p>ib u
</p><p>te
</p><p>to
<br /> 21/37
</p><p>P
</p><p>ro m
</p><p>as te r!
</p><p>Revision1.0
</p><p>L1 L2 M3 M2
</p><p>GPIOB_20 GPIOB_21 GPIOB_22 GPIOB_23
</p><p>LCD_B4 LCD_B5 LCD_B6 LCD_B7
</p><p>FEC_D4_OUT FEC_D5_OUT FEC_D6_OUT FEC_D7_OUT
</p><p>
</p><p>Table3.GPIOC_xandGPIOD_xMultiFunctionpins
<br /> Pin# N3 N1 N2 P2 P3 R3 R4 R2 T3 T2 M5 N5 N6 P5 P4 R1 R5 T6 T5 W1
D_0 GPIOD_1 GPIOD_2 GPIOD_3 GPIOD_4 GPIOD_5 GPIOD_6 GPIOD_7 GPIOD_8 GPIOD_9 GPIOC_0
GPIOC_2 GPIOC_3 GPIOC_4 GPIOC_5 GPIOC_6 GPIOC_7 GPIOC_8 GPIOC_9 GPIOC_10 GPIOC_11 GP
GPIOC_13 GPIOC_15 LCD/LED LCD_VGHL_PWM LED_BL_PWM LCD_VGHL_PWM LED_BL_
ENC_17 TCON TCON_0_B(LCD)/TCON_STH1_B TCON_1_B/TCON_STV1_B TCON_2_B/TCON_
_CPV1_B TCON_4_B/TCON_OEV1_B TCON_5_B/TCON_CPH50_B/TCON_CPH1_B/ TCON_CPH2_B/TCON_CPH3_
CON_6_B/TCON_VCOM_B TCON_7_B TCON_0_A(mLVDS)/TCON_STH1 TCON_1_A/TCON_STV1 TCON_2_
H SPI/SPDIF HDMI CLK PCM/PWM PWM_C PWM_D VGA
</p><p>ro m
<br /> SPDIF_IN SPDIF_OUT HDMI_HPD(5V) HD
</p><p>P
</p><p>TCON_3_A/TCON_CPV1
</p><p>TCON_4_A/TCON_OEV1
</p><p>to
</p><p>TCON_5_A/TCON_CPH50/TCON_CPH1/TCON_CPH/ TCON_CPH3 TCON_6_A/TCON_VCOM
</p><p>te
</p><p>TCON_7_A
</p><p>
</p><p>ib u
</p><p>
</p><p>
</p><p>
</p><p>D is
</p><p>tr
</p><p>
</p><p>
</p><p> 22/37
</p><p>as te r!
<br /> CLK_OUT1(XTAL,RT
</p><p>Revision1.0
</p><p>Table4.GPIOAO_xMultiFunctionpins
<br /> Pin# U4 U6 Y2 W5 W3 U5 W2 Y5 Y3 V5 AA3 AA1 PinName GPIOAO_0 GPIOAO_1
_4 GPIOAO_5 GPIOAO_6 GPIOAO_7 GPIOAO_8 GPIOAO_9 GPIOAO_10 GPIOAO_11 UART UART_TX_AO
X_AO UART_CTS_AO UART_RTS_AO I2C/I2S I2C_SCK_AO/I2C_CLK_SLAVE_AO I
VE_AO I2C_SCK_AO/I2C_SCK_SLAVE_AO I2C_SDA_AO/I2C_SDA_SLAVE_AO JTAG JTAG_TDO
AG_TMS JTAG_TCK JTAG_TCK JTAG_TMS JTAG_TDI JTAG_TDO CLK Remote
</p><p>
</p><p>
</p><p>D is
</p><p>tr
</p><p>ib u
</p><p>te
</p><p>to
</p><p>P
</p><p> 23/37
</p><p>ro m
</p><p>as te r!
<br />CLK_OUT2(XTAL,RTC,PLL) CLK_OUT2(XTAL,RTC,PLL)
</p><p>REMOTE_INPUT
</p><p>Revision1.0
</p><p>Table5.GPIOX_xMultiFunctionpins
<br /> Pin# C19 D17 B19 C21 B18 PinName GPIOX_0 GPIOX_1 GPIOX_2 GPIOX_3 GPIOX_4
2C/I2S I2S_OUT_CH67 I2S_OUT_CH45 I2S_OUT_CH23 I2S_OUT_CH01 SD SDXC_D0_A/SD_D0_A
A/SD_D1_A SDXC_D2_A/SD_D2_A SDXC_D3_A/SD_D3_A SDXC_D4_A ISO7816 PCM/PWM
</p><p>C17
</p><p>GPIOX_5
</p><p>
</p><p>
</p><p>I2S_IN_CH01
</p><p>D18
</p><p>GPIOX_6
</p><p>
</p><p>
</p><p>I2S_LR_CLK
</p><p>SDXC_D6_A
</p><p>C16 B16 C15 A15 C18 E18 A17 E22 A19 E16 A25 D15 A11 E14 B21 F13 B20 D1
</p><p>GPIOX_8 GPIOX_9 GPIOX_10 GPIOX_11 GPIOX_12 GPIOX_13 GPIOX_14 GPIOX_15 GPIOX_16
OX_17 GPIOX_18 GPIOX_19 GPIOX_20 GPIOX_21 GPIOX_22 GPIOX_23 GPIOX_24
</p><p>
</p><p> UART_TX_A UART_RX_A UART_CTS_A UART_RTS_A UART_TX_B UART_RX_B
</p><p>
</p><p>ro m
</p><p>B17
</p><p>GPIOX_7
</p><p>
</p><p>
</p><p>I2S_AM_CLK
</p><p>SDXC_D7_A
</p><p>SDXC_CLK_A/SD_CLK_A
</p><p>as te r!
<br />SDXC_D5_A ISO7816_DET ISO7816_RESET ISO7816_CLK ISO7816_DATA
6_RESET ISO7816_CLK ISO7816_DATA
</p><p>PCM_IN
</p><p> PCM_FS
</p><p> PCM_CLK
</p><p>SDXC_CMD_A/SD_CMD_A SDXC_GPIO0_A SDXC_GPIO1_A SDXC_GPIO2_A
</p><p>to
<br /> I2S_AM_CLK I2S_AO_CLK I2S_LR_CLK
</p><p>P
<br />
</p><p>I2S_AO_CLK
</p><p>PCM_CLK PCM_FS PCM_IN
</p><p>UART_CTS_B
</p><p>ib u
<br />UART_TX_C UART_RX_C
</p><p>UART_RTS_B
</p><p>te
</p><p>I2S_IN_CH01/I2S_OUT_CH01 I2C_SDA_A I2C_SCK_A I2C_SDA_B I2C_SCK_B I2C_SCK_C
_SDA_C
</p><p>UART_CTS_C/UART_TX_B
</p><p>GPIOX_25 GPIOX_26
</p><p>C14 E17 C13
</p><p>B12 B13 C12 A13
</p><p>D is
<br /> GPIOX_27 GPIOX_28 GPIOX_29 GPIOX_30 GPIOX_31 GPIOX_32 GPIOX_33 GPIOX_34 GP
</p><p>tr
<br /> SPI_SS2 SPI_RDYn SPI_SS0 SPI_SS1 SPI_SCLK SPI_MOSI SPI_MISO
</p><p>UART_RTS_C/UART_RX_B
</p><p> 24/37
</p><p>Revision1.0
</p><p>Table6.GPIOY_xMultiFunctionpins
<br /> Pin# C11 B14 B11 C10 B10 C9 A9 B9 C8 B8 C7 E9 B7 E10 A7 D9 D8 E8 E7
_1 GPIOY_2 GPIOY_3 GPIOY_4 GPIOY_5 GPIOY_6 GPIOY_7 GPIOY_8 GPIOY_9 GPIOY_10 GPIOY_11
12 GPIOY_13 GPIOY_14 GPIOY_15 GPIOY_16 GPIOY_17 GPIOY_18 GPIOY_19 GPIOY_20 GPIOY_21
22 RMII RMII_CLK50_IN_OUT RMII_RX_ERR RMII_CRS_DV RMII_RX_DATA1 RMII_RX_DATA0 RMII_TX
N RMII_TX_DATA1 RMII_TX_DATA0 RMII_MDC RMII_MDIO ITU601
U601_VS ITU601_D0 CLK
</p><p>ro m
<br />ITU601_D1 ITU601_D2 ITU601_D3 ITU601_D4 ITU601_D5 ITU601_D6
</p><p>P to
<br />
</p><p>ITU601_D7 ITU601_CLK
</p><p>D is
</p><p>tr
</p><p>ib u
</p><p>te
</p><p>
</p><p>
</p><p> 25/37
</p><p>as te r!
<br /> CLK_OUT0(XTAL,RTC,PLL)
</p><p>Revision1.0
</p><p>Table7.CARD_xMultiFunctionPin
<br />Pin# G20 C24 F22 B24 E21 D21 D20 E20 E19 PinName CARD_0 CARD_1 CARD_2 CAR
ARD_6 CARD_7 CARD_8 SDXC SDXC_D0_B SDXC_D1_B SDXC_D2_B SDXC_D3_B SDXC_CLK_B SDXC_CMD
_B SDXC_GPIO0_B SDXC_GPIO1 SDXC_GPIO2 SDIO SD_D0_B SD_D1_B SD_D2_B SD_D3_B SD_CLK_B SD
_CMD_B
</p><p>Table8.BOOT_xMultiFunctionPin
<br />Pin# D24 D22 C25 F21 B25 F14 D14 A24 C23 A23 B23 C22 B22 B15 E12 E13 C2
_1 BOOT_2 BOOT_3 BOOT_4 BOOT_5 BOOT_6 BOOT_7 BOOT_8 BOOT_9 BOOT_10 BOOT_11 BOOT_12
OT_14 BOOT_15 BOOT_16 BOOT_17 NAND NAND_IO_0 NAND_IO_1 NAND_IO_2 NAND_IO_3 NAND_IO_4
IO_5 NAND_IO_6 NAND_IO_7 NAND_CE0boot NAND_CE1 NAND_CE2/NAND_RB0 NAND_CE3/NAND_BR1
LE NAND_CLE NAND_WEn_CLK NAND_REn_WR NAND_DQS SDXC SDXC_D0_C SDXC_D1_C SDXC_D2_C SDXC_
D3_C SDXC_D4_C SDXC_D5_C SDXC_D6_C SDXC_D7_C SDXC_CMD_C SDXC_CLK_C(bootable)
</p><p>SDIO SD_D0_C SD_D1_C SD_D2_C SD_D3_C SD_CMD_C SD_CLK_C
</p><p>ro m
</p><p>
</p><p>
</p><p>D is
</p><p>tr
</p><p>ib u
</p><p>te
</p><p>to
</p><p>
</p><p>P
</p><p> 26/37
</p><p>as te r!
<br />NOR_SPI SPI_NOR_D_A SPI_NOR_Q_A SPI_NOR_C_A SPI_NRO_CS_n_A
</p><p>
</p><p>Revision1.0
</p><p>4.SignalDescription
<br />Table9.LCD/LEDSignalDescription
<br />SignalName LCDin_R0 LCDin_R1 LCDin_R2 LCDin_R3 LCDin_R4 LCDin_R5 LCDin_R6 LCDin
CDin_G0 LCDin_G1 LCDin_G2 LCDin_G3 LCDin_G4 LCDin_G5 LCDin_G6 LCDin_G7 LCDin_B0 LCDin
CDin_B2 LCDin_B3 LCDin_B4 LCDin_B5 LCDin_B6 LCDin_B7 LCDin_CLK LCDin_HS LCDin_VS LCDi
LCD_R0 LCD_R1 LCD_R2 LCD_R3 LCD_R4 LCD_R5 LCD_R6 LCD_R7 Type I I I I I I I I I
cription Digitalvideoinputredbit0(LSB) Digitalvideoinputredbit1 Digitalvideoin
nputredbit3 Digitalvideoinputredbit4 Digitalvideoinputredbit6 Digitalvideoin
</p><p>Digitalvideoinputredbit7(MSB) Digitalvideoinputgreenbit1 Digitalvideoinp
deoinputgreenbit3 Digitalvideoinputgreenbit4 Digitalvideoinputgreenbit5
</p><p>Digitalvideoinputgreenbit0(LSB)
</p><p>to
<br />I I
</p><p>te
</p><p>I I O O O O O O O O O O O O O O O O O O O
</p><p>ib u
</p><p>tr
</p><p>D is
</p><p>LCD_G0 LCD_G1 LCD_G2 LCD_G3 LCD_G4 LCD_G5 LCD_G6 LCD_G7 LCD_B0 LCD_B1 LCD_B2
</p><p>P
<br /> 27/37
</p><p>ro m
<br />Digitalvideoinputbluebit1 Digitalvideoinputbluebit2 Digitalvideoinputblue
tbluebit4 Digitalvideoinputbluebit5 Digitalvideoinputbluebit6 Digitalvideoin
</p><p>Digitalvideoinputgreenbit6 Digitalvideoinputgreenbit7(MSB) Digitalvideoi
</p><p>Digitalvideoinputbluebit7(MSB) Digitalvideoinputhorizontalsync Digitalvide
ync Digitalvideoinputdataenable TTLLCDdataoutputredbit0(LSB) TTLLCDdataoutput
t2 TTLLCDdataoutputredbit3 TTLLCDdataoutputredbit4 TTLLCDdataoutputredbit
utredbit7(MSB) TTLLCDdataoutputgreenbit0(LSB) TTLLCDdataoutputgreenbit1 TT
tputgreenbit3 TTLLCDdataoutputgreenbit4 TTLLCDdataoutputgreenbit5 TTLLCDda
reenbit7(MSB) TTLLCDdataoutputbluebit0(LSB) TTLLCDdataoutputbluebit1 TTLLC
</p><p>as te r!
</p><p>Revision1.0
</p><p>SignalName LCD_B3 LCD_B4 LCD_B5 LCD_B6 LCD_B7 LCD_VGHL_PWM LED_BL_PWM
</p><p>Type O O O O O O O TTLLCDdataoutputbluebit3 TTLLCDdataoutputbluebit
aoutputbluebit6
</p><p>Description
</p><p>TTLLCDdataoutputbluebit7(MSB) LCDpanelVGHLtuningpulsewidthmodulationsign
ghttuningpulsewidthmodulationsignaloutput
</p><p><b>Table10.FEC/ENCInterfaceSignalDescription
</b><br />SignalName FEC_D0_A FEC_D1_A FEC_D2_A FEC_D3_A/ FEC_D0_C FEC_D4_A/ FEC_CLK_C
FEC_D5_A/ FEC_SOP_C FEC_D6_A/ FEC_D_VALID_C FEC_D7_A/ FEC_FAIL_C FEC_CLK_A FEC_SOP_A
FEC_D_VALID_A FEC_FAIL_A FEC_D0_B FEC_D1_B FEC_D2_B FEC_D3_B FEC_D4_B FEC_D5_B FEC_D6_
EC_D7_B Type I I I I I I I I I I I I I I I I I I I I I I I I O O O O
abusbit0(LSB) TSinputportAdatabusbit1 TSinputportAdatabusbit2
</p><p>to te
</p><p>ib u
</p><p>FEC_CLK_B
</p><p>FEC_SOP_B
</p><p>FEC_D_VALID_B FEC_FAIL_B FEC_D0_OUT FEC_D1_OUT FEC_D2_OUT FEC_D3_OUT FEC_D4_OUT
FEC_D5_OUT FEC_D6_OUT FEC_D7_OUT FEC_FAIL_OUT
</p><p>tr
</p><p>D is
</p><p>FEC_D_VALID_OUT FEC_SOP_OUT FEC_CLK_OUT ENC_0
</p><p>P
<br />TBD
</p><p> 28/37
</p><p>ro m
<br />TSinputportAclock TSinputportBclock TSoutputdatabusbit1 TSoutputdatab
tdatabusbit4 TSoutputdatabusbit5 TSoutputdatabusbit6 TSoutputdatafailures
putclock
</p><p>TSinputportAdatabusbit3 SerialTSinputdata TSinputportAdatabusbit4 S
usbit5 SerialTSstartofstreamsignal TSinputportAdatabusbit6 SerialTSdataval
</p><p>TSinputportAdatabusbit7(MSB) SerialTSdatafailuresignal TSinputportAst
</p><p>TSinputportAdatevalidsignal TSinputportBdatabusbit0(LSB) TSinputport
TSinputportBdatabusbit3 TSinputportBdatabusbit4 TSinputportBdatabusbit5
MSB) TSinputportBstartofstreamsignal TSinputportBdatevalidsignal
</p><p>TSinputportAdatafailuresignal
</p><p>TSinputportBdatafailuresignal TSoutputdatabusbit0(LSB)
</p><p>TSoutputdatabusbit7(MSB)
</p><p>TSoutputstartofstreamsignal
</p><p>as te r!
</p><p>Revision1.0
</p><p>SignalName ENC_1 ENC_2 ENC_3 ENC_4 ENC_5 ENC_6 ENC_7 ENC_8 ENC_9 ENC_10 ENC
NC_13 ENC_14 ENC_15 ENC_16 ENC_17
</p><p>Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
</p><p>Description TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
</p><p>
</p><p>
</p><p>D is
</p><p>tr
</p><p>ib u
</p><p>te
</p><p>to
<br /> 29/37
</p><p>P
</p><p>ro m
</p><p>as te r!
</p><p>Revision1.0
</p><p>Table11.TCONInterfaceSignalDescription
<br />SignalName TCON_0_B/TCON_STH1_B TCON_1_B/TCON_STV1_B TCON_2_B/TCON_OEH_B TCON_3
N_CPV1_B TCON_4_B/TCON_OEV1_B TCON_5_B/TCON_CPH50_B/TCON_CPH1_B/TCON_CPH2_B/TCON_CPH3_
CON_6_B/TCON_VCOM_B TCON_7_B TCON_0_A/TCON_STH1 TCON_1_A/TCON_STV1 TCON_2_A/TCON_OEH
_A/TCON_CPV1 TCON_4_A/TCON_OEV1 TCON_5_A/TCON_CPH50/TCON_CPH1/TCON_CPH/TCON_CPH3 TCON
/TCON_VCOM TCON_7_A SignalName SPDIF_IN SPDIF_OUT Type O O O O O O O O O O
leTCONportBsignal0forTTLLCD st TCON1 sourcedriverstartpulseforTTLLCD Program
st TCON1 gatedriverstartpulseforTTLLCD ProgrammableTCONportBsignal2forTTLLCD
ourcedriverforTTLLCD ProgrammableTCONportBsignal3forTTLLCD st TCON1 gatedrive
</p><p>ProgrammableTCONportBsignal5forTTLLCD TCONsourcedrivershiftclockoutputfo
eTCONportBsignal6forTTLLCD TCONPOLdrivingsignalforTTLLCD ProgrammableTCONpor
</p><p>ProgrammableTCONportAsignal0forLVDSandminiLVDS ProgrammableTCONportAsig
</p><p>P
<br />O O O
</p><p>to
<br />Type I O Type O I O O O O I
</p><p>te
</p><p>Table12.SPDIFInterfaceSignalDescription
<br />Description SPDIFinputsignal SPDIFoutputsignal
</p><p>
</p><p>ib u
</p><p>Table13.SPIIOInterfaceSignalDescription
<br />Description SPIslaveselect2 SPIReadysignal,lowactive SPIslaveselect0 SPIs
lClock SPIMasterOutput,SlaveInput SPIMasterInput,SlaveOutput
</p><p>D is
</p><p>
</p><p>
</p><p>tr
</p><p>SignalName SPI_SS2 SPI_RDYn SPI_SS0 SPI_SS1 SPI_SCLK SPI_MOSI SPI_MISO
</p><p>
</p><p> 30/37
</p><p>ro m
<br />O O
</p><p>ProgrammableTCONportAsignal2forMINILVDS ProgrammableTCONportAsignal3for
bleTCONportAsignal4forMINILVDS
</p><p>ProgrammableTCONportAsignal5forMINILVDS ProgrammableTCONportAsignal6for
bleTCONportAsignal7forMINILVDS
</p><p>as te r!
</p><p>ProgrammableTCONportBsignal4forTTLLCD st TCONoutputenablesignalfor1 gate
</p><p>Revision1.0
</p><p>Table14.UARTInterfaceSignalDescription
<br />SignalName UART_TX_AO UART_RX_AO UART_CTS_AO UART_RTS_AO UART_TX_A UART_RX_A UAR
CTS_A UART_RTS_A UART_TX_B UART_RX_B UART_CTS_B UART_RTS_B UART_TX_C UART_RX_C UART_CT
C/UART_TX_B UART_RTS_C/ UART_RX_B Type O I I O O I I O O I I O O I I O UA
t UARTPortAOClearToSendSignal UARTPortAOReadyToSendSignal UARTPortAdataoutp
earToSendSignal UARTPortBdataoutput UARTPortBdatainput UARTPortAReadyToSend
</p><p>UARTPortBClearToSendSignal UARTPortCdataoutput UARTPortCdatainput
</p><p>UARTPortBReadyToSendSignal
</p><p>
<br />SignalName I2S_OUT_CH67 I2S_OUT_CH45 I2S_OUT_CH23 I2S_OUT_CH01 I2S_IN_CH01 I2S_LR
_CLK I2S_AM_CLK I2S_AO_CLK Type O O O O I
</p><p>Table15.I2SInterfaceSignalDescription
</p><p>to
<br />O O
</p><p>
</p><p>SignalName I2C_SCK_AO/I2C_SCK_SLAVE_AO I2C_SDA_A I2C_SCK_A I2C_SCK_B I2C_SCK_C
C_SDA_C I2C_SDA_B
</p><p>ib u
</p><p>te
</p><p>O/I
</p><p>Table16.I2CInterfaceSignalDescription
<br />Type I/O I/O I/O I/O I/O I/O I/O I/O Description AlwaysonI2Cserialclocklin
dpullhigh AlwaysonI2Cserialdataline,MasterorSlave,needpullhigh I2CbusportAd
e,needpullhigh I2CbusportAclockinput/output,MasterorSlave,needpullhigh I2Cbus
terorSlave,needpullhigh I2CbusportBclockinput/output,MasterorSlave,needpullhi
utput,MasterorSlave,needpullhigh I2CbusportCclockinput/output,MasterorSlave,ne
</p><p>I2C_SDA_AO/I2C_SDA_SLAVE_AO
</p><p>D is
</p><p>
</p><p>tr
</p><p>
</p><p>P
<br /> 31/37
</p><p>ro m
<br />I2SLeft/RightClockOut I2Smasterclockoutput I2Sdataclockinput/output
</p><p>UARTPortCClearToSendSignal UARTPortBdataoutput UARTPortCClearToSendSi
</p><p>Description I2SAudioDataOutputchannel6and7 I2SAudioDataOutputchannel4and
annel2and3 I2SAudioDataOutputchannel0and1
</p><p>I2SAudioDataInputchannel0and1
</p><p>as te r!
</p><p>Revision1.0
</p><p>Table17.HDMIInterfaceSignalDescription
<br />SignalName HDMI_HPD(5V) HDMI_SDA(5V) HDMI_SCL(5V) HDMI_CEC Type I/O I/O I/O
tion HDMIhotplugindetectionsignalinput HDMII2Ccontrolinterfacedatasignal,needpu
linterfaceclocksignal,needpullhigh HDMICEC(Consumerelectronicscontrol)
</p><p>
</p><p>Table18.SDInterfaceSignalDescription
<br />SDXC_D1_A/SD_D1_A SDXC_D2_A/SD_D2_A SDXC_D3_A/SD_D3_A SDXC_D4_A SDXC_D5_A SDXC_
SDXC_D7_A SDXC_CLK_A/SD_CLK_A SDXC_CMD_A/SD_CMD_A SDXC_GPIO0_A SDXC_GPIO1_A SDXC_GPIO2
I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O SDXC/SDIOPortAdatabusbit1sign
al SDXCPortAdatabusbit4signal SDXCPortAdatabusbit5signal SDXCPortAdatabus
XC/SDIOPortAclocksignal SDXCPortAGPIObit0signal SDXCPortAGPIObit1signal SDX
</p><p>SDXC/SDIOPortAdatabusbit3signal
</p><p>
<br />SignalName ISO7816_DET ISO7816_RESET ISO7816_CLK ISO7816_DATA Type I O O
</p><p>to
<br />I/O
</p><p>ib u
</p><p>SignalName RMII_CLK50_IN_OUT RMII_RX_ERR RMII_CRS_DV
</p><p>te
</p><p>
</p><p>Table20.RMIIInterfaceSignalDescription
<br />Type I/O I I I I O O O O I/O Description EthernetRMIIinterfaceMasterClock
) EthernetRMIIinterfaceReceiveError EthernetRMIIinterfaceCarrierSense/ReceiveDataV
thernetRMIIinterfaceReceiveData1 EthernetRMIIinterfaceReceiveData0 EthernetRMIII
tEnable EthernetRMIIinterfaceTransmitData1 EthernetRMIIinterfaceTransmitData0 Et
aceManagementDataClock EthernetRMIIinterfaceManagementDatainput/output
</p><p>RMII_RX_DATA1 RMII_RX_DATA0 RMII_TX_EN RMII_TX_DATA1 RMII_TX_DATA0 RMII_MDC RMI
I_MDIO
</p><p>D is
</p><p>
</p><p>
</p><p>tr
</p><p>
</p><p>P
<br /> 32/37
</p><p>Table19.ISO7816InterfaceSignalDescription
<br />Description ISO7816detectsignal ISO7816resetsignal ISO7816clocksignal ISO78
nal
</p><p>ro m
</p><p>SDXC/SDIOPortAcommandsignal
</p><p>as te r!
</p><p>SignalName SDXC_D0_A/SD_D0_A
</p><p>Type I/O
</p><p>Description SDXC/SDIOPortAdatabusbit0signal
</p><p>Revision1.0
</p><p>Table21.ITU601InterfaceSignalDescription
<br />SignalName ITU601_FIR/ ITU601_IDQ ITU601_HS ITU601_VS ITU601_D0 ITU601_D1 ITU601
2 ITU601_D3 ITU601_D4 ITU601_D5 ITU601_D6 ITU601_D7 ITU601_CLK Type I I I I I I I I I
I I/O Description ITU601VideoInputFieldSignal ITU601VideoInputHorizontalSyncSigna
utVerticalSyncSignal ITU601VideoInputDataBusbit0(LSB) ITU601VideoInputDataBu
t2 ITU601VideoInputDataBusbit3 ITU601VideoInputDataBusbit5 ITU601VideoInp
ock ITU601VideoInputDataBusbit4
</p><p>ITU601VideoInputDataBusbit7(MSB)
</p><p>
<br />SignalName JTAG_TDO JTAG_TDI JTAG_TMS JTAG_TCK Type O I I I JTAGScandatainp
</p><p>Table22.JTAGInterfaceSignalDescription
<br />JTAGScandataoutput
</p><p>
<br />SignalName CLK_OUT2(XTAL,RTC,PLL) CLK_OUT1(XTAL,RTC,PLL) CLK_OUT0(XTAL,RTC,P
O O
</p><p>Table23.CLKInterfaceSignalDescription
</p><p>to
<br />Type I Type O O O O
</p><p>
<br />SignalName REMOTE_INPUT
</p><p>Table24.RemoteInterfaceSignalDescription
<br />
<br />SignalName PWM_A PWM_B PWM_C
</p><p>ib u
</p><p>te
</p><p>Table25.PWMInterfaceSignalDescription
<br />Description PWMchannelAoutputsignal PWMchannelBoutputsignal PWMchannelCout
nelDoutputsignal
</p><p>
</p><p>D is
</p><p>
</p><p>tr
</p><p>PWM_D
</p><p>
</p><p>P
<br /> 33/37
</p><p>ro m
<br />JTAGTestmodeselectinput JTAGTestclockinput Description XTAL,RTCCLK,PLLcloc
K,PLLclockoutput1 XTAL,RTCCLK,PLLclockoutput0 Description IRRemotecontrollerin
</p><p>as te r!
<br />Description
</p><p>Revision1.0
</p><p>Table26.PCMInterfaceSignalDescription
<br />SignalName PCM_OUT PCM_IN PCM_FS PCM_CLK Type O I O O PCMoutputdatastream
m PCMframesynchronization PCMmasterclockinput Description
</p><p>
</p><p>Table27.VGAInterfaceSignalDescription
<br />O O VGA_VS VGAoutputverticalsyncsignal
</p><p>
</p><p>D is
</p><p>tr
</p><p>ib u
</p><p>te
</p><p>to
<br /> 34/37
</p><p>P
</p><p>ro m
</p><p>as te r!
</p><p>SignalName VGA_HS
</p><p>Type
</p><p>Description VGAoutputhorizontalsyncsignal
</p><p>Revision1.0
</p><p>4. OperatingConditions
<br />AbsoluteMaximumRatings
<br />Thetablebelowgivestheabsolutemaximumratings.Exposuretostressesbeyondthosel
yresultin permanentdevicedamage,unreliabilityorboth. Characteristic Value Unit 1.2
yVoltage 1.4 V 1.5VSupplyVoltage 1.65 V 2.5VSupplyVoltage 2.75 V 3.3VSupplyVoltag
oltage,VI 0.5~VDD+0.3 V JunctionTemperature TBD C
</p><p>RecommendedOperatingConditions
<br />Symbol VDD(CORE) 1.2VCoreSupplyVoltage VDD(SSTL) 1.5VSSTLSupplyVoltage VDD(AV
DDSupplyVoltage VDD(IO) 3.3VIOSupplyVoltage TJ JunctionTemperature Parameter
</p><p>DCCharacteristics
<br />VDD=3.3+/0.3V,TA=0to75C Symbol Parameters VIH HighLevelInput VIL Low
ositivegoingThreshold VT Schmitttrigger,negativegoingthreshold Vol Lowleveloutput
</p><p>to
</p><p>P
</p><p>ro m
<br />Condition Ioh=2.0mA Iol=2.0mA 35/37
</p><p>ib u
</p><p>Voh
</p><p>Highleveloutputvoltage
</p><p>te
</p><p>D is
</p><p>tr
</p><p>as te r!
<br />Min. 1.14 1.35 2.38 3.14 0 Typ. 1.2 1.5 2.5 3.3 Max 1.32 1.65 2.75 3.63 125
V V C Min Typ 2.0 0.3 1.5 0.93 2.4 Max 3.3 0.8 0.4 Unit V V V V
</p><p>Revision1.0
</p><p>5. MechanicalDimensions
<br />The AML8726M3 processor comes in a 445 balls LFBGA RoHS package. The mecha
s are given in millimeters asbelow:
</p><p>ro m
</p><p>
</p><p>D is
</p><p>tr
</p><p>ib u
</p><p>te
</p><p>to
</p><p>P
</p><p>
</p><p>
</p><p> 36/37
</p><p>as te r!
<br /> AMLOGIC,Inc.Proprietary
</p><p>Revision1.0
</p><p>P D is tr ib u te to
<br /> 37/37
</p><p>ro m
<br /> AMLOGIC,Inc.Proprietary
</p><p>as te r!
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iv></div><script type="text/javascript">Scribd.Lightbox.initialize();</script><d
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new Scribd.SignIn("#autogen_id_580976231");
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new Scribd.Header("#global_header");

Scribd.BookPreview.bind_links();

new Scribd.LanguageSelector("#autogen_id_580979685");
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var el = document.getElementById("document_column");
if (el) {
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var infolinks_plugins = "ratio";
var infolinks_ratio = 100;
writeScript("http://resources.infolinks.com/js/infolinks_main.js");
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<script async src="http://i.simpli.fi/dpx.js?cid=4939&m=1"></script>


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</div>
<div class="autogen_class_views_shared_document_popups_document" id="autogen_id_
580985485"><script id="tpl_document_popup" type="template"><div class="document_
popup object_popup" data-object_id="{{ id }}"><div class="popup_arrow"></div><p
class="recommendation_explanation"></p><div class="title_row"><a data-track="{{
list_title }}" data-track_event="click_popup_title_link" data-track_rats="click_
popup" data-track_rats_value="{"event_name":"click_popup",&q
uot;context":"{{ context }}","action":"title_link&
quot;,"list":"{{ list_title }}","list_index":&quot
;{{ list_index }}","position":"{{ position }}","do
c_id":"{{ id }}","source":"{{ source }}",&quo
t;source_ids":"{{ source_ids }}"}" data-track_value="{{ position
}}" href="{{ url }}">{{ title }}</a></div> {[ if (typeof authors !== undefine
d && authors.length) { ]}
<div class='creator_row creator_row_authors'>
by
<a class='author' href='{{authors[0].url}}'>
{{authors[0].name}}
</a>
{[ for(var i=1;i < authors.length;i++){ ]}
,
<a class='author' href='{{authors[i].url}}'>
{{authors[i].name}}
</a>
{[ } ]}
</div>
{[ } else { ]}
<div class='creator_row creator_row_publisher'>
<a data-track='{{ list_title }}' data-track_event='click_popup_author_li
nk' data-track_value='{{ position }}' data-track_rats='click_popup' data-track_r
ats_value='{"event_name":"click_popup","context":"{{ context }}","action":"autho
r_link","list":"{{ list_title }}","list_index":"{{ list_index }}","position":"{{
position }}","doc_id":"{{ id }}","source":"{{ source }}","source_ids":"{{ sourc
e_ids }}"}' href='{{publisher.url}}'>
{{publisher.name}}
</a>
</div>
{[ } ]}
<span class="star_ratings_row"> <span class="stars"></span><span class="value">
(<span class="rating_number">{{ _.numberFormat(stats.ratings_count) }} Ratings</
span><span class="on_rating">Your rating</span>)</span></span><div class="page_c
ount">{{ page_count }}</div><div class="document_description"><p class="descript
ion">{{ description }}</p></div><span class="view_restriction_msg"></span><div c
lass="recommendation_not_interested "><a class="not_interested_btn" href="#" tit
le="Remove this document from my recommendations">Not interested</a></div><div c
lass="primary_action">{[ if (typeof download_url !== undefined && download_url)
{ ]}<a class="download_btn flat_btn" href="#">Download</a>{[ } else if (typeof s
how_read_now !== undefined && show_read_now) { ]}<a class="read_now_btn flat_btn
" data-track="{{ list_title }}" data-track_event="click_popup_read_now_btn" data
-track_rats="click_popup" data-track_rats_value="{"event_name":"c
lick_popup","context":"{{ context }}","action&quot
;:"read_now_btn","list":"{{ list_title }}","l
ist_index":"{{ list_index }}","position":"{{ posit
ion }}","doc_id":"{{ id }}","source":"{{
source }}","source_ids":"{{ source_ids }}"}" data-trac
k_value="{{ position }}" href="{{ url }}">{[ if (typeof read_full !== undefined
&& read_full) { ]}<span class="read_now_label">Read now</span>{[ } else { ]}<spa
n class="read_excerpt_label">Read excerpt</span>{[ } ]}</a>{[ } ]}</div>{[ if (t
ypeof user_can_save_bookmarks !== undefined && user_can_save_bookmarks) { ]}<div
class="document_sub_action"><span class="save_bookmark_btn" data-track="{{ list
_title }}" data-track_event="click_popup_save_bookmark_btn" data-track_rats="cli
ck_popup" data-track_rats_value="{"event_name":"click_popup"
,"context":"{{ context }}","action":"save_boo
kmark_btn","list":"{{ list_title }}","list_index&q
uot;:"{{ list_index }}","position":"{{ position }}&quot
;,"doc_id":"{{ id }}","source":"{{ source }}&
quot;,"source_ids":"{{ source_ids }}"}" data-track_value="{{
position }}"><a class="save">Save for later</a><a class="unsave">Saved!</a></sp
an></div>{[ } ]}</div></script></div><div class="autogen_class_views_shared_docu
ment_popups_collection" id="autogen_id_580986405"><script id="tpl_collection_pop
up" type="template"><div class="collection_popup object_popup" data-object_id="{
{ id }}"><div class="popup_arrow"></div><div class="content"><div class="title_r
ow"><a data-track="{{ list_title }}" data-track_event="click_popup_title_link" d
ata-track_rats="click_popup" data-track_rats_value="{"event_name":&quo
t;click_popup","context":"{{ context }}","action&q
uot;:"title_link","list":"{{ list_title }}","
list_index":"{{ list_index }}","position":"{{ posi
tion }}","doc_id":"{{ id }}","source":"{
{ source }}","source_ids":"{{ source_ids }}"}" data-tra
ck_value="{{ position }}" href="{{ url }}">{{ title }}</a></div><div class="subt
itle_row">Collection</div><div class="document_list"></div><div class="remaining
_docs"><a href="{{ url }}">+{{ remaining_docs }} more</a></div><div class="prima
ry_action"><a class="flat_btn" data-track="{{ list_title }}" data-track_event="c
lick_popup_view_collection_btn" data-track_rats="click_popup" data-track_rats_va
lue="{"event_name":"click_popup","context":"{
{ context }}","action":"view_collection_btn","list
":"{{ list_title }}","list_index":"{{ list_index }
}","position":"{{ position }}","doc_id":&quot
;{{ id }}","source":"{{ source }}","source_ids&quo
t;:"{{ source_ids }}"}" data-track_value="{{ position }}" href="{{ url
}}"><span>View Collection</span></a></div></div></div></script><script id="tpl_
popup_document_row" type="template"><div class="document_row">{{ index }}. <a hr
ef="{{ url }}">{{ title }}</a></div></script></div><div class="autogen_class_vie
ws_shared_document_popups_onboarding_book autogen_class_views_shared_document_po
pups_document" id="autogen_id_580987737"><script id="tpl_onboarding_book_popup"
type="template"><div class="onboarding_book_popup object_popup" data-object_id="
{{ id }}"><div class="popup_arrow"></div> {[ if (typeof authors !== undefined
&& authors.length) { ]}
<div class='creator_row creator_row_authors'>
<span class='author' href='{{authors[0].url}}' data-track='title_link' >
{{authors[0].name}}
</span>
{[ for(var i=1;i < authors.length;i++){ ]}
,
<span class='author' href='{{authors[i].url}}' data-track='title_link'
>
{{authors[i].name}}
</span>
{[ } ]}
</div>
{[ } ]}
<div class='creator_row creator_row_publisher'>
<span href='{{publisher.url}}'>
{{publisher.name}}
</span>
</div>
<div class="title_row"><div>{{ title }}</div></div><div class="document_descript
ion"><p class="description">{{ description }}</p></div></div></script></div></bo
dy></html>

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