00 Cover & Contents

AM335x ARM Cortex-A8 Microprocessors
(MPUs)
Technical Reference Manual
Literature Number: SPRUH73E

October 2011 Revised May 2012
Contents
....................................................................................................................................
Introduction ....................................................................................................................
1.1
AM335x Family ...........................................................................................................
1.1.1 Device Features .................................................................................................
1.1.2 Device Identification ............................................................................................
1.1.3 Feature Identification ...........................................................................................
Memory Map ...................................................................................................................
2.1
ARM Cortex-A8 Memory Map ..........................................................................................
2.2
ARM Cortex-M3 Memory Map .........................................................................................
ARM MPU Subsystem .......................................................................................................
3.1
ARM Cortex-A8 MPU Subsystem ......................................................................................
3.1.1 Features ..........................................................................................................
3.1.2 MPU Subsystem Integration ...................................................................................
3.1.3 MPU Subsystem Clock and Reset Distribution .............................................................
3.1.4 ARM Subchip ....................................................................................................
3.1.5 Interrupt Controller ..............................................................................................
3.1.6 Power Management ............................................................................................
3.1.7 ARM Programming Model .....................................................................................
Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS) .............
4.1
Introduction ...............................................................................................................
Graphics Accelerator (SGX) ..............................................................................................
5.1
Introduction ...............................................................................................................
5.1.1 POWERVR SGX Main Features ..............................................................................
5.1.2 SGX 3D Features ...............................................................................................
5.1.3 Universal Scalable Shader Engine (USSE) Key Features ..............................................
5.1.4 Unsupported Features ..........................................................................................
5.2
Integration .................................................................................................................
5.2.1 SGX530 Connectivity Attributes ...............................................................................
5.2.2 SGX530 Clock and Reset Management .....................................................................
5.2.3 SGX530 Pin List .................................................................................................
5.3
Functional Description ...................................................................................................
5.3.1 SGX Block Diagram ............................................................................................
5.3.2 SGX Elements Description ....................................................................................
Interrupts ........................................................................................................................
6.1
Functional Description ...................................................................................................
6.1.1 Interrupt Processing ............................................................................................
6.1.2 Register Protection .............................................................................................
6.1.3 Module Power Saving ..........................................................................................
6.1.4 Error Handling ...................................................................................................
6.1.5 Interrupt Handling ...............................................................................................
6.1.6 Basic Programming Model .....................................................................................
6.2
ARM Cortex-A8 Interrupts ..............................................................................................
6.3
ARM Cortex-M3 Interrupts ..............................................................................................
6.4
PWM Events ..............................................................................................................
Preface
153
154
4
5
Contents
154
154
155
156
158
158
167
169
170
171
171
172
175
176
176
179
181
182
183
184
184
184
185
186
187
187
187
188
189
189
189
191
192
193
194
194
194
194
195
204
208
210
SPRUH73E October 2011 Revised May 2012

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Copyright 20112012, Texas Instruments Incorporated
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6.5
Memory Subsystem
7.1
7.2
7.3
7.4
Interrupt Controller Registers ........................................................................................... 211

6.5.1 INTC Registers .................................................................................................. 211
......................................................................................................... 386
GPMC .....................................................................................................................
7.1.1 Introduction ......................................................................................................
7.1.2 Integration ........................................................................................................
7.1.3 Functional Description ..........................................................................................
7.1.4 Use Cases .......................................................................................................
7.1.5 Registers .........................................................................................................
OCMC-RAM ..............................................................................................................
7.2.1 Introduction ......................................................................................................
7.2.2 Integration ........................................................................................................
EMIF .......................................................................................................................
7.3.1 Introduction ......................................................................................................
7.3.2 Integration ........................................................................................................
7.3.4 Use Cases .......................................................................................................
7.3.5 EMIF4D Registers ..............................................................................................
7.3.6 DDR2/3/mDDR PHY Registers ...............................................................................
ELM ........................................................................................................................
7.4.1 Introduction ......................................................................................................
7.4.2 Integration ........................................................................................................
7.4.4 Basic Programming Model .....................................................................................
7.4.5 ELM Registers ...................................................................................................
387
387
390
392
491
502
535
535
536
537
537
539
541
559
559
600
609
609
610
611
614
620
.................................................................... 632
8.1
Power, Reset, and Clock Management ............................................................................... 633
8.1.1 Introduction ...................................................................................................... 633
8.1.2 Device Power-Management Architecture Building Blocks ................................................. 633
8.1.3 Clock Management ............................................................................................. 633
8.1.4 Power Management ............................................................................................ 639
8.1.5 PRCM Module Overview ....................................................................................... 647
8.1.6 Clock Generation and Management .......................................................................... 648
8.1.7 Reset Management ............................................................................................. 664
8.1.8 Power-Up/Down Sequence .................................................................................... 673
8.1.9 IO State ........................................................................................................... 673
8.1.10 Voltage and Power Domains ................................................................................. 673
8.1.11 Device Modules and Power Management Attributes List ................................................. 674
8.1.12 Clock Module Registers ....................................................................................... 677
8.1.13 Power Management Registers ............................................................................... 834
Control Module ................................................................................................................ 875
9.1
Introduction ............................................................................................................... 876
9.2
Functional Description ................................................................................................... 876
9.2.1 Control Module Initialization ................................................................................... 876
9.2.2 Pad Control Registers .......................................................................................... 876
9.2.3 EDMA Event Multiplexing ...................................................................................... 877
9.2.4 Device Control and Status ..................................................................................... 878
9.2.5 DDR PHY ........................................................................................................ 884
9.3
CONTROL_MODULE Registers ....................................................................................... 885
9.3.1 control_revision Register (offset = 0h) [reset = 0h] ......................................................... 892
9.3.2 device_id Register (offset = 600h) [reset = 0x] ............................................................. 893
9.3.3 control_hwinfo Register (offset = 4h) [reset = 0h] .......................................................... 894
9.3.4 control_sysconfig Register (offset = 10h) [reset = 0h] ..................................................... 895
Power, Reset, and Clock Management (PRCM)

Contents
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9.3.5
9.3.6
9.3.7
9.3.8
9.3.9
9.3.10
9.3.11
9.3.12
9.3.13
9.3.14
9.3.15
9.3.16
9.3.17
9.3.18
9.3.19
9.3.20
9.3.21
9.3.22
9.3.23
9.3.24
9.3.25
9.3.26
9.3.27
9.3.28
9.3.29
9.3.30
9.3.31
9.3.32
9.3.33
9.3.34
9.3.35
9.3.36
9.3.37
9.3.38
9.3.39
9.3.40
9.3.41
9.3.42
9.3.43
9.3.44
9.3.45
9.3.46
9.3.47
9.3.48
9.3.49
9.3.50
9.3.51
9.3.52
9.3.53
9.3.54
9.3.55
9.3.56
9.3.57
4
Contents
control_status Register (offset = 40h) [reset = 0h] .........................................................

cortex_vbbldo_ctrl Register (offset = 41Ch) [reset = 0h] ..................................................
core_sldo_ctrl Register (offset = 428h) [reset = 0h] ........................................................
mpu_sldo_ctrl Register (offset = 42Ch) [reset = 0h] .......................................................
clk32kdivratio_ctrl Register (offset = 444h) [reset = 0h] ...................................................
bandgap_ctrl Register (offset = 448h) [reset = 0h] ........................................................
bandgap_trim Register (offset = 44Ch) [reset = 0h] .......................................................
pll_clkinpulow_ctrl Register (offset = 458h) [reset = 0h] ..................................................
mosc_ctrl Register (offset = 468h) [reset = 0h] ............................................................
rcosc_ctrl Register (offset = 46Ch) [reset = 0h] ............................................................
deepsleep_ctrl Register (offset = 470h) [reset = 0h] ......................................................
dev_feature Register (offset = 604h) [reset = 0h] .........................................................
init_priority_0 Register (offset = 608h) [reset = 0h] ........................................................
init_priority_1 Register (offset = 60Ch) [reset = 0h] .......................................................
mmu_cfg Register (offset = 610h) [reset = 0h] .............................................................
tptc_cfg Register (offset = 614h) [reset = 0h] ..............................................................
usb_ctrl0 Register (offset = 620h) [reset = 0h] .............................................................
usb_sts0 Register (offset = 624h) [reset = 0h] .............................................................
usb_ctrl1 Register (offset = 628h) [reset = 0h] .............................................................
usb_sts1 Register (offset = 62Ch) [reset = 0h] ............................................................
mac_id0_lo Register (offset = 630h) [reset = 0h] ..........................................................
mac_id0_hi Register (offset = 634h) [reset = 0h] ..........................................................
mac_id1_lo Register (offset = 638h) [reset = 0h] ..........................................................
mac_id1_hi Register (offset = 63Ch) [reset = 0h] .........................................................
dcan_raminit Register (offset = 644h) [reset = 0h] ........................................................
usb_wkup_ctrl Register (offset = 648h) [reset = 0h] ......................................................
gmii_sel Register (offset = 650h) [reset = 0h] ..............................................................
pwmss_ctrl Register (offset = 664h) [reset = 0h] ..........................................................
mreqprio_0 Register (offset = 670h) [reset = 0h] ..........................................................
mreqprio_1 Register (offset = 674h) [reset = 0h] ..........................................................
hw_event_sel_grp1 Register (offset = 690h) [reset = 0h] ................................................
hw_event_sel_grp4 Register (offset = 69Ch) [reset = 0h] ................................................
smrt_ctrl Register (offset = 6A0h) [reset = 0h] .............................................................
mpuss_hw_debug_sel Register (offset = 6A4h) [reset = 0h] ............................................
mpuss_hw_dbg_info Register (offset = 6A8h) [reset = 0h] ...............................................
vdd_mpu_opp_050 Register (offset = 770h) [reset = 0h] .................................................
vdd_mpu_opp_turbo Register (offset = 77Ch) [reset = 0h] ..............................................
vdd_core_opp_050 Register (offset = 7B8h) [reset = 0h] ................................................
vdd_core_opp_100 Register (offset = 7BCh) [reset = 0h] ................................................
bb_scale Register (offset = 7D0h) [reset = 0h] ............................................................
usb_vid_pid Register (offset = 7F4h) [reset = 4516141h] ................................................
conf_<module>_<pin> Register (offset = 800h) ...........................................................
cqdetect_status Register (offset = E00h) [reset = 0h] ....................................................
ddr_io_ctrl Register (offset = E04h) [reset = 0h] ...........................................................
vtp_ctrl Register (offset = E0Ch) [reset = 0h] ..............................................................
vref_ctrl Register (offset = E14h) [reset = 0h] ..............................................................
tpcc_evt_mux_0_3 Register (offset = F90h) [reset = 0h] .................................................
tpcc_evt_mux_4_7 Register (offset = F94h) [reset = 0h] .................................................
tpcc_evt_mux_8_11 Register (offset = F98h) [reset = 0h] ...............................................
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
914
915
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950

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9.3.58
9.3.59
9.3.60
9.3.61
9.3.62
9.3.63
9.3.64
9.3.65
9.3.66
9.3.67
9.3.68
9.3.69
9.3.70
9.3.71
9.3.72
9.3.73
9.3.74
9.3.75
9.3.76
9.3.77
9.3.78
9.3.79
9.3.80
9.3.81
9.3.82
9.3.83
9.3.84
9.3.85
9.3.86
9.3.87
9.3.88
9.3.89
9.3.90
10
Interconnects
10.1
11
tpcc_evt_mux_12_15 Register (offset = F9Ch) [reset = 0h] .............................................

tpcc_evt_mux_16_19 Register (offset = FA0h) [reset = 0h] ..............................................
tpcc_evt_mux_28_31 Register (offset = FACh) [reset = 0h] .............................................
tpcc_evt_mux_32_35 Register (offset = FB0h) [reset = 0h] ..............................................
tpcc_evt_mux_44_47 Register (offset = FBCh) [reset = 0h] .............................................
tpcc_evt_mux_48_51 Register (offset = FC0h) [reset = 0h] .............................................
tpcc_evt_mux_60_63 Register (offset = FCCh) [reset = 0h] .............................................
timer_evt_capt Register (offset = FD0h) [reset = 0h] .....................................................
ecap_evt_capt Register (offset = FD4h) [reset = 0h] .....................................................
adc_evt_capt Register (offset = FD8h) [reset = 0h] .......................................................
reset_iso Register (offset = 1000h) [reset = 0h] ...........................................................
ddr_cke_ctrl Register (offset = 131Ch) [reset = 0h] .......................................................
sma2 Register (offset = 1320h) [reset = 0h] ................................................................
m3_txev_eoi Register (offset = 1324h) [reset = 0h] .......................................................
ipc_msg_reg0 Register (offset = 1328h) [reset = 0h] .....................................................
ipc_msg_reg1 Register (offset = 132Ch) [reset = 0h] .....................................................
ipc_msg_reg5 Register (offset = 133Ch) [reset = 0h] .....................................................
ddr_cmd0_ioctrl Register (offset = 1404h) [reset = 0h] ...................................................
ddr_cmd1_ioctrl Register (offset = 1408h) [reset = 0h] ...................................................
ddr_cmd2_ioctrl Register (offset = 140Ch) [reset = 0h] ..................................................
ddr_data0_ioctrl Register (offset = 1440h) [reset = 0h] ...................................................
ddr_data1_ioctrl Register (offset = 1444h) [reset = 0h] ...................................................
.................................................................................................................. 989
Introduction ...............................................................................................................
10.1.1 Terminology .....................................................................................................
10.1.2 L3 Interconnect .................................................................................................
10.1.3 L4 Interconnect .................................................................................................
Enhanced Direct Memory Access (EDMA)

11.1
11.2
11.3
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
981
983
985
987
990
990
990
993
........................................................................... 995
Introduction ............................................................................................................... 996

11.1.1 EDMA3 Controller Block Diagram ........................................................................... 996
11.1.2 Third-Party Channel Controller (TPCC) Overview ......................................................... 996
11.1.3 Third-Party Transfer Controller (TPTC) Overview ......................................................... 997
Integration ................................................................................................................. 999
11.2.1 Third-Party Channel Controller (TPCC) Integration ....................................................... 999
11.2.2 Third-Party Transfer Controller (TPTC) Integration ...................................................... 1000
Functional Description ................................................................................................. 1002
11.3.1 Functional Overview ......................................................................................... 1002
11.3.2 Types of EDMA3 Transfers ................................................................................. 1005
11.3.3 Parameter RAM (PaRAM) ................................................................................... 1007
11.3.4 Initiating a DMA Transfer .................................................................................... 1019
11.3.5 Completion of a DMA Transfer ............................................................................. 1022
11.3.6 Event, Channel, and PaRAM Mapping .................................................................... 1023

Contents
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11.4
11.5
12
Touchscreen Controller
12.1
12.2
12.3
12.4
12.5
13
13.2
13.3
1148
1148
1148
1149
1149
1150
1150
1151
1151
1151
1151
1151
1151
1151
1152
1153
1154
1157
1157
............................................................................................................... 1221
Introduction ..............................................................................................................
13.1.1 Purpose of the Peripheral ...................................................................................
13.1.2 Features .......................................................................................................
Integration ...............................................................................................................
13.2.1 LCD Controller Connectivity Attributes ....................................................................
13.2.2 LCD Controller Clock and Reset Management ...........................................................
13.2.3 LCD Controller Pin List ......................................................................................
Functional Description .................................................................................................
13.3.1 Clocking ........................................................................................................
13.3.2 LCD External I/O Signals ....................................................................................
13.3.3 DMA Engine ...................................................................................................
Contents
1025
1027
1028
1034
1038
1040
1043
1043
1044
1044
1044
1044
1046
1062
1065
1065
1119
1143
1143
1144
1145
.................................................................................................. 1147
Introduction ..............................................................................................................
12.1.1 TSC_ADC Features ..........................................................................................
12.1.2 Unsupported TSC_ADC_SS Features ....................................................................
Integration ...............................................................................................................
12.2.1 TSC_ADC Connectivity Attributes ..........................................................................
12.2.2 TSC_ADC Clock and Reset Management ................................................................
12.2.3 TSC_ADC Pin List ............................................................................................
12.3.1 HW Synchronized or SW Channels ........................................................................
12.3.2 Open Delay and Sample Delay .............................................................................
12.3.3 Averaging of Samples (1, 2, 4, 8, and 16) ................................................................
12.3.4 One-Shot (Single) or Continuous Mode ...................................................................
12.3.5 Interrupts ......................................................................................................
12.3.6 DMA Requests ................................................................................................
12.3.7 Analog Front End (AFE) Functional Block Diagram .....................................................
Operational Modes .....................................................................................................
12.4.1 PenCtrl and PenIRQ .........................................................................................
Touchscreen Controller Registers ....................................................................................
12.5.1 TSC_ADC_SS Registers ....................................................................................
LCD Controller
13.1
11.3.7 EDMA3 Channel Controller Regions .......................................................................

11.3.8 Chaining EDMA3 Channels .................................................................................
11.3.9 EDMA3 Interrupts ............................................................................................
11.3.10 Memory Protection ..........................................................................................
11.3.11 Event Queue(s) .............................................................................................
11.3.12 EDMA3 Transfer Controller (EDMA3TC) ................................................................
11.3.13 Event Dataflow ..............................................................................................
11.3.14 EDMA3 Prioritization .......................................................................................
11.3.15 EDMA3 Operating Frequency (Clock Control) ..........................................................
11.3.16 Reset Considerations .......................................................................................
11.3.17 Power Management ........................................................................................
11.3.18 Emulation Considerations ..................................................................................
11.3.19 EDMA Transfer Examples .................................................................................
11.3.20 EDMA Events ................................................................................................
EDMA3 Registers ......................................................................................................
11.4.1 EDMA3 Channel Controller Registers .....................................................................
11.4.2 EDMA3 Transfer Controller Registers .....................................................................
Appendix A ..............................................................................................................
11.5.1 Debug Checklist ..............................................................................................
11.5.2 Miscellaneous Programming/Debug Tips .................................................................
11.5.3 Setting Up a Transfer ........................................................................................
1222
1222
1223
1224
1224
1225
1225
1226
1226
1228
1229

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13.4
13.5
14
13.3.4 LIDD Controller ...............................................................................................

13.3.5 Raster Controller .............................................................................................
13.3.6 Interrupt Conditions ..........................................................................................
13.3.7 DMA ............................................................................................................
13.3.8 Power Management ..........................................................................................
Programming Model ....................................................................................................
13.4.1 LCD Character Displays .....................................................................................
13.4.2 Active Matrix Displays .......................................................................................
13.4.3 System Interaction ...........................................................................................
13.4.4 Palette Lookup ................................................................................................
13.4.5 Test Logic .....................................................................................................
13.4.6 Disable and Software Reset Sequence ...................................................................
13.4.7 Precedence Order for Determining Frame Buffer Type .................................................
LCD Registers ..........................................................................................................
13.5.1 PID Register (offset = 0h) [reset = 0h] .....................................................................
13.5.2 CTRL Register (offset = 4h) [reset = 0h] ..................................................................
13.5.3 LIDD_CTRL Register (offset = Ch) [reset = 0h] ..........................................................
13.5.4 LIDD_CS0_CONF Register (offset = 10h) [reset = 0h] ..................................................
13.5.5 LIDD_CS0_ADDR Register (offset = 14h) [reset = 0h] ..................................................
13.5.6 LIDD_CS0_DATA Register (offset = 18h) [reset = 0h] ..................................................
13.5.7 LIDD_CS1_CONF Register (offset = 1Ch) [reset = 0h] .................................................
13.5.8 LIDD_CS1_ADDR Register (offset = 20h) [reset = 0h] ..................................................
13.5.9 LIDD_CS1_DATA Register (offset = 24h) [reset = 0h] ..................................................
13.5.10 RASTER_CTRL Register (offset = 28h) [reset = 0h] ...................................................
13.5.11 RASTER_TIMING_0 Register (offset = 2Ch) [reset = 0h] .............................................
13.5.12 RASTER_TIMING_1 Register (offset = 30h) [reset = 0h] .............................................
13.5.13 RASTER_TIMING_2 Register (offset = 34h) [reset = 0h] .............................................
13.5.14 RASTER_SUBPANEL Register (offset = 38h) [reset = 0h] ...........................................
13.5.15 RASTER_SUBPANEL2 Register (offset = 3Ch) [reset = 0h] .........................................
13.5.16 LCDDMA_CTRL Register (offset = 40h) [reset = 0h] ..................................................
13.5.17 LCDDMA_FB0_BASE Register (offset = 44h) [reset = 0h] ............................................
13.5.18 LCDDMA_FB0_CEILING Register (offset = 48h) [reset = 0h] ........................................
13.5.19 LCDDMA_FB1_BASE Register (offset = 4Ch) [reset = 0h] ...........................................
13.5.20 LCDDMA_FB1_CEILING Register (offset = 50h) [reset = 0h] ........................................
13.5.21 SYSCONFIG Register (offset = 54h) [reset = 0h] ......................................................
13.5.22 IRQSTATUS_RAW Register (offset = 58h) [reset = 0h] ...............................................
13.5.23 IRQSTATUS Register (offset = 5Ch) [reset = 0h] ......................................................
13.5.24 IRQENABLE_SET Register (offset = 60h) [reset = 0h] ................................................
13.5.25 IRQENABLE_CLEAR Register (offset = 64h) [reset = 0h] ............................................
13.5.26 CLKC_ENABLE Register (offset = 6Ch) [reset = 0h] ..................................................
13.5.27 CLKC_RESET Register (offset = 70h) [reset = 0h] ....................................................
Ethernet Subsystem
14.1
14.2
1230
1232
1243
1245
1245
1246
1246
1249
1249
1249
1251
1251
1252
1252
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1266
1267
1268
1270
1271
1272
1274
1275
1276
1277
1278
1280
1282
1284
1286
1288
1289
....................................................................................................... 1290
Introduction ..............................................................................................................
14.1.1 Features .......................................................................................................
14.1.2 Unsupported Features .......................................................................................
Integration ...............................................................................................................
14.2.1 Ethernet Switch Connectivity Attributes ...................................................................
14.2.2 Ethernet Switch Clock and Reset Management ..........................................................
14.2.3 Ethernet Switch Pin List .....................................................................................
14.2.4 Ethernet Switch RMII Clocking Details ....................................................................
14.2.5 GMII Interface Signal Connections and Descriptions ....................................................
14.2.6 RMII Signal Connections and Descriptions ...............................................................
14.2.7 RGMII Signal Connections and Descriptions .............................................................

Contents
1291
1291
1292
1293
1293
1295
1296
1296
1297
1300
1301
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14.3
14.4
14.5
15
Pulse-Width Modulation Subsystem (PWMSS)

15.1
15.2
15.3
15.4
16
16.2
1614
1614
1616
1618
1623
1623
1627
1686
1710
1736
1736
1737
1747
1763
1775
1775
1778
1796
.............................................................................................. 1814
Introduction ..............................................................................................................
16.1.1 Acronyms, Abbreviations, and Definitions .................................................................
16.1.2 Unsupported USB OTG and PHY Features ..............................................................
Integration ...............................................................................................................
16.2.1 USB Connectivity Attributes .................................................................................
16.2.2 USB Clock and Reset Management .......................................................................
Contents
1303
1303
1308
1350
1352
1353
1353
1356
1361
1363
1363
1365
1366
1366
1367
1367
1368
1368
1383
1436
1449
1449
1483
1539
1553
1566
1602
................................................................... 1613
Pulse-Width Modulation Subsystem (PWMSS) ....................................................................

15.1.1 Introduction ....................................................................................................
15.1.2 Integration .....................................................................................................
15.1.3 PWMSS Configuration Registers ...........................................................................
Enhanced PWM (ePWM) Module ....................................................................................
15.2.1 Introduction ....................................................................................................
15.2.2 Functional Description .......................................................................................
15.2.3 Use Cases .....................................................................................................
15.2.4 Registers ......................................................................................................
Enhanced Capture (eCAP) Module ..................................................................................
15.3.1 Introduction ....................................................................................................
15.3.3 Use Cases .....................................................................................................
15.3.4 Registers ......................................................................................................
Enhanced Quadrature Encoder Pulse (eQEP) Module ...........................................................
15.4.1 Introduction ....................................................................................................
15.4.3 eQEP Registers ..............................................................................................
Universal Serial Bus (USB)

16.1

14.3.1 CPSW_3G Subsystem .......................................................................................
14.3.2 CPSW_3G .....................................................................................................
14.3.3 Ethernet Mac Sliver (CPGMAC_SL) .......................................................................
14.3.4 Command IDLE ...............................................................................................
14.3.5 RMII Interface .................................................................................................
14.3.6 RGMII Interface ...............................................................................................
14.3.7 Common Platform Time Sync (CPTS) .....................................................................
14.3.8 MDIO ...........................................................................................................
Software Operation .....................................................................................................
14.4.1 Transmit Operation ...........................................................................................
14.4.2 Receive Operation ...........................................................................................
14.4.3 Initializing the MDIO Module ................................................................................
14.4.4 Writing Data to a PHY Register ............................................................................
14.4.5 Reading Data from a PHY Register ........................................................................
14.4.6 Initialization and Configuration of CPSW ..................................................................
Ethernet Subsystem Registers .......................................................................................
14.5.1 CPSW_ALE Registers .......................................................................................
14.5.2 CPSW_CPDMA Registers ..................................................................................
14.5.3 CPSW_CPTS Registers .....................................................................................
14.5.4 CPSW_STATS Registers ...................................................................................
14.5.5 CPDMA_STATERAM Registers ............................................................................
14.5.6 CPSW_PORT Registers .....................................................................................
14.5.7 CPSW_SL Registers .........................................................................................
14.5.8 CPSW_SS Registers ........................................................................................
14.5.9 CPSW_WR Registers ........................................................................................
14.5.10 Management Data Input/Output (MDIO) Registers .....................................................
1815
1815
1817
1818
1818
1819

www.ti.com
16.3
16.4
16.5
17
Interprocessor Communication
17.1
17.2
18
16.2.3 USB Pin List ...................................................................................................

16.2.4 USB GPIO Details ............................................................................................
16.2.5 USB Unbonded PHY Pads ..................................................................................
16.3.1 VBUS Voltage Sourcing Control ............................................................................
16.3.2 Pull-up/Pull-Down Resistors ................................................................................
16.3.3 Role Assuming Method ......................................................................................
16.3.4 Clock, PLL, and PHY Initialization .........................................................................
16.3.5 Indexed and Non-Indexed Register Spaces ..............................................................
16.3.6 Dynamic FIFO Sizing ........................................................................................
16.3.7 USB Controller Host and Peripheral Modes Operation ..................................................
16.3.8 Protocol Description(s) .......................................................................................
16.3.9 Communications Port Programming Interface (CPPI) 4.1 DMA .......................................
16.3.10 USB 2.0 Test Modes .......................................................................................
Supported Use Cases .................................................................................................
USB Registers ..........................................................................................................
16.5.1 USBSS Registers .............................................................................................
16.5.2 USB0_CTRL Registers ......................................................................................
16.5.3 USB1_CTRL Registers ......................................................................................
16.5.4 USB2PHY Registers .........................................................................................
16.5.5 CPPI_DMA Registers ........................................................................................
16.5.6 CPPI_DMA_SCHEDULER Registers ......................................................................
16.5.7 QUEUE_MGR Registers ....................................................................................
18.1
18.2
18.3
........................................................................................ 3425
Mailbox ...................................................................................................................
17.1.1 Introduction ....................................................................................................
17.1.2 Integration .....................................................................................................
17.1.4 Programming Guide ..........................................................................................
17.1.5 MAILBOX Registers ..........................................................................................
Spinlock ..................................................................................................................
17.2.1 SPINLOCK Registers ........................................................................................
Multimedia Card (MMC)
1819
1819
1820
1821
1821
1821
1822
1822
1823
1823
1824
1825
1858
1883
1884
1885
1885
1928
1978
2026
2053
2209
2274
3426
3426
3427
3428
3432
3435
3496
3496
................................................................................................... 3534
Introduction ..............................................................................................................
18.1.1 MMCHS Features ............................................................................................
18.1.2 Unsupported MMCHS Features ............................................................................
Integration ...............................................................................................................
18.2.1 MMCHS Connectivity Attributes ............................................................................
18.2.2 MMCHS Clock and Reset Management ..................................................................
18.2.3 MMCHS Pin List ..............................................................................................
18.3.1 MMC/SD/SDIO Functional Modes .........................................................................
18.3.2 Resets .........................................................................................................
18.3.4 Interrupt Requests ............................................................................................
18.3.5 DMA Modes ...................................................................................................
18.3.6 Mode Selection ...............................................................................................
18.3.7 Buffer Management ..........................................................................................
18.3.8 Transfer Process .............................................................................................
18.3.9 Transfer or Command Status and Error Reporting ......................................................
18.3.10 Auto Command 12 Timings ................................................................................
18.3.11 Transfer Stop ................................................................................................
18.3.12 Output Signals Generation ................................................................................

Contents
3535
3535
3535
3536
3537
3538
3538
3540
3540
3547
3548
3551
3553
3556
3556
3559
3560
3565
3567
3568
9
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18.4
19
Universal Asynchronous Receiver/Transmitter (UART)

19.1
19.2
19.3
19.4
19.5
20
20.2
20.3
20.4
3626
3626
3626
3626
3626
3628
3628
3629
3631
3632
3632
3633
3633
3633
3635
3638
3646
3652
3675
3675
3681
3684
3684
.......................................................................................................................... 3728
DMTimer .................................................................................................................
20.1.1 Introduction ....................................................................................................
20.1.2 Integration .....................................................................................................
20.1.4 Use Cases .....................................................................................................
20.1.5 TIMER Registers .............................................................................................
DMTimer 1ms ...........................................................................................................
20.2.1 Introduction ....................................................................................................
20.2.2 Integration .....................................................................................................
20.2.4 Use Cases .....................................................................................................
20.2.5 DMTIMER_1MS Registers ..................................................................................
RTC_SS .................................................................................................................
20.3.1 Introduction ....................................................................................................
20.3.2 Integration .....................................................................................................
20.3.4 Use Cases .....................................................................................................
20.3.5 RTC Registers ................................................................................................
WATCHDOG ............................................................................................................
20.4.1 Introduction ....................................................................................................
20.4.2 Integration .....................................................................................................
Contents
3570
3571
3571
3572
3573
3578
3578
....................................................... 3625
Introduction ..............................................................................................................
19.1.1 UART Mode Features ........................................................................................
19.1.2 IrDA Mode Features .........................................................................................
19.1.3 CIR Mode Features ..........................................................................................
19.1.4 Unsupported UART Features ...............................................................................
Integration ...............................................................................................................
19.2.1 UART Connectivity Attributes ...............................................................................
19.2.2 UART Clock and Reset Management .....................................................................
19.2.3 UART Pin List .................................................................................................
19.3.1 Block Diagram ................................................................................................
19.3.2 Clock Configuration ..........................................................................................
19.3.3 Software Reset ...............................................................................................
19.3.5 Interrupt Requests ............................................................................................
19.3.6 FIFO Management ...........................................................................................
19.3.7 Mode Selection ...............................................................................................
19.3.8 Protocol Formatting ..........................................................................................
UART/IrDA/CIR Basic Programming Model .........................................................................
19.4.1 UART Programming Model .................................................................................
19.4.2 IrDA Programming Model ...................................................................................
UART Registers ........................................................................................................
19.5.1 UART Registers ..............................................................................................
Timers
20.1
10
18.3.13 Card Boot Mode Management ............................................................................

18.3.14 CE-ATA Command Completion Disable Management ................................................
18.3.15 Test Registers ...............................................................................................
18.3.16 MMC/SD/SDIO Hardware Status Features ..............................................................
18.3.17 Low-Level Programming Models ..........................................................................
Multimedia Card Registers ............................................................................................
18.4.1 MMC/SD/SDIO Registers ...................................................................................
3729
3729
3731
3733
3742
3742
3760
3760
3762
3764
3772
3772
3796
3796
3797
3798
3806
3806
3844
3844
3845

www.ti.com
20.4.3 Functional Description ....................................................................................... 3846

20.4.4 Use Cases ..................................................................................................... 3853
20.4.5 Watchdog Timer Registers .................................................................................. 3854
21
I2C ................................................................................................................................ 3865

21.1
21.2
21.3
21.4
22
Introduction ..............................................................................................................
21.1.1 I2C Features ..................................................................................................
21.1.2 Unsupported I2C Features ..................................................................................
Integration ...............................................................................................................
21.2.1 I2C Connectivity Attributes ..................................................................................
21.2.2 I2C Clock and Reset Management ........................................................................
21.2.3 I2C Pin List ....................................................................................................
21.3.1 Functional Block Diagram ...................................................................................
21.3.2 I2C Master/Slave Contoller Signals ........................................................................
21.3.3 I2C Reset ......................................................................................................
21.3.4 Data Validity ...................................................................................................
21.3.5 START & STOP Conditions .................................................................................
21.3.6 I2C Operation .................................................................................................
21.3.7 Arbitration ......................................................................................................
21.3.8 I2C Clock Generation and I2C Clock Synchronization ..................................................
21.3.9 Prescaler (SCLK/ICLK) ......................................................................................
21.3.10 Noise Filter ...................................................................................................
21.3.11 I2C Interrupts ................................................................................................
21.3.12 DMA Events .................................................................................................
21.3.13 Interrupt and DMA Events .................................................................................
21.3.14 FIFO Management ..........................................................................................
21.3.15 How to Program I2C ........................................................................................
Registers .................................................................................................................
21.4.1 I2C Registers .................................................................................................
Multichannel Audio Serial Port (McASP)

22.1
22.2
22.3
........................................................................... 3925
Introduction ..............................................................................................................
22.1.2 Features .......................................................................................................
22.1.3 Protocols Supported .........................................................................................
22.1.4 Unsupported McASP Features .............................................................................
Integration ...............................................................................................................
22.2.1 McASP Connectivity Attributes .............................................................................
22.2.2 McASP Clock and Reset Management ....................................................................
22.2.3 McASP Pin List ...............................................................................................
22.3.1 Overview .......................................................................................................
22.3.2 Functional Block Diagram ...................................................................................
22.3.3 Industry Standard Compliance Statement ................................................................
22.3.4 Definition of Terms ...........................................................................................
22.3.5 Clock and Frame Sync Generators ........................................................................
22.3.6 Signal Descriptions ...........................................................................................
22.3.7 Pin Multiplexing ...............................................................................................
22.3.8 Transfer Modes ...............................................................................................
22.3.9 General Architecture .........................................................................................
22.3.10 Operation .....................................................................................................
22.3.11 Reset Considerations .......................................................................................
22.3.12 Setup and Initialization .....................................................................................
22.3.13 Interrupts .....................................................................................................

3866
3866
3866
3867
3867
3868
3868
3869
3869
3869
3870
3870
3872
3872
3874
3874
3875
3875
3875
3876
3876
3876
3880
3882
3882
Contents
3926
3926
3926
3926
3927
3928
3928
3929
3929
3930
3930
3931
3934
3938
3940
3944
3944
3945
3952
3956
3973
3973
3978
11
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22.4
23
Controller Area Network (CAN)

23.1
23.2
23.3
23.4
24
24.2
24.3
4038
4038
4038
4039
4039
4040
4040
4041
4041
4042
4042
4042
4042
4042
4042
4043
4049
4050
4052
4054
4055
4055
4058
4063
4071
4073
4078
4079
4079
......................................................................... 4120
Introduction ..............................................................................................................
24.1.1 McSPI Features ..............................................................................................
24.1.2 Unsupported McSPI Features ..............................................................................
Integration ...............................................................................................................
24.2.1 McSPI Connectivity Attributes ..............................................................................
24.2.2 McSPI Clock and Reset Management .....................................................................
24.2.3 McSPI Pin List ................................................................................................
24.3.1 SPI Transmission .............................................................................................
24.3.2 Master Mode ..................................................................................................
24.3.3 Slave Mode ....................................................................................................
24.3.4 Interrupts ......................................................................................................
24.3.5 DMA Requests ................................................................................................
24.3.6 Emulation Mode ..............................................................................................
24.3.7 Power Saving Management .................................................................................
24.3.8 System Test Mode ...........................................................................................
Contents
3980
3982
3982
3983
3983
4036
........................................................................................ 4037
Introduction ..............................................................................................................
23.1.1 DCAN Features ...............................................................................................
23.1.2 Unsupported DCAN Features ...............................................................................
Integration ...............................................................................................................
23.2.1 DCAN Connectivity Attributes ...............................................................................
23.2.2 DCAN Clock and Reset Management .....................................................................
23.2.3 DCAN Pin List .................................................................................................
23.3.1 CAN Core ......................................................................................................
23.3.2 Message Handler .............................................................................................
23.3.3 Message RAM ................................................................................................
23.3.4 Message RAM Interface .....................................................................................
23.3.5 Registers and Message Object Access ...................................................................
23.3.6 Module Interface ..............................................................................................
23.3.7 Dual Clock Source ...........................................................................................
23.3.8 CAN Operation ................................................................................................
23.3.9 Dual Clock Source ...........................................................................................
23.3.10 Interrupt Functionality ......................................................................................
23.3.11 Local Power-Down Mode ..................................................................................
23.3.12 Parity Check Mechanism ..................................................................................
23.3.13 Debug/Suspend Mode .....................................................................................
23.3.14 Configuration of Message Objects ........................................................................
23.3.15 Message Handling ..........................................................................................
23.3.16 CAN Bit Timing ..............................................................................................
23.3.17 Message Interface Register Sets .........................................................................
23.3.18 Message RAM ...............................................................................................
23.3.19 GIO Support .................................................................................................
DCAN Registers ........................................................................................................
23.4.1 DCAN Control Registers .....................................................................................
Multichannel Serial Port Interface (McSPI)

24.1
12
22.3.14 EDMA Event Support .......................................................................................

22.3.15 Power Management ........................................................................................
22.3.16 Emulation Considerations ..................................................................................
McASP Registers .......................................................................................................
22.4.1 McASP CFG Registers ......................................................................................
22.4.2 McASP Data Port Registers ................................................................................
4121
4121
4121
4121
4123
4123
4123
4124
4124
4131
4149
4153
4154
4155
4156
4157

www.ti.com
24.4
24.5
25
General-Purpose Input/Output
25.1
25.2
25.3
25.4
26
4157
4158
4158
4159
4159
4159
4160
......................................................................................... 4183
Introduction ..............................................................................................................
25.1.2 GPIO Features ................................................................................................
25.1.3 Unsupported GPIO Features ...............................................................................
Integration ...............................................................................................................
25.2.1 GPIO Connectivity Attributes ...............................................................................
25.2.2 GPIO Clock and Reset Management ......................................................................
25.2.3 GPIO Pin List .................................................................................................
25.3.1 Operating Modes .............................................................................................
25.3.2 Clocking and Reset Strategy ................................................................................
25.3.3 Interrupt Features ............................................................................................
25.3.4 General-Purpose Interface Basic Programming Model .................................................
GPIO Registers .........................................................................................................
25.4.1 GPIO Registers ...............................................................................................
Initialization
26.1
24.3.9 Reset ...........................................................................................................

24.3.10 Access to Data Registers ..................................................................................
24.3.11 Programming Aid ...........................................................................................
24.3.12 Interrupt and DMA Events .................................................................................
Use Cases ...............................................................................................................
McSPI Registers ........................................................................................................
24.5.1 SPI Registers .................................................................................................
4184
4184
4184
4184
4185
4185
4186
4187
4188
4188
4188
4189
4191
4194
4194
................................................................................................................... 4219

26.1.1 Architecture ...................................................................................................
26.1.2 Functionality ...................................................................................................
26.1.3 Memory Map ..................................................................................................
26.1.4 Start-up and Configuration ..................................................................................
26.1.5 Booting .........................................................................................................
26.1.6 Fast External Booting ........................................................................................
26.1.7 Memory Booting ..............................................................................................
26.1.8 Peripheral Booting ............................................................................................
26.1.9 Image Format .................................................................................................
26.1.10 Code Execution ............................................................................................
26.1.11 Wakeup ......................................................................................................
26.1.12 Tracing .......................................................................................................
Revision History
4220
4220
4220
4221
4225
4227
4236
4238
4265
4270
4271
4272
4273
............................................................................................................ 4277

Contents
13
www.ti.com
List of Figures
3-1.
Microprocessor Unit (MPU) Subsystem Signal Interface ........................................................... 172
3-3.
MPU Subsystem Clocking Scheme
3-4.
3-5.
...................................................................................
173
Reset Scheme of the MPU Subsystem ............................................................................... 174
MPU Subsystem Power Domain Overview ........................................................................... 177
5-1.
SGX530 Integration ...................................................................................................... 187
5-2.
SGX Block Diagram
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
6-20.
6-21.
6-22.
6-23.
6-24.
6-25.
6-26.
6-27.
6-28.
6-29.
6-30.
6-31.
6-32.
6-33.
6-34.
6-35.
6-36.
6-37.
6-38.
6-39.
6-40.
14
Microprocessor Unit (MPU) Subsystem ............................................................................... 170
3-2.
.....................................................................................................
Interrupt Controller Block Diagram ....................................................................................
IRQ/FIQ Processing Sequence ........................................................................................
Nested IRQ/FIQ Processing Sequence ..............................................................................
INTC_REVISION Register ..............................................................................................
INTC_SYSCONFIG Register ...........................................................................................
INTC_SYSSTATUS Register ...........................................................................................
INTC_SIR_IRQ Register ................................................................................................
INTC_SIR_FIQ Register ................................................................................................
INTC_CONTROL Register ..............................................................................................
INTC_PROTECTION Register .........................................................................................
INTC_IDLE Register .....................................................................................................
INTC_IRQ_PRIORITY Register ........................................................................................
INTC_FIQ_PRIORITY Register ........................................................................................
INTC_THRESHOLD Register ..........................................................................................
INTC_ITR0 Register .....................................................................................................
INTC_MIR0 Register ....................................................................................................
INTC_MIR_CLEAR0 Register ..........................................................................................
INTC_MIR_SET0 Register ..............................................................................................
INTC_ISR_SET0 Register ..............................................................................................
INTC_ISR_CLEAR0 Register ..........................................................................................
INTC_PENDING_IRQ0 Register .......................................................................................
INTC_PENDING_FIQ0 Register .......................................................................................
List of Figures
189
192
198
202
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251

www.ti.com
6-41.
6-42.
INTC_MIR_CLEAR3 Register .......................................................................................... 252
INTC_MIR_SET3 Register .............................................................................................. 253
6-43.
INTC_ISR_SET3 Register .............................................................................................. 254
6-44.
INTC_ISR_CLEAR3 Register
6-45.
6-46.
6-47.
6-48.
6-49.
6-50.
6-51.
6-52.
6-53.
6-54.
6-55.
6-56.
6-57.
6-58.
6-59.
6-60.
6-61.
6-62.
6-63.
6-64.
6-65.
6-66.
6-67.
6-68.
6-69.
6-70.
6-71.
6-72.
6-73.
6-74.
6-75.
6-76.
6-77.
6-78.
6-79.
6-80.
6-81.
6-82.
6-83.
6-84.
6-85.
6-86.
6-87.
6-88.
6-89.
..........................................................................................
INTC_ILR0 Register .....................................................................................................
INTC_ILR10 Register ....................................................................................................

List of Figures
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
15
www.ti.com
6-90.
6-91.
6-92.
6-93.
6-94.
6-95.
6-96.
6-97.
6-98.
6-99.
INTC_ILR43 Register .................................................................................................... 301

6-100. INTC_ILR53 Register .................................................................................................... 311

16
List of Figures

www.ti.com

6-147. INTC_ILR100 Register .................................................................................................. 358

7-1.
7-2.
7-3.
GPMC Block Diagram ................................................................................................... 389

GPMC Integration ........................................................................................................ 390
GPMC to 16-Bit Address/Data-Multiplexed Memory ................................................................ 394
7-4.
GPMC to 16-Bit Non-multiplexed Memory ............................................................................ 395
7-5.
GPMC to 8-Bit NAND Device
7-6.
7-7.
7-8.
7-9.
..........................................................................................
Chip-Select Address Mapping and Decoding Mask .................................................................
Wait Behavior During an Asynchronous Single Read Access (GPMCFCLKDivider = 1) ......................
Wait Behavior During a Synchronous Read Burst Access .........................................................
395
400
403
405
Read to Read for an Address-Data Multiplexed Device, On Different CS, Without Bus Turnaround (CS0n
Attached to Fast Device) ................................................................................................ 407
7-10.
Read to Read / Write for an Address-Data Multiplexed Device, On Different CS, With Bus Turnaround.... 407
7-11.
Read to Read / Write for a Address-Data or AAD-Multiplexed Device, On Same CS, With Bus
Turnaround................................................................................................................ 408

List of Figures
17
www.ti.com
7-12.
Asynchronous Single Read Operation on an Address/Data Multiplexed Device ................................ 417
7-13.
Two Asynchronous Single Read Accesses on an Address/Data Multiplexed Device (32-Bit Read Split
Into 2 16-Bit Read) .................................................................................................... 418
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
7-22.
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
7-52.
7-53.
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
18
Asynchronous Single Write on an Address/Data-Multiplexed Device............................................. 419

Asynchronous Single-Read on an AAD-Multiplexed Device ....................................................... 420
.......................................................
Synchronous Single Read (GPMCFCLKDIVIDER = 0) .............................................................
Synchronous Single Read (GPMCFCLKDIVIDER = 1) .............................................................
Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 0) ..................................................
Synchronous Multiple (Burst) Read (GPMCFCLKDIVIDER = 1) ..................................................
Synchronous Single Write on an Address/Data-Multiplexed Device ..............................................
Synchronous Multiple Write (Burst Write) in Address/Data-Multiplexed Mode ..................................
Synchronous Multiple Write (Burst Write) in Address/Address/Data-Multiplexed Mode ........................
Asynchronous Single Read on an Address/Data-Nonmultiplexed Device .......................................
Asynchronous Single Write on an Address/Data-Nonmultiplexed Device ........................................
Asynchronous Multiple (Page Mode) Read...........................................................................
NAND Command Latch Cycle ..........................................................................................
NAND Address Latch Cycle ............................................................................................
NAND Data Read Cycle ................................................................................................
NAND Data Write Cycle .................................................................................................
Hamming Code Accumulation Algorithm (1 of 2) ....................................................................
Hamming Code Accumulation Algorithm (2 of 2) ....................................................................
ECC Computation for a 256-Byte Data Stream (Read or Write) ..................................................
ECC Computation for a 512-Byte Data Stream (Read or Write) ..................................................
128 Word16 ECC Computation ........................................................................................
256 Word16 ECC Computation ........................................................................................
Manual Mode Sequence and Mapping ................................................................................
NAND Page Mapping and ECC: Per-Sector Schemes .............................................................
NAND Page Mapping and ECC: Pooled Spare Schemes ..........................................................
NAND Page Mapping and ECC: Per-Sector Schemes, with Separate ECC .....................................
NAND Read Cycle Optimization Timing Description ................................................................
Programming Model Top-Level Diagram .............................................................................
NOR Interfacing Timing Parameters Diagram .......................................................................
NAND Command Latch Cycle Timing Simplified Example .........................................................
Synchronous NOR Single Read Simplified Example................................................................
Asynchronous NOR Single Write Simplified Example ..............................................................
GPMC Connection to an External NOR Flash Memory.............................................................
Synchronous Burst Read Access (Timing Parameters in Clock Cycles) .........................................
Asynchronous Single Read Access (Timing Parameters in Clock Cycles) ......................................
Asynchronous Single Write Access (Timing Parameters in Clock Cycles) .......................................
GPMC_REVISION .......................................................................................................
GPMC_SYSCONFIG ....................................................................................................
GPMC_SYSSTATUS ....................................................................................................
GPMC_IRQSTATUS ....................................................................................................
GPMC_IRQENABLE ....................................................................................................
GPMC_TIMEOUT_CONTROL .........................................................................................
GPMC_ERR_ADDRESS ................................................................................................
GPMC_ERR_TYPE ......................................................................................................
GPMC_CONFIG .........................................................................................................
Asynchronous Single Write on an AAD-Multiplexed Device
List of Figures
422
424
425
427
428
429
430
431
433
434
435
440
441
442
443
447
448
448
449
450
450
455
460
461
462
469
472
479
483
488
490
492
494
496
498
503
503
504
505
506
507
507
508
509

www.ti.com
7-60.
7-61.
7-62.
7-63.
7-64.
7-65.
7-66.
GPMC_STATUS ......................................................................................................... 510
GPMC_CONFIG1_i ...................................................................................................... 511

GPMC_CONFIG2_i ...................................................................................................... 514
GPMC_CONFIG3_i ...................................................................................................... 515
GPMC_CONFIG4_i ...................................................................................................... 517
GPMC_CONFIG5_i ...................................................................................................... 519
GPMC_CONFIG6_i ...................................................................................................... 520
7-67.
GPMC_CONFIG7_i ...................................................................................................... 521
7-68.
GPMC_NAND_COMMAND_i
7-69.
7-70.
7-71.
7-72.
7-73.
7-74.
7-75.
7-76.
7-77.
7-78.
7-79.
7-80.
7-81.
7-82.
7-83.
7-84.
7-85.
7-86.
7-87.
7-88.
7-89.
7-90.
7-91.
7-92.
7-93.
7-94.
7-95.
7-96.
7-97.
7-98.
7-99.
7-100.
7-101.
7-102.
7-103.
7-104.
7-105.
7-106.
7-107.
7-108.
..........................................................................................
GPMC_NAND_ADDRESS_i............................................................................................
GPMC_NAND_DATA_i .................................................................................................
GPMC_PREFETCH_CONFIG1 ........................................................................................
GPMC_PREFETCH_CONFIG2 ........................................................................................
GPMC_PREFETCH_CONTROL .......................................................................................
GPMC_PREFETCH_STATUS .........................................................................................
GPMC_ECC_CONFIG ..................................................................................................
GPMC_ECC_CONTROL ...............................................................................................
GPMC_ECC_SIZE_CONFIG ...........................................................................................
GPMC_ECCj_RESULT .................................................................................................
GPMC_BCH_RESULT0_i ..............................................................................................
GPMC_BCH_RESULT1_i ..............................................................................................
GPMC_BCH_RESULT2_i ..............................................................................................
GPMC_BCH_RESULT3_i ..............................................................................................
GPMC_BCH_SWDATA .................................................................................................
GPMC_BCH_RESULT4_i ..............................................................................................
GPMC_BCH_RESULT5_i ..............................................................................................
GPMC_BCH_RESULT6_i ..............................................................................................
OCMC RAM Integration .................................................................................................
DDR2/3/mDDR Memory Controller Signals ..........................................................................
DDR2/3/mDDR Subsystem Block Diagram ..........................................................................
DDR2/3/mDDR Memory Controller FIFO Block Diagram ...........................................................
EMIF_MOD_ID_REV Register .........................................................................................
STATUS Register ........................................................................................................
SDRAM_CONFIG Register .............................................................................................
SDRAM_CONFIG_2 Register ..........................................................................................
SDRAM_REF_CTRL Register .........................................................................................
SDRAM_REF_CTRL_SHDW Register ................................................................................
SDRAM_TIM_1 Register ................................................................................................
SDRAM_TIM_1_SHDW Register ......................................................................................
PWR_MGMT_CTRL Register ..........................................................................................
PWR_MGMT_CTRL_SHDW Register ................................................................................
PERF_CNT_1 Register .................................................................................................
PERF_CNT_2 Register .................................................................................................
PERF_CNT_CFG Register .............................................................................................
PERF_CNT_SEL Register ..............................................................................................

List of Figures
522
522
522
523
525
525
526
527
528
529
531
532
532
532
533
533
533
534
534
536
541
543
544
560
561
562
564
565
566
567
568
569
570
571
572
573
575
576
577
578
579
19
www.ti.com
7-109. PERF_CNT_TIM Register .............................................................................................. 580
7-110. READ_IDLE_CTRL Register ........................................................................................... 581
.................................................................................
....................................................................................
IRQSTATUS_SYS Register ............................................................................................
IRQENABLE_SET_SYS Register......................................................................................
IRQENABLE_CLR_SYS Register .....................................................................................
ZQ_CONFIG Register ...................................................................................................
Read-Write Leveling Ramp Window Register Register .............................................................
Read-Write Leveling Ramp Control Register Register ..............................................................
Read-Write Leveling Control Register Register ......................................................................
DDR_PHY_CTRL_1 Register ..........................................................................................
DDR_PHY_CTRL_1_SHDW Register ................................................................................
Priority to Class of Service Mapping Register Register .............................................................
Connection ID to Class of Service 1 Mapping Register Register ..................................................
Connection ID to Class of Service 2 Mapping Register Register ..................................................
Read Write Execution Threshold Register Register .................................................................
7-111. READ_IDLE_CTRL_SHDW Register
582
7-112. IRQSTATUS_RAW_SYS Register
583
7-113.
7-114.
7-115.
7-116.
7-117.
7-118.
7-119.
7-120.
7-121.
7-122.
7-123.
7-124.
7-125.
584
585
586
587
588
589
590
591
593
595
596
597
599
7-126. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register

(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0) .................................................................. 602
7-127. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register(
CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) ........................................................................ 602
7-128. DDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0) ...................................................................... 603
7-129. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0)) .............................................................. 603
7-130. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) ..................................................................... 604
7-131. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0) .................................................................... 605
7-132. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0).................................................................... 605
7-133. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) ................................................................. 606
7-134. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio
Register(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) .................................................... 606
7-135. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) ............................................................. 607
7-136. DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS) ...... 608
..........................................................................................................
ELM Revision Register (ELM_REVISION) ...........................................................................
ELM System Configuration Register (ELM_SYSCONFIG) .........................................................
ELM System Status Register (ELM_SYSSTATUS) .................................................................
ELM Interrupt Status Register (ELM_IRQSTATUS) .................................................................
ELM Interrupt Enable Register (ELM_IRQENABLE) ................................................................
ELM Location Configuration Register (ELM_LOCATION_CONFIG) ..............................................
ELM Page Definition Register (ELM_PAGE_CTRL) ................................................................
ELM_SYNDROME_FRAGMENT_0_i Register ......................................................................
7-137. ELM Integration

7-138.
7-139.
7-140.
7-141.
7-142.
7-143.
7-144.
7-145.
7-146.
7-147.
7-148.
7-149.
20
List of Figures
610
621
621
622
623
625
626
627
628
628
628
629
629

www.ti.com
7-150. ELM_SYNDROME_FRAGMENT_5_i Register ...................................................................... 629
7-151. ELM_SYNDROME_FRAGMENT_6_i Register ...................................................................... 630

7-152. ELM_LOCATION_STATUS_i Register................................................................................ 630
7-153. ELM_ERROR_LOCATION_0-15_i Registers ........................................................................ 631
8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
8-25.
8-26.
8-27.
8-28.
8-29.
8-30.
8-31.
8-32.
8-33.
8-34.
8-35.
8-36.
8-37.
8-38.
8-39.
8-40.
8-41.
8-42.
8-43.
8-44.
8-45.
.......................................................................................
..................................................................................................
Clock Domain State Transitions .......................................................................................
Generic Power Domain Architecture ..................................................................................
High Level System View for RTC-only Mode ........................................................................
System Level View of Power Management of Cortex A8 MPU and Cortex M3 .................................
ADPLLS ...................................................................................................................
Basic Structure of the ADPLLLJ .......................................................................................
Core PLL ..................................................................................................................
Peripheral PLL Structure ................................................................................................
MPU Subsystem PLL Structure ........................................................................................
Display PLL Structure ...................................................................................................
DDR PLL Structure ......................................................................................................
CLKOUT Signals .........................................................................................................
Watchdog Timer Clock Selection ......................................................................................
Timer Clock Selection ...................................................................................................
RTC, VTP, and Debounce Clock Selection ..........................................................................
PORz ......................................................................................................................
External System Reset ..................................................................................................
nRESETIN_OUT Waveform as Warm Reset Source ...............................................................
nRESETIN_OUT Waveform Not as Warm Reset Source ..........................................................
CM_PER_L4LS_CLKSTCTRL Register ..............................................................................
CM_PER_L3S_CLKSTCTRL Register ................................................................................
CM_PER_L3_CLKSTCTRL Register ..................................................................................
CM_PER_CPGMAC0_CLKCTRL Register ...........................................................................
CM_PER_LCDC_CLKCTRL Register .................................................................................
CM_PER_USB0_CLKCTRL Register .................................................................................
CM_PER_TPTC0_CLKCTRL Register................................................................................
CM_PER_EMIF_CLKCTRL Register ..................................................................................
CM_PER_OCMCRAM_CLKCTRL Register ..........................................................................
CM_PER_GPMC_CLKCTRL Register ................................................................................
CM_PER_MCASP0_CLKCTRL Register .............................................................................
CM_PER_UART5_CLKCTRL Register ...............................................................................
CM_PER_MMC0_CLKCTRL Register ................................................................................
CM_PER_ELM_CLKCTRL Register...................................................................................
CM_PER_I2C2_CLKCTRL Register ..................................................................................
CM_PER_I2C1_CLKCTRL Register ..................................................................................
CM_PER_SPI0_CLKCTRL Register ..................................................................................
CM_PER_SPI1_CLKCTRL Register ..................................................................................
CM_PER_L4LS_CLKCTRL Register ..................................................................................
CM_PER_L4FW_CLKCTRL Register .................................................................................
CM_PER_MCASP1_CLKCTRL Register .............................................................................
Functional and Interface Clocks
633
Generic Clock Domain
638

List of Figures
638
640
643
645
650
652
654
657
659
660
661
662
662
663
664
666
667
668
669
679
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
21
www.ti.com
8-46.
8-47.
8-48.
8-49.
8-50.
8-51.
8-52.
8-53.
8-54.
8-55.
8-56.
8-57.
8-58.
CM_PER_TIMER7_CLKCTRL Register .............................................................................. 706

CM_PER_GPIO1_CLKCTRL Register ................................................................................ 710
CM_PER_TPCC_CLKCTRL Register ................................................................................. 713
CM_PER_DCAN0_CLKCTRL Register ............................................................................... 714

CM_PER_DCAN1_CLKCTRL Register ............................................................................... 715
CM_PER_EPWMSS1_CLKCTRL Register........................................................................... 716
8-59.
8-60.
CM_PER_L3_INSTR_CLKCTRL Register
8-61.
8-62.
8-63.
8-64.
8-65.
8-66.
8-67.
8-68.
...........................................................................
719
CM_PER_L3_CLKCTRL Register ..................................................................................... 720
CM_PER_IEEE5000_CLKCTRL Register ............................................................................ 721

CM_PER_PRU_ICSS_CLKCTRL Register........................................................................... 722
CM_PER_MMC1_CLKCTRL Register ................................................................................ 725
CM_PER_MMC2_CLKCTRL Register ................................................................................ 726
CM_PER_TPTC1_CLKCTRL Register................................................................................ 727
8-69.
CM_PER_TPTC2_CLKCTRL Register................................................................................ 728
8-70.
CM_PER_SPINLOCK_CLKCTRL Register
8-71.
8-72.
8-73.
8-74.
8-75.
8-76.
8-77.
8-78.
8-79.
8-80.
..........................................................................
729
CM_PER_MAILBOX0_CLKCTRL Register........................................................................... 730
CM_PER_L4HS_CLKSTCTRL Register .............................................................................. 731

CM_PER_L4HS_CLKCTRL Register
.................................................................................
732
CM_PER_OCPWP_L3_CLKSTCTRL Register ...................................................................... 733

CM_PER_OCPWP_CLKCTRL Register .............................................................................. 734
CM_PER_PRU_ICSS_CLKSTCTRL Register ....................................................................... 735
CM_PER_CPSW_CLKSTCTRL Register............................................................................. 736
CM_PER_LCDC_CLKSTCTRL Register ............................................................................. 737
CM_PER_CLKDIV32K_CLKCTRL Register.......................................................................... 738
CM_PER_CLK_24MHZ_CLKSTCTRL Register ..................................................................... 739
8-81.
CM_WKUP_CLKSTCTRL Register.................................................................................... 743
8-82.
CM_WKUP_CONTROL_CLKCTRL Register
8-83.
8-84.
8-85.
8-86.
8-87.
8-88.
8-89.
8-90.
8-91.
8-92.
8-93.
8-94.
22
CM_PER_UART4_CLKCTRL Register ............................................................................... 705
........................................................................
745
..........................................................................
CM_WKUP_TIMER0_CLKCTRL Register ............................................................................
CM_WKUP_DEBUGSS_CLKCTRL Register ........................................................................
CM_L3_AON_CLKSTCTRL Register .................................................................................
CM_AUTOIDLE_DPLL_MPU Register ................................................................................
CM_IDLEST_DPLL_MPU Register ....................................................................................
CM_SSC_DELTAMSTEP_DPLL_MPU Register ....................................................................
CM_SSC_MODFREQDIV_DPLL_MPU Register ....................................................................
CM_CLKSEL_DPLL_MPU Register ...................................................................................
CM_AUTOIDLE_DPLL_DDR Register ................................................................................
CM_IDLEST_DPLL_DDR Register ....................................................................................
747
CM_WKUP_GPIO0_CLKCTRL Register ............................................................................. 746

CM_WKUP_L4WKUP_CLKCTRL Register
List of Figures
748
749
750
751
752
753
754
755
756
757

www.ti.com
8-95.
8-96.
CM_SSC_DELTAMSTEP_DPLL_DDR Register .................................................................... 758
CM_SSC_MODFREQDIV_DPLL_DDR Register .................................................................... 759
8-97.
CM_CLKSEL_DPLL_DDR Register ................................................................................... 760
8-98.
CM_AUTOIDLE_DPLL_DISP Register
8-99.
8-100.
8-101.
8-102.
8-103.
8-104.
8-105.
8-106.
8-107.
8-108.
8-109.
8-110.
8-111.
8-112.
8-113.
8-114.
8-115.
8-116.
8-117.
8-118.
8-119.
8-120.
8-121.
8-122.
8-123.
8-124.
8-125.
8-126.
8-127.
8-128.
8-129.
8-130.
8-131.
8-132.
8-133.
8-134.
8-135.
8-136.
8-137.
8-138.
8-139.
8-140.
8-141.
8-142.
8-143.
...............................................................................
CM_IDLEST_DPLL_DISP Register ...................................................................................
CM_SSC_DELTAMSTEP_DPLL_DISP Register ....................................................................
CM_SSC_MODFREQDIV_DPLL_DISP Register....................................................................
CM_CLKSEL_DPLL_DISP Register...................................................................................
CM_AUTOIDLE_DPLL_CORE Register ..............................................................................
CM_IDLEST_DPLL_CORE Register ..................................................................................
CM_SSC_DELTAMSTEP_DPLL_CORE Register ..................................................................
CM_SSC_MODFREQDIV_DPLL_CORE Register ..................................................................
CM_CLKSEL_DPLL_CORE Register .................................................................................
CM_AUTOIDLE_DPLL_PER Register ................................................................................
CM_IDLEST_DPLL_PER Register ....................................................................................
CM_SSC_DELTAMSTEP_DPLL_PER Register.....................................................................
CM_SSC_MODFREQDIV_DPLL_PER Register ....................................................................
CM_CLKDCOLDO_DPLL_PER Register .............................................................................
CM_DIV_M4_DPLL_CORE Register ..................................................................................
CM_CLKMODE_DPLL_MPU Register ................................................................................
CM_CLKMODE_DPLL_PER Register ................................................................................
CM_CLKMODE_DPLL_CORE Register ..............................................................................
CM_CLKMODE_DPLL_DDR Register ................................................................................
CM_CLKMODE_DPLL_DISP Register................................................................................
CM_CLKSEL_DPLL_PERIPH Register ...............................................................................
CM_DIV_M2_DPLL_DDR Register....................................................................................
CM_DIV_M2_DPLL_DISP Register ...................................................................................
CM_DIV_M2_DPLL_MPU Register ...................................................................................
CM_DIV_M2_DPLL_PER Register ....................................................................................
CM_WKUP_WKUP_M3_CLKCTRL Register ........................................................................
CM_WKUP_UART0_CLKCTRL Register .............................................................................
CM_WKUP_I2C0_CLKCTRL Register ................................................................................
CM_WKUP_ADC_TSC_CLKCTRL Register .........................................................................
CM_WKUP_SMARTREFLEX0_CLKCTRL Register ................................................................
CM_WKUP_TIMER1_CLKCTRL Register ............................................................................
CM_WKUP_SMARTREFLEX1_CLKCTRL Register ................................................................
CM_L4_WKUP_AON_CLKSTCTRL Register ........................................................................
CM_WKUP_WDT1_CLKCTRL Register ..............................................................................
CLKSEL_TIMER7_CLK Register ......................................................................................
CM_MAC_CLKSEL Register ...........................................................................................
CM_CPTS_RFT_CLKSEL Register ...................................................................................
CLKSEL_TIMER1MS_CLK Register ..................................................................................

List of Figures
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
780
782
784
786
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
804
805
806
807
808
809
810
811
812
23
www.ti.com
8-144. CLKSEL_GFX_FCLK Register ......................................................................................... 813

8-145. CLKSEL_PRU_ICSS_OCP_CLK Register ........................................................................... 814
8-146. CLKSEL_LCDC_PIXEL_CLK Register................................................................................ 815
........................................................................................
CLKSEL_GPIO0_DBCLK Register ....................................................................................
CM_MPU_CLKSTCTRL Register ......................................................................................
CM_MPU_MPU_CLKCTRL Register ..................................................................................
CM_CLKOUT_CTRL Register .........................................................................................
CM_RTC_RTC_CLKCTRL Register...................................................................................
CM_RTC_CLKSTCTRL Register ......................................................................................
CM_GFX_L3_CLKSTCTRL Register ..................................................................................
CM_GFX_GFX_CLKCTRL Register...................................................................................
CM_GFX_L4LS_GFX_CLKSTCTRL Register .......................................................................
CM_GFX_MMUCFG_CLKCTRL Register ............................................................................
CM_GFX_MMUDATA_CLKCTRL Register ..........................................................................
CM_CEFUSE_CLKSTCTRL Register .................................................................................
CM_CEFUSE_CEFUSE_CLKCTRL Register ........................................................................
REVISION_PRM Register ..............................................................................................
PRM_IRQSTATUS_MPU Register ....................................................................................
PRM_IRQENABLE_MPU Register ....................................................................................
PRM_IRQSTATUS_M3 Register ......................................................................................
PRM_IRQENABLE_M3 Register ......................................................................................
RM_PER_RSTCTRL Register .........................................................................................
PM_PER_PWRSTST Register .........................................................................................
PM_PER_PWRSTCTRL Register .....................................................................................
RM_WKUP_RSTCTRL Register .......................................................................................
PM_WKUP_PWRSTCTRL Register ...................................................................................
PM_WKUP_PWRSTST Register ......................................................................................
RM_WKUP_RSTST Register ..........................................................................................
PM_MPU_PWRSTCTRL Register .....................................................................................
PM_MPU_PWRSTST Register ........................................................................................
RM_MPU_RSTST Register.............................................................................................
PRM_RSTCTRL Register ...............................................................................................
PRM_RSTTIME Register ...............................................................................................
PRM_RSTST Register ..................................................................................................
PRM_SRAM_COUNT Register ........................................................................................
PRM_LDO_SRAM_CORE_SETUP Register ........................................................................
PRM_LDO_SRAM_CORE_CTRL Register ..........................................................................
PRM_LDO_SRAM_MPU_SETUP Register ..........................................................................
PRM_LDO_SRAM_MPU_CTRL Register ............................................................................
PM_RTC_PWRSTCTRL Register .....................................................................................
PM_RTC_PWRSTST Register .........................................................................................
PM_GFX_PWRSTCTRL Register .....................................................................................
RM_GFX_RSTCTRL Register .........................................................................................
PM_GFX_PWRSTST Register .........................................................................................
RM_GFX_RSTST Register .............................................................................................
PM_CEFUSE_PWRSTCTRL Register ................................................................................
PM_CEFUSE_PWRSTST Register ...................................................................................
Event Crossbar ...........................................................................................................
8-147. CLKSEL_WDT1_CLK Register

8-148.
8-149.
8-150.
8-151.
8-152.
8-153.
8-154.
8-155.
8-156.
8-157.
8-158.
8-159.
8-160.
8-161.
8-162.
8-163.
8-164.
8-165.
8-166.
8-167.
8-168.
8-169.
8-170.
8-171.
8-172.
8-173.
8-174.
8-175.
8-176.
8-177.
8-178.
8-179.
8-180.
8-181.
8-182.
8-183.
8-184.
8-185.
8-186.
8-187.
8-188.
8-189.
8-190.
8-191.
9-1.
24
List of Figures
816
817
818
819
821
823
824
826
827
828
829
830
832
833
835
836
837
838
839
841
842
843
845
846
847
848
850
852
853
855
856
857
858
859
861
862
864
866
867
869
870
871
872
873
874
878

www.ti.com
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
USB Charger Detection ................................................................................................. 880
Timer Events.............................................................................................................. 883
control_revision Register ................................................................................................ 892
device_id Register ....................................................................................................... 893

control_hwinfo Register ................................................................................................. 894
control_sysconfig Register .............................................................................................. 895
control_status Register .................................................................................................. 896
cortex_vbbldo_ctrl Register ............................................................................................. 897

core_sldo_ctrl Register .................................................................................................. 898
mpu_sldo_ctrl Register .................................................................................................. 899
clk32kdivratio_ctrl Register ............................................................................................. 900
bandgap_ctrl Register ................................................................................................... 901
bandgap_trim Register .................................................................................................. 902

pll_clkinpulow_ctrl Register ............................................................................................. 903
mosc_ctrl Register ....................................................................................................... 904
rcosc_ctrl Register ....................................................................................................... 905
9-18.
deepsleep_ctrl Register ................................................................................................. 906
9-19.
dev_feature Register
9-20.
9-21.
9-22.
9-23.
9-24.
9-25.
9-26.
9-27.
9-28.
9-29.
9-30.
9-31.
....................................................................................................
907
init_priority_0 Register................................................................................................... 908
init_priority_1 Register................................................................................................... 909

mmu_cfg Register........................................................................................................ 910
tptc_cfg Register ......................................................................................................... 911
usb_ctrl0 Register ........................................................................................................ 912

usb_sts0 Register ........................................................................................................ 914
usb_ctrl1 Register ........................................................................................................ 915
usb_sts1 Register ........................................................................................................ 917
mac_id0_lo Register ..................................................................................................... 918
mac_id0_hi Register ..................................................................................................... 919
mac_id1_lo Register ..................................................................................................... 920
mac_id1_hi Register ..................................................................................................... 921
9-32.
dcan_raminit Register ................................................................................................... 922
9-33.
usb_wkup_ctrl Register
9-34.
9-35.
9-36.
9-37.
9-38.
9-39.
9-40.
9-41.
9-42.
9-43.
9-44.
9-45.
9-46.
9-47.
9-48.
9-49.
9-50.
.................................................................................................
923
gmii_sel Register ......................................................................................................... 924
pwmss_ctrl Register ..................................................................................................... 925

mreqprio_0 Register ..................................................................................................... 926
mreqprio_1 Register ..................................................................................................... 927
hw_event_sel_grp1 Register ........................................................................................... 928
smrt_ctrl Register ........................................................................................................ 932

mpuss_hw_debug_sel Register ........................................................................................ 933
mpuss_hw_dbg_info Register .......................................................................................... 934

vdd_mpu_opp_050 Register............................................................................................ 935
vdd_mpu_opp_turbo Register .......................................................................................... 938
vdd_core_opp_050 Register............................................................................................ 939

vdd_core_opp_100 Register............................................................................................ 940

List of Figures
25
www.ti.com
9-51.
9-52.
9-53.
9-54.
9-55.
9-56.
9-57.
9-58.
usb_vid_pid Register .................................................................................................... 942

conf_<module>_<pin> Register ........................................................................................ 943
cqdetect_status Register ................................................................................................ 944
ddr_io_ctrl Register ...................................................................................................... 945
vtp_ctrl Register .......................................................................................................... 946

vref_ctrl Register ......................................................................................................... 947
tpcc_evt_mux_0_3 Register ............................................................................................ 948
9-59.
tpcc_evt_mux_4_7 Register ............................................................................................ 949
9-60.
tpcc_evt_mux_8_11 Register
9-61.
9-62.
9-63.
9-64.
9-65.
9-66.
9-67.
9-68.
9-69.
9-70.
9-71.
9-72.
9-73.
9-74.
9-75.
9-76.
9-77.
9-78.
9-79.
9-80.
9-81.
9-82.
9-83.
9-84.
9-85.
9-86.
9-87.
..........................................................................................
950
tpcc_evt_mux_12_15 Register ......................................................................................... 951

timer_evt_capt Register ................................................................................................. 964
ecap_evt_capt Register ................................................................................................. 965

adc_evt_capt Register................................................................................................... 966
reset_iso Register ........................................................................................................ 967

ddr_cke_ctrl Register .................................................................................................... 968
sma2 Register ............................................................................................................ 969
m3_txev_eoi Register ................................................................................................... 970
ipc_msg_reg0 Register .................................................................................................. 971

9-88.
9-89.
ddr_cmd0_ioctrl Register
9-90.
9-91.
9-92.
9-93.
10-1.
10-2.
11-1.
11-2.
11-3.
11-4.
26
bb_scale Register ........................................................................................................ 941
...............................................................................................
ddr_cmd1_ioctrl Register ...............................................................................................
ddr_cmd2_ioctrl Register ...............................................................................................
ddr_data0_ioctrl Register ...............................................................................................
ddr_data1_ioctrl Register ...............................................................................................
L3 Topology...............................................................................................................
L4 Topology...............................................................................................................
EDMA3 Controller Block Diagram .....................................................................................
TPCC Integration.........................................................................................................
TPTC Integration .......................................................................................................
EDMA3 Channel Controller (EDMA3CC) Block Diagram .........................................................
List of Figures
979
981
983
985
987
991
994
996
999
1000
1003

www.ti.com
11-5.
11-6.
11-7.
11-8.
11-9.
11-10.
11-11.
11-12.
11-13.
11-14.
11-15.
11-16.
11-17.
11-18.
11-19.
11-20.
11-21.
11-22.
11-23.
11-24.
11-25.
11-26.
11-27.
11-28.
11-29.
11-30.
11-31.
11-32.
11-33.
11-34.
11-35.
11-36.
11-37.
11-38.
11-39.
11-40.
11-41.
11-42.
11-43.
11-44.
11-45.
11-46.
11-47.
11-48.
11-49.
11-50.
11-51.
11-52.
11-53.
.........................................................
Definition of ACNT, BCNT, and CCNT .............................................................................
A-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) ...................................................
AB-Synchronized Transfers (ACNT = n, BCNT = 4, CCNT = 3) .................................................
PaRAM Set ..............................................................................................................
Channel Options Parameter (OPT) ..................................................................................
Linked Transfer .........................................................................................................
Link-to-Self Transfer ...................................................................................................
DMA Channel and QDMA Channel to PaRAM Mapping ..........................................................
QDMA Channel to PaRAM Mapping .................................................................................
Shadow Region Registers .............................................................................................
Interrupt Diagram .......................................................................................................
Error Interrupt Operation ..............................................................................................
PaRAM Set Content for Proxy Memory Protection Example .....................................................
Channel Options Parameter (OPT) Example .......................................................................
Proxy Memory Protection Example ..................................................................................
EDMA3 Prioritization ...................................................................................................
Block Move Example ...................................................................................................
Block Move Example PaRAM Configuration ........................................................................
Subframe Extraction Example ........................................................................................
Subframe Extraction Example PaRAM Configuration .............................................................
Data Sorting Example ..................................................................................................
Data Sorting Example PaRAM Configuration .......................................................................
Servicing Incoming McASP Data Example .........................................................................
Servicing Incoming McASP Data Example PaRAM Configuration...............................................
Servicing Peripheral Burst Example .................................................................................
Servicing Peripheral Burst Example PaRAM Configuration ......................................................
Servicing Continuous McASP Data Example .......................................................................
Servicing Continuous McASP Data Example PaRAM Configuration ............................................
Servicing Continuous McASP Data Example Reload PaRAM Configuration ..................................
Ping-Pong Buffering for McASP Data Example ...................................................................
Ping-Pong Buffering for McASP Example PaRAM Configuration ................................................
Ping-Pong Buffering for McASP Example Pong PaRAM Configuration .........................................
Ping-Pong Buffering for McASP Example Ping PaRAM Configuration..........................................
Intermediate Transfer Completion Chaining Example .............................................................
Single Large Block Transfer Example ...............................................................................
Smaller Packet Data Transfers Example ............................................................................
Peripheral ID Register (PID) ..........................................................................................
EDMA3CC Configuration Register (CCCFG) .......................................................................
EDMA3CC System Configuration Register (SYSCONFIG) .......................................................
DMA Channel Map n Registers (DCHMAPn) .......................................................................
QDMA Channel Map n Registers (QCHMAPn) ....................................................................
DMA Channel Queue n Number Registers (DMAQNUMn) .......................................................
QDMA Channel Queue Number Register (QDMAQNUM) ........................................................
Queue Priority Register (QUEPRI) ...................................................................................
Event Missed Register (EMR) ........................................................................................
Event Missed Register High (EMRH) ................................................................................
Event Missed Clear Register (EMCR) ...............................................................................
Event Missed Clear Register High (EMCRH) .......................................................................
EDMA3 Transfer Controller (EDMA3TC) Block Diagram

List of Figures
1004
1005
1006
1007
1009
1011
1018
1019
1024
1025
1026
1030
1033
1037
1037
1038
1045
1046
1046
1047
1047
1048
1049
1050
1050
1051
1052
1053
1054
1055
1057
1057
1058
1059
1060
1061
1061
1068
1069
1071
1072
1073
1074
1075
1076
1077
1077
1078
1078
27
www.ti.com
11-54. QDMA Event Missed Register (QEMR) ............................................................................. 1079
11-55. QDMA Event Missed Clear Register (QEMCR) .................................................................... 1080
11-56. EDMA3CC Error Register (CCERR) ................................................................................. 1080

11-57. EDMA3CC Error Clear Register (CCERRCLR) .................................................................... 1081
..................................................................................
..................................................
11-60. DMA Region Access Enable High Register for Region m (DRAEHm) ..........................................
11-61. QDMA Region Access Enable for Region m (QRAEm)32-bit, 2 Rows..........................................
11-62. Event Queue Entry Registers (QxEy) ................................................................................
11-63. Queue Status Register n (QSTATn) .................................................................................
11-64. Queue Watermark Threshold A Register (QWMTHRA) ...........................................................
11-65. EDMA3CC Status Register (CCSTAT) ..............................................................................
11-66. Memory Protection Fault Address Register (MPFAR) .............................................................
11-67. Memory Protection Fault Status Register (MPFSR) ...............................................................
11-68. Memory Protection Fault Command Register (MPFCR) ..........................................................
11-69. Memory Protection Page Attribute Register (MPPAn) .............................................................
11-70. Event Register (ER) ....................................................................................................
11-71. Event Register High (ERH)............................................................................................
11-72. Event Clear Register (ECR) ...........................................................................................
11-73. Event Clear Register High (ECRH) ..................................................................................
11-74. Event Set Register (ESR) .............................................................................................
11-75. Event Set Register High (ESRH) .....................................................................................
11-76. Chained Event Register (CER) .......................................................................................
11-77. Chained Event Register High (CERH) ...............................................................................
11-78. Event Enable Register (EER) .........................................................................................
11-79. Event Enable Register High (EERH).................................................................................
11-80. Event Enable Clear Register (EECR) ................................................................................
11-81. Event Enable Clear Register High (EECRH) .......................................................................
11-82. Event Enable Set Register (EESR) ..................................................................................
11-83. Event Enable Set Register High (EESRH) ..........................................................................
11-84. Secondary Event Register (SER) ....................................................................................
11-85. Secondary Event Register High (SERH) ............................................................................
11-86. Secondary Event Clear Register (SECR) ...........................................................................
11-87. Secondary Event Clear Register High (SECRH) ...................................................................
11-88. Interrupt Enable Register (IER) .......................................................................................
11-89. Interrupt Enable Register High (IERH) ..............................................................................
11-90. Interrupt Enable Clear Register (IECR)..............................................................................
11-91. Interrupt Enable Clear Register High (IECRH) .....................................................................
11-92. Interrupt Enable Set Register (IESR) ................................................................................
11-93. Interrupt Enable Set Register High (IESRH) ........................................................................
11-94. Interrupt Pending Register (IPR) .....................................................................................
11-95. Interrupt Pending Register High (IPRH) .............................................................................
11-96. Interrupt Clear Register (ICR).........................................................................................
11-97. Interrupt Clear Register High (ICRH) ................................................................................
11-98. Interrupt Evaluate Register (IEVAL) .................................................................................
11-99. QDMA Event Register (QER) .........................................................................................
11-100. QDMA Event Enable Register (QEER) ............................................................................
11-101. QDMA Event Enable Clear Register (QEECR) ...................................................................
11-102. QDMA Event Enable Set Register (QEESR) ......................................................................
28
11-58. Error Evaluation Register (EEVAL)
1083
11-59. DMA Region Access Enable Register for Region m (DRAEm)
1084
List of Figures
1084
1085
1086
1087
1088
1089
1091
1092
1093
1094
1096
1096
1097
1097
1098
1099
1100
1100
1102
1102
1103
1103
1104
1104
1105
1105
1106
1106
1107
1107
1108
1108
1109
1109
1110
1110
1111
1111
1112
1113
1114
1115
1116

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11-103. QDMA Secondary Event Register (QSER) ........................................................................ 1117

11-104. QDMA Secondary Event Clear Register (QSECR) ............................................................... 1118
11-105. Peripheral ID Register (PID) ......................................................................................... 1120

11-106. EDMA3TC Configuration Register (TCCFG) ...................................................................... 1121
..................................................................
1122
....................................................................................
1125
11-107. EDMA3TC Channel Status Register (TCSTAT)
11-108. Error Register (ERRSTAT)........................................................................................... 1124

11-109. Error Enable Register (ERREN)
11-110. Error Clear Register (ERRCLR) ..................................................................................... 1126

11-111. Error Details Register (ERRDET) ................................................................................... 1127
11-112. Error Interrupt Command Register (ERRCMD) ................................................................... 1128

11-113. Read Rate Register (RDRATE) ..................................................................................... 1129
11-114. Source Active Options Register (SAOPT) ......................................................................... 1130
11-115. Source Active Source Address Register (SASRC) ............................................................... 1132
11-116. Source Active Count Register (SACNT) ........................................................................... 1132

11-117. Source Active Destination Address Register (SADST)
..........................................................
1133
11-118. Source Active Source B-Dimension Index Register (SABIDX).................................................. 1133

11-119. Source Active Memory Protection Proxy Register (SAMPPRXY) .............................................. 1134
11-120. Source Active Count Reload Register (SACNTRLD)............................................................. 1135
11-121. Source Active Source Address B-Reference Register (SASRCBREF) ........................................ 1135
11-122. Source Active Destination Address B-Reference Register (SADSTBREF) ................................... 1136
11-123. Destination FIFO Options Register (DFOPTn) .................................................................... 1137
11-124. Destination FIFO Source Address Register (DFSRCn) .......................................................... 1139
11-125. Destination FIFO Count Register (DFCNTn) ...................................................................... 1139
11-126. Destination FIFO Destination Address Register (DFDSTn) ..................................................... 1140
11-127. Destination FIFO B-Index Register (DFBIDXn) ................................................................... 1140

11-128. Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) ......................................... 1141
11-129. Destination FIFO Count Reload Register (DFCNTRLDn) ....................................................... 1142

11-130. Destination FIFO Source Address B-Reference Register (DFSRCBREFn) ................................... 1142
11-131. Destination FIFO Destination Address B-Reference Register (DFDSTBREFn) .............................. 1143
12-1.
TSC_ADC Integration .................................................................................................. 1149
12-2.
Functional Block Diagram ............................................................................................. 1152
12-3.
Sequencer FSM
12-4.
12-5.
12-6.
12-7.
12-8.
12-9.
........................................................................................................
1155
Example Timing Diagram for Sequencer ............................................................................ 1156
REVISION Register .................................................................................................... 1159
SYSCONFIG Register ................................................................................................. 1160
IRQSTATUS_RAW Register .......................................................................................... 1161

IRQSTATUS Register .................................................................................................. 1163
IRQENABLE_SET Register ........................................................................................... 1165
12-10. IRQENABLE_CLR Register ........................................................................................... 1167

12-11. IRQWAKEUP Register ................................................................................................. 1169
12-12. DMAENABLE_SET Register .......................................................................................... 1170

12-13. DMAENABLE_CLR Register.......................................................................................... 1171
12-14. CTRL Register .......................................................................................................... 1172
12-15. ADCSTAT Register..................................................................................................... 1173
12-16. ADCRANGE Register .................................................................................................. 1174
12-17. ADC_CLKDIV Register ................................................................................................ 1175

12-18. ADC_MISC Register ................................................................................................... 1176
12-19. STEPENABLE Register
...............................................................................................
1177
12-20. IDLECONFIG Register ................................................................................................. 1178

List of Figures
29
www.ti.com
12-21. TS_CHARGE_STEPCONFIG Register.............................................................................. 1179
12-22. TS_CHARGE_DELAY Register ...................................................................................... 1180
12-23. STEPCONFIG1 Register .............................................................................................. 1181

12-24. STEPDELAY1 Register ................................................................................................ 1182
12-41. STEPCONFIG10 Register............................................................................................. 1199

12-42. STEPDELAY10 Register .............................................................................................. 1200






12-55. FIFO0COUNT Register ................................................................................................ 1213

12-56. FIFO0THRESHOLD Register ......................................................................................... 1214
12-57. DMA0REQ Register .................................................................................................... 1215
12-58. FIFO1COUNT Register ................................................................................................ 1216

12-59. FIFO1THRESHOLD Register ......................................................................................... 1217
12-60. DMA1REQ Register .................................................................................................... 1218
12-61. FIFO0DATA Register .................................................................................................. 1219

12-62. FIFO1DATA Register .................................................................................................. 1220
13-1.
13-2.
13-3.
13-4.
13-5.
30
LCD Controller .......................................................................................................... 1222
LCD Controller Integration............................................................................................. 1224

Input and Output Clocks ............................................................................................... 1226
Logical Data Path for Raster Controller ............................................................................. 1233
Frame Buffer Structure
................................................................................................
1234
...........................................................................
1236
13-6.
16-Entry Palette/Buffer Format (1, 2, 4, 12, 16 BPP) .............................................................. 1235
13-7.
256-Entry Palette/Buffer Format (8 BPP)
List of Figures

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13-8.
13-9.
13-10.
13-11.
13-12.
13-13.
13-14.
13-15.
13-16.
13-17.
13-18.
13-19.
13-20.
13-21.
13-22.
13-23.
13-24.
13-25.
13-26.
13-27.
13-28.
13-29.
13-30.
13-31.
13-32.
13-33.
13-34.
13-35.
13-36.
13-37.
13-38.
13-39.
13-40.
13-41.
13-42.
13-43.
13-44.
13-45.
14-1.
14-2.
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
..........................................
12-BPP Data Memory OrganizationLittle Endian ................................................................
8-BPP Data Memory Organization ..................................................................................
4-BPP Data Memory Organization ...................................................................................
Monochrome and Color Output .......................................................................................
Example of Subpicture .................................................................................................
Subpicture HOLS Bit ...................................................................................................
Raster Mode Display Format .........................................................................................
Palette Lookup Examples .............................................................................................
PID Register .............................................................................................................
CTRL Register ..........................................................................................................
LIDD_CTRL Register ..................................................................................................
LIDD_CS0_CONF Register ...........................................................................................
LIDD_CS0_ADDR Register ...........................................................................................
LIDD_CS0_DATA Register............................................................................................
LIDD_CS1_CONF Register ...........................................................................................
LIDD_CS1_ADDR Register ...........................................................................................
LIDD_CS1_DATA Register............................................................................................
RASTER_CTRL Register ..............................................................................................
RASTER_TIMING_0 Register ........................................................................................
RASTER_SUBPANEL Register ......................................................................................
RASTER_SUBPANEL2 Register .....................................................................................
LCDDMA_CTRL Register .............................................................................................
LCDDMA_FB0_BASE Register.......................................................................................
LCDDMA_FB0_CEILING Register ...................................................................................
LCDDMA_FB1_BASE Register.......................................................................................
LCDDMA_FB1_CEILING Register ...................................................................................
SYSCONFIG Register .................................................................................................
IRQSTATUS_RAW Register ..........................................................................................
IRQSTATUS Register ..................................................................................................
IRQENABLE_SET Register ...........................................................................................
IRQENABLE_CLEAR Register .......................................................................................
CLKC_ENABLE Register ..............................................................................................
CLKC_RESET Register ...............................................................................................
Ethernet Switch Integration ...........................................................................................
Ethernet Switch RMII Clock Detail ...................................................................................
MII Interface Connections .............................................................................................
RMII Interface Connections ...........................................................................................
RGMII Interface Connections .........................................................................................
CPSW_3G Block Diagram ............................................................................................
Tx Buffer Descriptor Format ..........................................................................................
Rx Buffer Descriptor Format ..........................................................................................
VLAN Header Encapsulation Word ..................................................................................
CPTS Block Diagram ..................................................................................................
Event FIFO Misalignment Condition .................................................................................
16-BPP Data Memory Organization (TFT Mode Only)Little Endian

List of Figures
1236
1237
1237
1237
1238
1238
1240
1241
1241
1242
1250
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1266
1267
1268
1270
1271
1272
1274
1275
1276
1277
1278
1280
1282
1284
1286
1288
1289
1293
1297
1298
1300
1301
1309
1314
1317
1321
1356
1358
31
www.ti.com
14-12. HW1/4_TSP_PUSH Connection...................................................................................... 1359
14-13. Port TX State RAM Entry .............................................................................................. 1364
14-14. Port RX DMA State..................................................................................................... 1365

14-15. IDVER Register ......................................................................................................... 1369
14-16. CONTROL Register .................................................................................................... 1370

14-17. PRESCALE Register ................................................................................................... 1372
14-18. UNKNOWN_VLAN Register
..........................................................................................
1373
14-19. TBLCTL Register ....................................................................................................... 1374

14-20. TBLW2 Register ........................................................................................................ 1375
14-21. TBLW1 Register ........................................................................................................ 1376
14-22. TBLW0 Register ........................................................................................................ 1377
14-23. PORTCTL0 Register ................................................................................................... 1378
14-29. TX_IDVER Register .................................................................................................... 1386
14-30. TX_CONTROL Register ............................................................................................... 1387
14-31. TX_TEARDOWN Register
............................................................................................
1388
14-32. RX_IDVER Register .................................................................................................... 1389

14-33. RX_CONTROL Register ............................................................................................... 1390
14-34. RX_TEARDOWN Register ............................................................................................ 1391
14-35. CPDMA_SOFT_RESET Register .................................................................................... 1392
14-36. DMACONTROL Register .............................................................................................. 1393
1395
14-38.
1397
14-39.
14-40.
14-41.
14-42.
14-43.
14-44.
14-45.
14-46.
14-47.
14-48.
14-49.
14-50.
14-51.
14-52.
14-53.
14-54.
14-55.
14-56.
14-57.
14-58.
14-59.
14-60.
32
................................................................................................
RX_BUFFER_OFFSET Register .....................................................................................
EMCONTROL Register ................................................................................................
TX_PRI0_RATE Register .............................................................................................
TX_INTSTAT_RAW Register .........................................................................................
TX_INTSTAT_MASKED Register ....................................................................................
TX_INTMASK_SET Register .........................................................................................
TX_INTMASK_CLEAR Register ......................................................................................
CPDMA_IN_VECTOR Register ......................................................................................
CPDMA_EOI_VECTOR Register ....................................................................................
RX_INTSTAT_RAW Register .........................................................................................
RX_INTSTAT_MASKED Register ....................................................................................
RX_INTMASK_SET Register .........................................................................................
RX_INTMASK_CLEAR Register .....................................................................................
DMA_INTSTAT_RAW Register.......................................................................................
DMA_INTSTAT_MASKED Register .................................................................................
DMA_INTMASK_SET Register .......................................................................................
14-37. DMASTATUS Register
List of Figures
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419

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14-61. DMA_INTMASK_CLEAR Register ................................................................................... 1420

14-62. RX0_PENDTHRESH Register ........................................................................................ 1421
........................................................................................
........................................................................................
14-72. RX2_FREEBUFFER Register ........................................................................................
14-78. CPTS_IDVER Register ................................................................................................
14-79. CPTS_CONTROL Register ...........................................................................................
14-80. CPTS_TS_PUSH Register ............................................................................................
14-81. CPTS_TS_LOAD_VAL Register......................................................................................
14-82. CPTS_TS_LOAD_EN Register .......................................................................................
14-83. CPTS_INTSTAT_RAW Register .....................................................................................
14-84. CPTS_INTSTAT_MASKED Register ................................................................................
14-85. CPTS_INT_ENABLE Register ........................................................................................
14-86. CPTS_EVENT_POP Register ........................................................................................
14-87. CPTS_EVENT_LOW Register ........................................................................................
14-88. CPTS_EVENT_HIGH Register .......................................................................................
14-89. TX0_HDP Register .....................................................................................................
14-90. TX1_HDP Register .....................................................................................................
14-91. TX2_HDP Register .....................................................................................................
14-92. TX3_HDP Register .....................................................................................................
14-93. TX4_HDP Register .....................................................................................................
14-94. TX5_HDP Register .....................................................................................................
14-95. TX6_HDP Register .....................................................................................................
14-96. TX7_HDP Register .....................................................................................................
14-97. RX0_HDP Register .....................................................................................................
14-98. RX1_HDP Register .....................................................................................................
14-99. RX2_HDP Register .....................................................................................................
14-100. RX3_HDP Register ...................................................................................................
14-101. RX4_HDP Register ...................................................................................................
14-102. RX5_HDP Register ...................................................................................................
14-103. RX6_HDP Register ...................................................................................................
14-104. RX7_HDP Register ...................................................................................................
14-105. TX0_CP Register......................................................................................................
14-106. TX1_CP Register......................................................................................................
14-107. TX2_CP Register......................................................................................................
14-108. TX3_CP Register......................................................................................................
14-109. TX4_CP Register......................................................................................................
14-70. RX0_FREEBUFFER Register
1429
14-71. RX1_FREEBUFFER Register
1430

List of Figures
1431
1432
1433
1434
1435
1436
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
33
www.ti.com
14-110. TX5_CP Register...................................................................................................... 1473

14-111. TX6_CP Register...................................................................................................... 1474
14-112. TX7_CP Register...................................................................................................... 1475
14-113. RX0_CP Register ..................................................................................................... 1476

14-114. RX1_CP Register ..................................................................................................... 1477
14-115. RX2_CP Register ..................................................................................................... 1478
14-116. RX3_CP Register ..................................................................................................... 1479
14-117. RX4_CP Register ..................................................................................................... 1480
14-118. RX5_CP Register ..................................................................................................... 1481
14-119. RX6_CP Register ..................................................................................................... 1482
14-120. RX7_CP Register ..................................................................................................... 1483
14-121. P0_CONTROL Register .............................................................................................. 1486
14-122. P0_MAX_BLKS Register ............................................................................................. 1487
14-123. P0_BLK_CNT Register ............................................................................................... 1488

14-124. P0_TX_IN_CTL Register ............................................................................................. 1489
14-125. P0_PORT_VLAN Register ........................................................................................... 1490
14-126. P0_TX_PRI_MAP Register .......................................................................................... 1491

14-127. P0_CPDMA_TX_PRI_MAP Register ............................................................................... 1492
14-128. P0_CPDMA_RX_CH_MAP Register ............................................................................... 1493
1494
14-130. P0_RX_DSCP_PRI_MAP1 Register
1495
14-131.
1496
14-132.
14-133.
14-134.
14-135.
14-136.
14-137.
14-138.
14-139.
14-140.
14-141.
14-142.
14-143.
14-144.
14-145.
14-146.
14-147.
14-148.
14-149.
14-150.
14-151.
14-152.
14-153.
14-154.
14-155.
14-156.
14-157.
14-158.
34
...............................................................................
...............................................................................
P0_RX_DSCP_PRI_MAP2 Register ...............................................................................
P1_CONTROL Register ..............................................................................................
P1_MAX_BLKS Register .............................................................................................
P1_BLK_CNT Register ...............................................................................................
P1_TX_IN_CTL Register .............................................................................................
P1_PORT_VLAN Register ...........................................................................................
P1_TX_PRI_MAP Register ..........................................................................................
P1_TS_SEQ_MTYPE Register .....................................................................................
P1_SA_LO Register ..................................................................................................
P1_SA_HI Register ...................................................................................................
P1_SEND_PERCENT Register .....................................................................................
P2_CONTROL Register ..............................................................................................
P2_MAX_BLKS Register .............................................................................................
P2_BLK_CNT Register ...............................................................................................
P2_TX_IN_CTL Register .............................................................................................
List of Figures
1497
1498
1499
1500
1501
1502
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1523
1524
1525

www.ti.com
14-159. P2_PORT_VLAN Register ........................................................................................... 1526
14-160. P2_TX_PRI_MAP Register .......................................................................................... 1527

14-161. P2_TS_SEQ_MTYPE Register
.....................................................................................
1528
14-162. P2_SA_LO Register .................................................................................................. 1529

14-163. P2_SA_HI Register ................................................................................................... 1530
14-164. P2_SEND_PERCENT Register ..................................................................................... 1531
...............................................................................
...............................................................................
IDVER Register .......................................................................................................
MACCONTROL Register.............................................................................................
MACSTATUS Register ...............................................................................................
SOFT_RESET Register ..............................................................................................
RX_MAXLEN Register ...............................................................................................
BOFFTEST Register ..................................................................................................
RX_PAUSE Register .................................................................................................
TX_PAUSE Register ..................................................................................................
EMCONTROL Register ..............................................................................................
RX_PRI_MAP Register ...............................................................................................
TX_GAP Register .....................................................................................................
ID_VER Register ......................................................................................................
CONTROL Register...................................................................................................
STAT_PORT_EN Register...........................................................................................
PTYPE Register .......................................................................................................
SOFT_IDLE Register .................................................................................................
THRU_RATE Register................................................................................................
GAP_THRESH Register .............................................................................................
TX_START_WDS Register ..........................................................................................
FLOW_CONTROL Register .........................................................................................
VLAN_LTYPE Register ...............................................................................................
TS_LTYPE Register ..................................................................................................
DLR_LTYPE Register ................................................................................................
IDVER Register .......................................................................................................
CONTROL Register...................................................................................................
INT_CONTROL Register .............................................................................................
C0_RX_THRESH_EN Register .....................................................................................
C0_RX_EN Register ..................................................................................................
C0_TX_EN Register ..................................................................................................
C0_MISC_EN Register ...............................................................................................
C1_RX_THRESH_EN Register .....................................................................................
C1_RX_EN Register ..................................................................................................
C1_TX_EN Register ..................................................................................................
1532
1533
14-167.
1534
14-168.
14-169.
14-170.
14-171.
14-172.
14-173.
14-174.
14-175.
14-176.
14-177.
14-178.
14-179.
14-180.
14-181.
14-182.
14-183.
14-184.
14-185.
14-186.
14-187.
14-188.
14-189.
14-190.
14-191.
14-192.
14-193.
14-194.
14-195.
14-196.
14-197.
14-198.
14-199.
14-200.
14-201.
14-202.
14-203.
14-204.
14-205.
14-206.
14-207.

List of Figures
1535
1536
1537
1538
1539
1541
1542
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
35
www.ti.com
14-208. C1_MISC_EN Register ............................................................................................... 1579
14-209. C2_RX_THRESH_EN Register ..................................................................................... 1580

14-210. C2_RX_EN Register .................................................................................................. 1581
14-211. C2_TX_EN Register .................................................................................................. 1582
14-212. C2_MISC_EN Register ............................................................................................... 1583
14-213. C0_RX_THRESH_STAT Register .................................................................................. 1584

14-214. C0_RX_STAT Register ............................................................................................... 1585
14-215. C0_TX_STAT Register ............................................................................................... 1586
14-216. C0_MISC_STAT Register ............................................................................................ 1587


14-225. C0_RX_IMAX Register ............................................................................................... 1596

14-226. C0_TX_IMAX Register ............................................................................................... 1597
.................................................................................................
14-232. MDIO Version Register (MDIOVER)................................................................................
14-233. MDIO Control Register (MDIOCONTROL) ........................................................................
14-234. PHY Acknowledge Status Register (MDIOALIVE)................................................................
14-235. PHY Link Status Register (MDIOLINK) ............................................................................
14-236. MDIO Link Status Change Interrupt Register (MDIOLINKINTRAW) ...........................................
14-237. MDIO Link Status Change Interrupt Register (Masked Value) (MDIOLINKINTMASKED) ..................
14-238. MDIO User Command Complete Interrupt Register (Raw Value) (MDIOUSERINTRAW) ..................
14-239. MDIO User Command Complete Interrupt Register (Masked Value) (MDIOUSERINTMASKED) .........
14-240. MDIO User Command Complete Interrupt Mask Set Register (MDIOUSERINTMASKSET) ...............
14-241. MDIO User Command Complete Interrupt Mask Clear Register (MDIOUSERINTMASKCLR) .............
14-242. MDIO User Access Register 0 (MDIOUSERACCESS0) .........................................................
14-243. MDIO User PHY Select Register 0 (MDIOUSERPHYSEL0) ....................................................
14-244. MDIO User Access Register 1 (MDIOUSERACCESS1) .........................................................
14-245. MDIO User PHY Select Register 1 (MDIOUSERPHYSEL1) ....................................................
15-1. PWMSS Integration ....................................................................................................
15-2. IP Revision Register (IDVER).........................................................................................
15-3. System Configuration Register (SYSCONFIG) .....................................................................
15-4. Clock Configuration Register (CLKCONFG) ........................................................................
15-5. Clock Status Register (CLKSTATUS) ...............................................................................
15-6. Multiple ePWM Modules ...............................................................................................
15-7. Submodules and Signal Connections for an ePWM Module .....................................................
15-8. ePWM Submodules and Critical Internal Signal Interconnects...................................................
15-9. Time-Base Submodule Block Diagram ..............................................................................
15-10. Time-Base Submodule Signals and Registers .....................................................................
15-11. Time-Base Frequency and Period ...................................................................................
14-231. RGMII_CTL Register
36
List of Figures
1602
1603
1604
1605
1605
1606
1606
1607
1607
1608
1608
1609
1610
1611
1612
1616
1619
1620
1621
1622
1624
1625
1626
1630
1632
1634

www.ti.com
...................................................................
Time-Base Up-Count Mode Waveforms.............................................................................
Time-Base Down-Count Mode Waveforms .........................................................................
Time-Base Up-Down-Count Waveforms, TBCTL[PHSDIR = 0] Count Down on Synchronization Event ...
Time-Base Up-Down Count Waveforms, TBCTL[PHSDIR = 1] Count Up on Synchronization Event ......
Counter-Compare Submodule ........................................................................................
Counter-Compare Submodule Signals and Registers .............................................................
Counter-Compare Event Waveforms in Up-Count Mode .........................................................
Counter-Compare Events in Down-Count Mode ...................................................................
15-12. Time-Base Counter Synchronization Scheme 1
1635
15-13.
1637
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
1638
1638
1639
1640
1640
1643
1643
15-21. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 0] Count Down on

Synchronization Event ................................................................................................ 1644
15-22. Counter-Compare Events in Up-Down-Count Mode, TBCTL[PHSDIR = 1] Count Up on Synchronization
Event .................................................................................................................... 1644
15-23. Action-Qualifier Submodule ........................................................................................... 1645
15-24. Action-Qualifier Submodule Inputs and Outputs
...................................................................
1646
15-25. Possible Action-Qualifier Actions for EPWMxA and EPWMxB Outputs ......................................... 1647
15-26. Up-Down-Count Mode Symmetrical Waveform .................................................................... 1650

15-27. Up, Single Edge Asymmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxBActive High ................................................................................................ 1651
15-28. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and
EPWMxBActive Low ................................................................................................. 1653
15-29. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA
..........
1655
15-30. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB Active Low ............................................................................................... 1657
15-31. Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation on EPWMxA and
EPWMxB Complementary ......................................................................................... 1659
15-32. Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation on EPWMxAActive
Low ....................................................................................................................... 1661
15-33. Dead-Band Generator Submodule ................................................................................... 1663
15-34. Configuration Options for the Dead-Band Generator Submodule
...............................................
1664
15-35. Dead-Band Waveforms for Typical Cases (0% < Duty < 100%) ................................................. 1666
15-36. PWM-Chopper Submodule ............................................................................................ 1667
15-37. PWM-Chopper Submodule Signals and Registers
................................................................
1668
15-38. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only .............................. 1669
15-39. PWM-Chopper Submodule Waveforms Showing the First Pulse and Subsequent Sustaining Pulses ..... 1669
15-40. PWM-Chopper Submodule Waveforms Showing the Pulse Width (Duty Cycle) Control of Sustaining
Pulses .................................................................................................................... 1670
15-41. Trip-Zone Submodule .................................................................................................. 1671
.........................................................................
Trip-Zone Submodule Interrupt Logic ................................................................................
Event-Trigger Submodule .............................................................................................
Event-Trigger Submodule Inter-Connectivity to Interrupt Controller .............................................
Event-Trigger Submodule Showing Event Inputs and Prescaled Outputs ......................................
Event-Trigger Interrupt Generator ....................................................................................
HRPWM System Interface ............................................................................................
Resolution Calculations for Conventionally Generated PWM ....................................................
Operating Logic Using MEP ..........................................................................................
Required PWM Waveform for a Requested Duty = 40.5% .......................................................
Low % Duty Cycle Range Limitation Example When PWM Frequency = 1 MHz ..............................
High % Duty Cycle Range Limitation Example when PWM Frequency = 1 MHz ..............................
Simplified ePWM Module ..............................................................................................
15-42. Trip-Zone Submodule Mode Control Logic
1674
15-43.
1674
15-44.
15-45.
15-46.
15-47.
15-48.
15-49.
15-50.
15-51.
15-52.
15-53.
15-54.

List of Figures
1675
1676
1676
1678
1679
1680
1681
1683
1685
1685
1686
37
www.ti.com
....................................
15-56. Control of Four Buck Stages. Here FPWM1 FPWM2 FPWM3 FPWM4 .................................................
15-57. Buck Waveforms for (Note: Only three bucks shown here).......................................................
15-58. Control of Four Buck Stages. (Note: FPWM2 = N FPWM1) ...........................................................
15-59. Buck Waveforms for (Note: FPWM2 = FPWM1)) ..........................................................................
15-60. Control of Two Half-H Bridge Stages (FPWM2 = N FPWM1) .........................................................
15-61. Half-H Bridge Waveforms for (Note: Here FPWM2 = FPWM1 ) .........................................................
15-62. Control of Dual 3-Phase Inverter Stages as Is Commonly Used in Motor Control ............................
15-63. 3-Phase Inverter Waveforms for (Only One Inverter Shown) ....................................................
15-64. Configuring Two PWM Modules for Phase Control ................................................................
15-65. Timing Waveforms Associated With Phase Control Between 2 Modules .......................................
15-66. Control of a 3-Phase Interleaved DC/DC Converter ...............................................................
15-67. 3-Phase Interleaved DC/DC Converter Waveforms for ...........................................................
15-68. Controlling a Full-H Bridge Stage (FPWM2 = FPWM1) ..................................................................
15-69. ZVS Full-H Bridge Waveforms ........................................................................................
15-70. Time-Base Control Register (TBCTL) ...............................................................................
15-71. Time-Base Status Register (TBSTS) ................................................................................
15-72. Time-Base Phase Register (TBPHS) ................................................................................
15-73. Time-Base Counter Register (TBCNT) ..............................................................................
15-74. Time-Base Period Register (TBPRD) ................................................................................
15-75. Counter-Compare Control Register (CMPCTL) ....................................................................
15-76. Counter-Compare A Register (CMPA) ..............................................................................
15-77. Counter-Compare B Register (CMPB)...............................................................................
15-78. Action-Qualifier Output A Control Register (AQCTLA) ............................................................
15-79. Action-Qualifier Output B Control Register (AQCTLB) ............................................................
15-80. Action-Qualifier Software Force Register (AQSFRC) ..............................................................
15-81. Action-Qualifier Continuous Software Force Register (AQCSFRC) .............................................
15-82. Dead-Band Generator Control Register (DBCTL)..................................................................
15-83. Dead-Band Generator Rising Edge Delay Register (DBRED) ...................................................
15-84. Dead-Band Generator Falling Edge Delay Register (DBFED) ...................................................
15-85. Trip-Zone Select Register (TZSEL) ..................................................................................
15-86. Trip-Zone Control Register (TZCTL) .................................................................................
15-87. Trip-Zone Enable Interrupt Register (TZEINT) .....................................................................
15-88. Trip-Zone Flag Register (TZFLG) ....................................................................................
15-89. Trip-Zone Clear Register (TZCLR) ...................................................................................
15-90. Trip-Zone Force Register (TZFRC) ..................................................................................
15-91. Event-Trigger Selection Register (ETSEL) ..........................................................................
15-92. Event-Trigger Prescale Register (ETPS) ............................................................................
15-93. Event-Trigger Flag Register (ETFLG) ...............................................................................
15-94. Event-Trigger Clear Register (ETCLR) ..............................................................................
15-95. Event-Trigger Force Register (ETFRC) .............................................................................
15-96. PWM-Chopper Control Register (PCCTL) ..........................................................................
15-97. Time-Base Phase High-Resolution Register (TBPHSHR) ........................................................
15-98. Counter-Compare A High-Resolution Register (CMPAHR) .......................................................
15-99. HRPWM Control Register (HRCTL)..................................................................................
15-100. Multiple eCAP Modules ..............................................................................................
15-101. Capture and APWM Modes of Operation .........................................................................
15-102. Capture Function Diagram ..........................................................................................
15-103. Event Prescale Control ...............................................................................................
15-55. EPWM1 Configured as a Typical Master, EPWM2 Configured as a Slave
38
List of Figures
1687
1688
1689
1691
1692
1694
1695
1697
1698
1701
1702
1703
1704
1707
1708
1711
1713
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1724
1725
1726
1726
1727
1728
1728
1729
1730
1731
1731
1732
1733
1734
1734
1735
1737
1738
1739
1740

www.ti.com
......................................................................................
Continuous/One-shot Block Diagram ..............................................................................
Counter and Synchronization Block Diagram ....................................................................
Interrupts in eCAP Module ...........................................................................................
PWM Waveform Details Of APWM Mode Operation ............................................................
Capture Sequence for Absolute Time-Stamp, Rising Edge Detect ............................................
Capture Sequence for Absolute Time-Stamp, Rising and Falling Edge Detect ..............................
Capture Sequence for Delta Mode Time-Stamp, Rising Edge Detect ........................................
Capture Sequence for Delta Mode Time-Stamp, Rising and Falling Edge Detect ..........................
PWM Waveform Details of APWM Mode Operation.............................................................
Multichannel PWM Example Using 4 eCAP Modules ...........................................................
Multiphase (channel) Interleaved PWM Example Using 3 eCAP Modules ...................................
Time-Stamp Counter Register (TSCTR) ...........................................................................
Counter Phase Control Register (CTRPHS) ......................................................................
Capture 1 Register (CAP1) .........................................................................................
Capture 2 Register (CAP2) ..........................................................................................
ECAP Control Register 1 (ECCTL1) ................................................................................
ECAP Control Register 2 (ECCTL2) ...............................................................................
ECAP Interrupt Enable Register (ECEINT) ........................................................................
ECAP Interrupt Flag Register (ECFLG) ...........................................................................
ECAP Interrupt Clear Register (ECCLR)...........................................................................
ECAP Interrupt Forcing Register (ECFRC) ........................................................................
Revision ID Register (REVID) .......................................................................................
Optical Encoder Disk ................................................................................................
QEP Encoder Output Signal for Forward/Reverse Movement ..................................................
Index Pulse Example ................................................................................................
Functional Block Diagram of the eQEP Peripheral ..............................................................
Functional Block Diagram of Decoder Unit ........................................................................
Quadrature Decoder State Machine ...............................................................................
Quadrature-clock and Direction Decoding ........................................................................
Position Counter Reset by Index Pulse for 1000 Line Encoder (QPOSMAX = 3999 or F9Fh) ............
Position Counter Underflow/Overflow (QPOSMAX = 4) ........................................................
Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) .............................................
Strobe Event Latch (QEPCTL[SEL] = 1) ..........................................................................
eQEP Position-compare Unit .......................................................................................
eQEP Position-compare Event Generation Points ...............................................................
eQEP Position-compare Sync Output Pulse Stretcher ..........................................................
eQEP Edge Capture Unit ...........................................................................................
Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) ..............................
eQEP Edge Capture Unit - Timing Details ........................................................................
eQEP Watchdog Timer ..............................................................................................
eQEP Unit Time Base ...............................................................................................
EQEP Interrupt Generation .........................................................................................
eQEP Position Counter Register (QPOSCNT) ....................................................................
eQEP Position Counter Initialization Register (QPOSINIT) .....................................................
eQEP Maximum Position Count Register (QPOSMAX) .........................................................
eQEP Position-Compare Register (QPOSCMP) ..................................................................
15-104. Prescale Function Waveforms

15-105.
15-106.
15-107.
15-108.
15-109.
15-110.
15-111.
15-112.
15-113.
15-114.
15-115.
15-116.
15-117.
15-118.
15-119.
15-120.
15-121.
15-122.
15-123.
15-124.
15-125.
15-126.
15-127.
15-128.
15-129.
15-130.
15-131.
15-132.
15-133.
15-134.
15-135.
15-136.
15-137.
15-138.
15-139.
15-140.
15-141.
15-142.
15-143.
15-144.
15-145.
15-146.
15-147.
15-148.
15-149.
15-150.
15-151.
15-152.

List of Figures
1740
1741
1742
1744
1745
1748
1750
1752
1754
1756
1758
1761
1763
1764
1764
1765
1765
1766
1766
1768
1770
1771
1772
1773
1774
1775
1776
1776
1779
1780
1782
1782
1784
1785
1787
1788
1789
1790
1790
1792
1792
1793
1794
1795
1795
1797
1797
1797
1798
39
www.ti.com
15-153. eQEP Index Position Latch Register (QPOSILAT) ............................................................... 1798

15-154. eQEP Strobe Position Latch Register (QPOSSLAT) ............................................................. 1798
15-155. eQEP Position Counter Latch Register (QPOSLAT) ............................................................. 1799
15-156. eQEP Unit Timer Register (QUTMR) ............................................................................... 1799

15-157. eQEP Unit Period Register (QUPRD) .............................................................................. 1799
15-158. eQEP Watchdog Timer Register (QWDTMR) ..................................................................... 1800
15-159. eQEP Watchdog Period Register (QWDPRD) .................................................................... 1800
15-160. QEP Decoder Control Register (QDECCTL) ...................................................................... 1801
.................................................................................
15-162. eQEP Capture Control Register (QCAPCTL) .....................................................................
15-163. eQEP Position-Compare Control Register (QPOSCTL) .........................................................
15-164. eQEP Interrupt Enable Register (QEINT) ..........................................................................
15-165. eQEP Interrupt Flag Register (QFLG) ..............................................................................
15-166. eQEP Interrupt Clear Register (QCLR) ............................................................................
15-167. eQEP Interrupt Force Register (QFRC) ............................................................................
15-168. eQEP Status Register (QEPSTS)...................................................................................
15-169. eQEP Capture Timer Register (QCTMR) ..........................................................................
15-170. eQEP Capture Period Register (QCPRD) .........................................................................
15-171. eQEP Capture Timer Latch Register (QCTMRLAT)..............................................................
15-172. eQEP Capture Period Latch Register (QCPRDLAT) .............................................................
15-173. eQEP Revision ID Register (REVID) ...............................................................................
16-1. USB Integration .........................................................................................................
16-2. USB GPIO Integration .................................................................................................
16-3. CPU Actions at Transfer Phases .....................................................................................
16-4. Sequence of Transfer ..................................................................................................
16-5. Flow Chart of Setup Stage of a Control Transfer in Peripheral Mode ...........................................
16-6. Flow Chart of Transmit Data Stage of a Control Transfer in Peripheral Mode .................................
16-7. Flow Chart of Receive Data Stage of a Control Transfer in Peripheral Mode..................................
16-8. Flow Chart of Setup Stage of a Control Transfer in Host Mode..................................................
16-9. Flow Chart of Data Stage (IN Data Phase) of a Control Transfer in Host Mode ...............................
16-10. Flow Chart of Data Stage (OUT Data Phase) of a Control Transfer in Host Mode ............................
16-11. Flow Chart of Status Stage of Zero Data Request or Write Request of a Control Transfer in Host Mode .
16-12. Chart of Status Stage of a Read Request of a Control Transfer in Host Mode ................................
16-13. Packet Descriptor Layout ..............................................................................................
16-14. Buffer Descriptor (BD) Layout ........................................................................................
16-15. Teardown Descriptor Layout ..........................................................................................
16-16. Relationship Between Memory Regions and Linking RAM .......................................................
16-17. High-level Transmit and Receive Data Transfer Example ........................................................
16-18. Transmit Descriptors and Queue Status Configuration ...........................................................
16-19. Transmit USB Data Flow Example (Initialization) ..................................................................
16-20. Receive Buffer Descriptors and Queue Status Configuration ....................................................
16-21. Receive USB Data Flow Example (Initialization) ...................................................................
16-22. REVREG Register ......................................................................................................
16-23. SYSCONFIG Register .................................................................................................
16-24. IRQSTATRAW Register ...............................................................................................
16-25. IRQSTAT Register .....................................................................................................
16-26. IRQENABLER Register ................................................................................................
16-27. IRQCLEARR Register .................................................................................................
16-28. IRQDMATHOLDTX00 Register .......................................................................................
15-161. eQEP Control Register (QEPCTL)
40
List of Figures
1802
1804
1805
1806
1807
1808
1810
1811
1812
1812
1812
1813
1813
1818
1820
1828
1829
1831
1832
1833
1844
1845
1847
1848
1850
1860
1863
1865
1871
1876
1878
1879
1881
1882
1887
1888
1889
1890
1891
1892
1893

www.ti.com
16-29. IRQDMATHOLDTX01 Register ....................................................................................... 1894

......................................................................................
IRQDMATHOLDRX01 Register ......................................................................................
IRQDMATHOLDTX10 Register .......................................................................................
IRQDMAENABLE0 Register ..........................................................................................
IRQDMAENABLE1 Register ..........................................................................................
IRQFRAMETHOLDTX00 Register ...................................................................................
IRQFRAMETHOLDRX00 Register ...................................................................................
IRQFRAMEENABLE0 Register .......................................................................................
IRQFRAMEENABLE1 Register .......................................................................................
USB0REV Register.....................................................................................................
USB0CTRL Register ...................................................................................................
USB0STAT Register ...................................................................................................
USB0IRQMSTAT Register ............................................................................................
USB0IRQSTATRAW0 Register.......................................................................................
USB0IRQSTATRAW1 Register.......................................................................................
USB0IRQSTAT0 Register .............................................................................................
USB0IRQSTAT1 Register .............................................................................................
USB0IRQENABLESET0 Register ....................................................................................
USB0IRQENABLESET1 Register ....................................................................................
USB0IRQENABLECLR0 Register ....................................................................................
USB0IRQENABLECLR1 Register ....................................................................................
USB0TXMODE Register...............................................................................................
USB0RXMODE Register ..............................................................................................
16-32. IRQDMATHOLDRX00 Register
1897
16-33.
1898
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
16-47.
16-48.
16-49.
16-50.
16-51.
16-52.
16-53.
16-54.
16-55.
16-56.
16-57.
16-58.
16-59.
16-60.
16-61.
16-62.
16-63.
16-64.
16-65.
16-66.
16-67.
16-68.
16-69.
16-70.
16-71.
16-72.
16-73.
16-74.
16-75.
16-76.
16-77.

List of Figures
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1930
1931
1933
1934
1935
1937
1939
1941
1943
1945
1947
1949
1951
1953
41
www.ti.com
16-78. USB0GENRNDISEP1 Register ....................................................................................... 1957

16-87. USB0GENRNDISEP10 Register ..................................................................................... 1966
16-93. USB0AUTOREQ Register ............................................................................................. 1972
16-94. USB0SRPFIXTIME Register .......................................................................................... 1974
..............................................................................................
...................................................................................................
16-97. USB0MGCUTMILB Register ..........................................................................................
16-98. USB0MODE Register ..................................................................................................
16-99. USB1REV Register.....................................................................................................
16-100. USB1CTRL Register ..................................................................................................
16-101. USB1STAT Register ..................................................................................................
16-102. USB1IRQMSTAT Register ...........................................................................................
16-103. USB1IRQSTATRAW0 Register .....................................................................................
16-104. USB1IRQSTATRAW1 Register .....................................................................................
16-105. USB1IRQSTAT0 Register ...........................................................................................
16-106. USB1IRQSTAT1 Register ...........................................................................................
16-107. USB1IRQENABLESET0 Register ..................................................................................
16-108. USB1IRQENABLESET1 Register ..................................................................................
16-109. USB1IRQENABLECLR0 Register ..................................................................................
16-110. USB1IRQENABLECLR1 Register ..................................................................................
16-111. USB1TXMODE Register .............................................................................................
16-112. USB1RXMODE Register .............................................................................................
16-113. USB1GENRNDISEP1 Register .....................................................................................
16-122. USB1GENRNDISEP10 Register ....................................................................................
42
16-95. USB0_TDOWN Register
1975
16-96. USB0UTMI Register
1976
List of Figures
1977
1978
1980
1981
1983
1984
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018

www.ti.com
16-127. USB1GENRNDISEP15 Register .................................................................................... 2019
16-128. USB1AUTOREQ Register ........................................................................................... 2020
........................................................................................
..............................................................................................
USB1UTMI Register ..................................................................................................
USB1UTMILB Register ...............................................................................................
USB1MODE Register.................................................................................................
Termination_control Register ........................................................................................
RX_CALIB Register ...................................................................................................
DLLHS_2 Register ....................................................................................................
RX_TEST_2 Register.................................................................................................
CHRG_DET Register .................................................................................................
PWR_CNTL Register .................................................................................................
UTMI_INTERFACE_CNTL_1 Register .............................................................................
UTMI_INTERFACE_CNTL_2 Register .............................................................................
BIST Register ..........................................................................................................
BIST_CRC Register ..................................................................................................
CDR_BIST2 Register .................................................................................................
GPIO Register .........................................................................................................
DLLHS Register .......................................................................................................
USB2PHYCM_TRIM Register .......................................................................................
USB2PHYCM_CONFIG Register ...................................................................................
USBOTG Register ....................................................................................................
AD_INTERFACE_REG1 Register ..................................................................................
ANA_CONFIG1 Register .............................................................................................
ANA_CONFIG2 Register .............................................................................................
DMAREVID Register .................................................................................................
TDFDQ Register ......................................................................................................
DMAEMU Register ....................................................................................................
TXGCR0 Register .....................................................................................................
RXGCR0 Register ....................................................................................................
RXHPCRA0 Register .................................................................................................
RXHPCRB0 Register .................................................................................................
TXGCR1 Register .....................................................................................................
RXGCR1 Register ....................................................................................................
TXGCR2 Register .....................................................................................................
RXGCR2 Register ....................................................................................................
TXGCR3 Register .....................................................................................................
RXGCR3 Register ....................................................................................................
TXGCR4 Register .....................................................................................................
RXGCR4 Register ....................................................................................................
16-129. USB1SRPFIXTIME Register
2022
16-130. USB1TDOWN Register
2023
16-131.
2024
16-132.
16-133.
16-134.
16-135.
16-136.
16-137.
16-138.
16-139.
16-140.
16-141.
16-142.
16-143.
16-144.
16-145.
16-146.
16-147.
16-148.
16-149.
16-150.
16-151.
16-152.
16-153.
16-154.
16-155.
16-156.
16-157.
16-158.
16-159.
16-160.
16-161.
16-162.
16-163.
16-164.
16-165.
16-166.
16-167.
16-168.
16-169.
16-170.
16-171.
16-172.
16-173.
16-174.
16-175.

List of Figures
2025
2026
2028
2029
2031
2032
2033
2035
2036
2037
2039
2040
2041
2042
2043
2044
2045
2046
2047
2049
2051
2052
2053
2057
2058
2059
2060
2061
2063
2064
2065
2066
2068
2069
2070
2071
2073
2074
2075
2076
2078
2079
2080
2081
43
www.ti.com
16-176. RXHPCRA4 Register ................................................................................................. 2083

16-177. RXHPCRB4 Register ................................................................................................. 2084
16-178. TXGCR5 Register ..................................................................................................... 2085

2086
16-180.
2088
16-181.
16-182.
16-183.
16-184.
16-185.
16-186.
16-187.
16-188.
16-189.
16-190.
16-191.
16-192.
16-193.
16-194.
16-195.
16-196.
16-197.
16-198.
16-199.
16-200.
16-201.
16-202.
16-203.
16-204.
16-205.
16-206.
16-207.
16-208.
16-209.
16-210.
16-211.
16-212.
16-213.
16-214.
16-215.
16-216.
16-217.
16-218.
16-219.
16-220.
16-221.
16-222.
16-223.
16-224.
44
....................................................................................................
TXGCR6 Register .....................................................................................................
RXGCR6 Register ....................................................................................................
TXGCR7 Register .....................................................................................................
RXGCR7 Register ....................................................................................................
TXGCR8 Register .....................................................................................................
RXGCR8 Register ....................................................................................................
TXGCR9 Register .....................................................................................................
RXGCR9 Register ....................................................................................................
TXGCR10 Register ...................................................................................................
RXGCR10 Register ...................................................................................................
RXHPCRA10 Register................................................................................................
RXHPCRB10 Register................................................................................................
TXGCR11 Register ...................................................................................................
RXGCR11 Register ...................................................................................................
TXGCR12 Register ...................................................................................................
RXGCR12 Register ...................................................................................................
TXGCR13 Register ...................................................................................................
RXGCR13 Register ...................................................................................................
TXGCR14 Register ...................................................................................................
RXGCR14 Register ...................................................................................................
TXGCR15 Register ...................................................................................................
RXGCR15 Register ...................................................................................................
TXGCR16 Register ...................................................................................................
RXGCR16 Register ...................................................................................................
16-179. RXGCR5 Register
List of Figures
2089
2090
2091
2093
2094
2095
2096
2098
2099
2100
2101
2103
2104
2105
2106
2108
2109
2110
2111
2113
2114
2115
2116
2118
2119
2120
2121
2123
2124
2125
2126
2128
2129
2130
2131
2133
2134
2135
2136
2138
2139
2140
2141
2143

www.ti.com
16-225. RXHPCRB16 Register................................................................................................ 2144
16-226. TXGCR17 Register ................................................................................................... 2145

16-227. RXGCR17 Register ................................................................................................... 2146
16-228. RXHPCRA17 Register................................................................................................ 2148
16-230. TXGCR18 Register ................................................................................................... 2150

16-231. RXGCR18 Register ................................................................................................... 2151
16-234. TXGCR19 Register ................................................................................................... 2155

16-235. RXGCR19 Register ................................................................................................... 2156
16-238. TXGCR20 Register ................................................................................................... 2160

16-239. RXGCR20 Register ................................................................................................... 2161
16-242. TXGCR21 Register ................................................................................................... 2165

16-243. RXGCR21 Register ................................................................................................... 2166
16-246. TXGCR22 Register ................................................................................................... 2170

16-247. RXGCR22 Register ................................................................................................... 2171
16-250. TXGCR23 Register ................................................................................................... 2175

16-251. RXGCR23 Register ................................................................................................... 2176
16-254. TXGCR24 Register ................................................................................................... 2180

16-255. RXGCR24 Register ................................................................................................... 2181
16-258. TXGCR25 Register ................................................................................................... 2185

16-259. RXGCR25 Register ................................................................................................... 2186
16-262. TXGCR26 Register ................................................................................................... 2190

16-263. RXGCR26 Register ................................................................................................... 2191
16-266. TXGCR27 Register ................................................................................................... 2195

16-267. RXGCR27 Register ................................................................................................... 2196
16-270. TXGCR28 Register ................................................................................................... 2200

16-271. RXGCR28 Register ................................................................................................... 2201
List of Figures
45
www.ti.com
16-274. TXGCR29 Register ................................................................................................... 2205
16-275. RXGCR29 Register ................................................................................................... 2206

16-278. DMA_SCHED_CTRL Register ...................................................................................... 2212
16-279. WORD0 Register ...................................................................................................... 2213

16-280. WORD1 Register ...................................................................................................... 2214
16-281. WORD2 Register ...................................................................................................... 2215
16-282. WORD5 Register ...................................................................................................... 2216
16-283. WORD6 Register ...................................................................................................... 2217
16-284. WORD7 Register ...................................................................................................... 2218
16-285. WORD8 Register ...................................................................................................... 2219
16-286. WORD9 Register ...................................................................................................... 2220
16-287. WORD10 Register .................................................................................................... 2221
16-288. WORD11 Register .................................................................................................... 2222
16-289. WORD12 Register .................................................................................................... 2223
16-290. WORD13 Register .................................................................................................... 2224
16-291. WORD14 Register .................................................................................................... 2225
16-292. WORD15 Register .................................................................................................... 2226
16-293. WORD16 Register .................................................................................................... 2227
16-294. WORD17 Register .................................................................................................... 2228
16-295. WORD18 Register .................................................................................................... 2229
16-296. WORD19 Register .................................................................................................... 2230
16-297. WORD20 Register .................................................................................................... 2231
16-298. WORD21 Register .................................................................................................... 2232
16-299. WORD22 Register .................................................................................................... 2233
16-300. WORD23 Register .................................................................................................... 2234
16-301. WORD24 Register .................................................................................................... 2235
16-302. WORD25 Register .................................................................................................... 2236
16-303. WORD26 Register .................................................................................................... 2237
16-304. WORD27 Register .................................................................................................... 2238
16-305. WORD28 Register .................................................................................................... 2239
16-306. WORD29 Register .................................................................................................... 2240
16-307. WORD30 Register .................................................................................................... 2241
16-308. WORD31 Register .................................................................................................... 2242
16-309. WORD32 Register .................................................................................................... 2243
16-310. WORD33 Register .................................................................................................... 2244
16-311. WORD34 Register .................................................................................................... 2245
16-312. WORD35 Register .................................................................................................... 2246
16-313. WORD36 Register .................................................................................................... 2247
16-314. WORD37 Register .................................................................................................... 2248
16-315. WORD38 Register .................................................................................................... 2249
16-316. WORD39 Register .................................................................................................... 2250
16-317. WORD40 Register .................................................................................................... 2251
16-318. WORD41 Register .................................................................................................... 2252
16-319. WORD42 Register .................................................................................................... 2253
16-320. WORD43 Register .................................................................................................... 2254
16-321. WORD44 Register .................................................................................................... 2255
16-322. WORD45 Register .................................................................................................... 2256
46
List of Figures

www.ti.com
16-323. WORD46 Register .................................................................................................... 2257
16-324. WORD47 Register .................................................................................................... 2258

16-325. WORD48 Register .................................................................................................... 2259
16-326. WORD49 Register .................................................................................................... 2260
16-327. WORD50 Register .................................................................................................... 2261
16-328. WORD51 Register .................................................................................................... 2262
16-329. WORD52 Register .................................................................................................... 2263
16-330. WORD53 Register .................................................................................................... 2264
16-331. WORD54 Register .................................................................................................... 2265
16-332. WORD55 Register .................................................................................................... 2266
16-333. WORD56 Register .................................................................................................... 2267
16-334. WORD57 Register .................................................................................................... 2268
16-335. WORD58 Register .................................................................................................... 2269
16-336. WORD59 Register .................................................................................................... 2270
16-337. WORD60 Register .................................................................................................... 2271
16-338. WORD61 Register .................................................................................................... 2272
16-339. WORD62 Register .................................................................................................... 2273
16-340. WORD63 Register .................................................................................................... 2274
16-341. QMGRREVID Register ............................................................................................... 2299
16-342. QMGRRST Register .................................................................................................. 2300
16-343. FDBSC0 Register ..................................................................................................... 2301
16-344. FDBSC1 Register ..................................................................................................... 2302
16-345. FDBSC2 Register ..................................................................................................... 2303
16-346. FDBSC3 Register ..................................................................................................... 2304
16-347. FDBSC4 Register ..................................................................................................... 2305
16-348. FDBSC5 Register ..................................................................................................... 2306
16-349. FDBSC6 Register ..................................................................................................... 2307
16-350. FDBSC7 Register ..................................................................................................... 2308
16-351. LRAM0BASE Register................................................................................................ 2309

16-352. LRAM0SIZE Register ................................................................................................. 2310
16-353. LRAM1BASE Register................................................................................................ 2311

16-354. PEND0 Register ....................................................................................................... 2312
16-355. PEND1 Register ....................................................................................................... 2313
16-356. PEND2 Register ....................................................................................................... 2314
16-357. PEND3 Register ....................................................................................................... 2315
16-358. PEND4 Register ....................................................................................................... 2316
16-359. QMEMRBASE0 Register ............................................................................................. 2317
16-360. QMEMCTRL0 Register ............................................................................................... 2318
List of Figures
47
www.ti.com

16-375. QUEUE_0_A Register ................................................................................................ 2333
16-376. QUEUE_0_B Register ................................................................................................ 2334
16-377. QUEUE_0_C Register ................................................................................................ 2335
16-378. QUEUE_0_D Register ................................................................................................ 2336
16-379. QUEUE_1_A Register ................................................................................................ 2337
16-380. QUEUE_1_B Register ................................................................................................ 2338
16-381. QUEUE_1_C Register ................................................................................................ 2339
16-382. QUEUE_1_D Register ................................................................................................ 2340
16-383. QUEUE_2_A Register ................................................................................................ 2341
16-384. QUEUE_2_B Register ................................................................................................ 2342
16-385. QUEUE_2_C Register ................................................................................................ 2343
16-386. QUEUE_2_D Register ................................................................................................ 2344
16-387. QUEUE_3_A Register ................................................................................................ 2345
16-388. QUEUE_3_B Register ................................................................................................ 2346
16-389. QUEUE_3_C Register ................................................................................................ 2347
16-390. QUEUE_3_D Register ................................................................................................ 2348
16-391. QUEUE_4_A Register ................................................................................................ 2349
16-392. QUEUE_4_B Register ................................................................................................ 2350
16-393. QUEUE_4_C Register ................................................................................................ 2351
16-394. QUEUE_4_D Register ................................................................................................ 2352
16-395. QUEUE_5_A Register ................................................................................................ 2353
16-396. QUEUE_5_B Register ................................................................................................ 2354
16-397. QUEUE_5_C Register ................................................................................................ 2355
16-398. QUEUE_5_D Register ................................................................................................ 2356
16-399. QUEUE_6_A Register ................................................................................................ 2357
16-400. QUEUE_6_B Register ................................................................................................ 2358
16-401. QUEUE_6_C Register ................................................................................................ 2359
16-402. QUEUE_6_D Register ................................................................................................ 2360
16-403. QUEUE_7_A Register ................................................................................................ 2361
16-404. QUEUE_7_B Register ................................................................................................ 2362
16-405. QUEUE_7_C Register ................................................................................................ 2363
16-406. QUEUE_7_D Register ................................................................................................ 2364
16-407. QUEUE_8_A Register ................................................................................................ 2365
16-408. QUEUE_8_B Register ................................................................................................ 2366
16-409. QUEUE_8_C Register ................................................................................................ 2367
16-410. QUEUE_8_D Register ................................................................................................ 2368
16-411. QUEUE_9_A Register ................................................................................................ 2369
16-412. QUEUE_9_B Register ................................................................................................ 2370
16-413. QUEUE_9_C Register ................................................................................................ 2371
16-414. QUEUE_9_D Register ................................................................................................ 2372
16-415. QUEUE_10_A Register .............................................................................................. 2373
16-416. QUEUE_10_B Register .............................................................................................. 2374
16-417. QUEUE_10_C Register .............................................................................................. 2375

16-418. QUEUE_10_D Register .............................................................................................. 2376
16-419. QUEUE_11_A Register .............................................................................................. 2377
16-420. QUEUE_11_B Register .............................................................................................. 2378
48
List of Figures

www.ti.com
16-421. QUEUE_11_C Register .............................................................................................. 2379

16-422. QUEUE_11_D Register .............................................................................................. 2380
16-423. QUEUE_12_A Register .............................................................................................. 2381
16-424. QUEUE_12_B Register .............................................................................................. 2382
16-425. QUEUE_12_C Register .............................................................................................. 2383

16-426. QUEUE_12_D Register .............................................................................................. 2384
16-427. QUEUE_13_A Register .............................................................................................. 2385
16-428. QUEUE_13_B Register .............................................................................................. 2386
16-429. QUEUE_13_C Register .............................................................................................. 2387

16-430. QUEUE_13_D Register .............................................................................................. 2388
16-431. QUEUE_14_A Register .............................................................................................. 2389
16-432. QUEUE_14_B Register .............................................................................................. 2390
16-433. QUEUE_14_C Register .............................................................................................. 2391

16-434. QUEUE_14_D Register .............................................................................................. 2392
16-435. QUEUE_15_A Register .............................................................................................. 2393
16-436. QUEUE_15_B Register .............................................................................................. 2394
16-437. QUEUE_15_C Register .............................................................................................. 2395

16-438. QUEUE_15_D Register .............................................................................................. 2396
16-439. QUEUE_16_A Register .............................................................................................. 2397
16-440. QUEUE_16_B Register .............................................................................................. 2398
16-441. QUEUE_16_C Register .............................................................................................. 2399

16-442. QUEUE_16_D Register .............................................................................................. 2400
16-443. QUEUE_17_A Register .............................................................................................. 2401
16-444. QUEUE_17_B Register .............................................................................................. 2402
16-445. QUEUE_17_C Register .............................................................................................. 2403

16-446. QUEUE_17_D Register .............................................................................................. 2404
16-447. QUEUE_18_A Register .............................................................................................. 2405
16-448. QUEUE_18_B Register .............................................................................................. 2406
16-449. QUEUE_18_C Register .............................................................................................. 2407

16-450. QUEUE_18_D Register .............................................................................................. 2408
16-451. QUEUE_19_A Register .............................................................................................. 2409
16-452. QUEUE_19_B Register .............................................................................................. 2410
16-453. QUEUE_19_C Register .............................................................................................. 2411

16-454. QUEUE_19_D Register .............................................................................................. 2412
16-455. QUEUE_20_A Register .............................................................................................. 2413
16-456. QUEUE_20_B Register .............................................................................................. 2414
16-457. QUEUE_20_C Register .............................................................................................. 2415

16-458. QUEUE_20_D Register .............................................................................................. 2416
16-459. QUEUE_21_A Register .............................................................................................. 2417
16-460. QUEUE_21_B Register .............................................................................................. 2418
16-461. QUEUE_21_C Register .............................................................................................. 2419

16-462. QUEUE_21_D Register .............................................................................................. 2420
16-463. QUEUE_22_A Register .............................................................................................. 2421
16-464. QUEUE_22_B Register .............................................................................................. 2422
16-465. QUEUE_22_C Register .............................................................................................. 2423

16-466. QUEUE_22_D Register .............................................................................................. 2424
16-467. QUEUE_23_A Register .............................................................................................. 2425
16-468. QUEUE_23_B Register .............................................................................................. 2426
16-469. QUEUE_23_C Register .............................................................................................. 2427

List of Figures
49
www.ti.com
16-470. QUEUE_23_D Register .............................................................................................. 2428

16-471. QUEUE_24_A Register .............................................................................................. 2429
16-472. QUEUE_24_B Register .............................................................................................. 2430
16-473. QUEUE_24_C Register .............................................................................................. 2431

16-474. QUEUE_24_D Register .............................................................................................. 2432
16-475. QUEUE_25_A Register .............................................................................................. 2433
16-476. QUEUE_25_B Register .............................................................................................. 2434
16-477. QUEUE_25_C Register .............................................................................................. 2435

16-478. QUEUE_25_D Register .............................................................................................. 2436
16-479. QUEUE_26_A Register .............................................................................................. 2437
16-480. QUEUE_26_B Register .............................................................................................. 2438
16-481. QUEUE_26_C Register .............................................................................................. 2439

16-482. QUEUE_26_D Register .............................................................................................. 2440
16-483. QUEUE_27_A Register .............................................................................................. 2441
16-484. QUEUE_27_B Register .............................................................................................. 2442
16-485. QUEUE_27_C Register .............................................................................................. 2443

16-486. QUEUE_27_D Register .............................................................................................. 2444
16-487. QUEUE_28_A Register .............................................................................................. 2445
16-488. QUEUE_28_B Register .............................................................................................. 2446
16-489. QUEUE_28_C Register .............................................................................................. 2447

16-490. QUEUE_28_D Register .............................................................................................. 2448
16-491. QUEUE_29_A Register .............................................................................................. 2449
16-492. QUEUE_29_B Register .............................................................................................. 2450
16-493. QUEUE_29_C Register .............................................................................................. 2451

16-494. QUEUE_29_D Register .............................................................................................. 2452
16-495. QUEUE_30_A Register .............................................................................................. 2453
16-496. QUEUE_30_B Register .............................................................................................. 2454
16-497. QUEUE_30_C Register .............................................................................................. 2455

16-498. QUEUE_30_D Register .............................................................................................. 2456
16-499. QUEUE_31_A Register .............................................................................................. 2457
16-500. QUEUE_31_B Register .............................................................................................. 2458
16-501. QUEUE_31_C Register .............................................................................................. 2459

16-502. QUEUE_31_D Register .............................................................................................. 2460
16-503. QUEUE_32_A Register .............................................................................................. 2461
16-504. QUEUE_32_B Register .............................................................................................. 2462
16-505. QUEUE_32_C Register .............................................................................................. 2463

16-506. QUEUE_32_D Register .............................................................................................. 2464
16-507. QUEUE_33_A Register .............................................................................................. 2465
16-508. QUEUE_33_B Register .............................................................................................. 2466
16-509. QUEUE_33_C Register .............................................................................................. 2467

16-510. QUEUE_33_D Register .............................................................................................. 2468
16-511. QUEUE_34_A Register .............................................................................................. 2469
16-512. QUEUE_34_B Register .............................................................................................. 2470
16-513. QUEUE_34_C Register .............................................................................................. 2471

16-514. QUEUE_34_D Register .............................................................................................. 2472
16-515. QUEUE_35_A Register .............................................................................................. 2473
16-516. QUEUE_35_B Register .............................................................................................. 2474
16-517. QUEUE_35_C Register .............................................................................................. 2475

16-518. QUEUE_35_D Register .............................................................................................. 2476
50
List of Figures

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16-519. QUEUE_36_A Register .............................................................................................. 2477

16-520. QUEUE_36_B Register .............................................................................................. 2478
16-521. QUEUE_36_C Register .............................................................................................. 2479

16-522. QUEUE_36_D Register .............................................................................................. 2480
16-523. QUEUE_37_A Register .............................................................................................. 2481
16-524. QUEUE_37_B Register .............................................................................................. 2482
16-525. QUEUE_37_C Register .............................................................................................. 2483

16-526. QUEUE_37_D Register .............................................................................................. 2484
16-527. QUEUE_38_A Register .............................................................................................. 2485
16-528. QUEUE_38_B Register .............................................................................................. 2486
16-529. QUEUE_38_C Register .............................................................................................. 2487

16-530. QUEUE_38_D Register .............................................................................................. 2488
16-531. QUEUE_39_A Register .............................................................................................. 2489
16-532. QUEUE_39_B Register .............................................................................................. 2490
16-533. QUEUE_39_C Register .............................................................................................. 2491

16-534. QUEUE_39_D Register .............................................................................................. 2492
16-535. QUEUE_40_A Register .............................................................................................. 2493
16-536. QUEUE_40_B Register .............................................................................................. 2494
16-537. QUEUE_40_C Register .............................................................................................. 2495

16-538. QUEUE_40_D Register .............................................................................................. 2496
16-539. QUEUE_41_A Register .............................................................................................. 2497
16-540. QUEUE_41_B Register .............................................................................................. 2498
16-541. QUEUE_41_C Register .............................................................................................. 2499

16-542. QUEUE_41_D Register .............................................................................................. 2500
16-543. QUEUE_42_A Register .............................................................................................. 2501
16-544. QUEUE_42_B Register .............................................................................................. 2502
16-545. QUEUE_42_C Register .............................................................................................. 2503

16-546. QUEUE_42_D Register .............................................................................................. 2504
16-547. QUEUE_43_A Register .............................................................................................. 2505
16-548. QUEUE_43_B Register .............................................................................................. 2506
16-549. QUEUE_43_C Register .............................................................................................. 2507

16-550. QUEUE_43_D Register .............................................................................................. 2508
16-551. QUEUE_44_A Register .............................................................................................. 2509
16-552. QUEUE_44_B Register .............................................................................................. 2510
16-553. QUEUE_44_C Register .............................................................................................. 2511

16-554. QUEUE_44_D Register .............................................................................................. 2512
16-555. QUEUE_45_A Register .............................................................................................. 2513
16-556. QUEUE_45_B Register .............................................................................................. 2514
16-557. QUEUE_45_C Register .............................................................................................. 2515

16-558. QUEUE_45_D Register .............................................................................................. 2516
16-559. QUEUE_46_A Register .............................................................................................. 2517
16-560. QUEUE_46_B Register .............................................................................................. 2518
16-561. QUEUE_46_C Register .............................................................................................. 2519

16-562. QUEUE_46_D Register .............................................................................................. 2520
16-563. QUEUE_47_A Register .............................................................................................. 2521
16-564. QUEUE_47_B Register .............................................................................................. 2522
16-565. QUEUE_47_C Register .............................................................................................. 2523

16-566. QUEUE_47_D Register .............................................................................................. 2524
16-567. QUEUE_48_A Register .............................................................................................. 2525
List of Figures
51
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16-568. QUEUE_48_B Register .............................................................................................. 2526
16-569. QUEUE_48_C Register .............................................................................................. 2527

16-570. QUEUE_48_D Register .............................................................................................. 2528
16-571. QUEUE_49_A Register .............................................................................................. 2529
16-572. QUEUE_49_B Register .............................................................................................. 2530
16-573. QUEUE_49_C Register .............................................................................................. 2531

16-574. QUEUE_49_D Register .............................................................................................. 2532
16-575. QUEUE_50_A Register .............................................................................................. 2533
16-576. QUEUE_50_B Register .............................................................................................. 2534
16-577. QUEUE_50_C Register .............................................................................................. 2535

16-578. QUEUE_50_D Register .............................................................................................. 2536
16-579. QUEUE_51_A Register .............................................................................................. 2537
16-580. QUEUE_51_B Register .............................................................................................. 2538
16-581. QUEUE_51_C Register .............................................................................................. 2539

16-582. QUEUE_51_D Register .............................................................................................. 2540
16-583. QUEUE_52_A Register .............................................................................................. 2541
16-584. QUEUE_52_B Register .............................................................................................. 2542
16-585. QUEUE_52_C Register .............................................................................................. 2543

16-586. QUEUE_52_D Register .............................................................................................. 2544
16-587. QUEUE_53_A Register .............................................................................................. 2545
16-588. QUEUE_53_B Register .............................................................................................. 2546
16-589. QUEUE_53_C Register .............................................................................................. 2547

16-590. QUEUE_53_D Register .............................................................................................. 2548
16-591. QUEUE_54_A Register .............................................................................................. 2549
16-592. QUEUE_54_B Register .............................................................................................. 2550
16-593. QUEUE_54_C Register .............................................................................................. 2551

16-594. QUEUE_54_D Register .............................................................................................. 2552
16-595. QUEUE_55_A Register .............................................................................................. 2553
16-596. QUEUE_55_B Register .............................................................................................. 2554
16-597. QUEUE_55_C Register .............................................................................................. 2555

16-598. QUEUE_55_D Register .............................................................................................. 2556
16-599. QUEUE_56_A Register .............................................................................................. 2557
16-600. QUEUE_56_B Register .............................................................................................. 2558
16-601. QUEUE_56_C Register .............................................................................................. 2559

16-602. QUEUE_56_D Register .............................................................................................. 2560
16-603. QUEUE_57_A Register .............................................................................................. 2561
16-604. QUEUE_57_B Register .............................................................................................. 2562
16-605. QUEUE_57_C Register .............................................................................................. 2563

16-606. QUEUE_57_D Register .............................................................................................. 2564
16-607. QUEUE_58_A Register .............................................................................................. 2565
16-608. QUEUE_58_B Register .............................................................................................. 2566
16-609. QUEUE_58_C Register .............................................................................................. 2567

16-610. QUEUE_58_D Register .............................................................................................. 2568
16-611. QUEUE_59_A Register .............................................................................................. 2569
16-612. QUEUE_59_B Register .............................................................................................. 2570
16-613. QUEUE_59_C Register .............................................................................................. 2571

16-614. QUEUE_59_D Register .............................................................................................. 2572
16-615. QUEUE_60_A Register .............................................................................................. 2573
16-616. QUEUE_60_B Register .............................................................................................. 2574
52
List of Figures

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16-617. QUEUE_60_C Register .............................................................................................. 2575

16-618. QUEUE_60_D Register .............................................................................................. 2576
16-619. QUEUE_61_A Register .............................................................................................. 2577
16-620. QUEUE_61_B Register .............................................................................................. 2578
16-621. QUEUE_61_C Register .............................................................................................. 2579

16-622. QUEUE_61_D Register .............................................................................................. 2580
16-623. QUEUE_62_A Register .............................................................................................. 2581
16-624. QUEUE_62_B Register .............................................................................................. 2582
16-625. QUEUE_62_C Register .............................................................................................. 2583

16-626. QUEUE_62_D Register .............................................................................................. 2584
16-627. QUEUE_63_A Register .............................................................................................. 2585
16-628. QUEUE_63_B Register .............................................................................................. 2586
16-629. QUEUE_63_C Register .............................................................................................. 2587

16-630. QUEUE_63_D Register .............................................................................................. 2588
16-631. QUEUE_64_A Register .............................................................................................. 2589
16-632. QUEUE_64_B Register .............................................................................................. 2590
16-633. QUEUE_64_C Register .............................................................................................. 2591

16-634. QUEUE_64_D Register .............................................................................................. 2592
16-635. QUEUE_65_A Register .............................................................................................. 2593
16-636. QUEUE_65_B Register .............................................................................................. 2594
16-637. QUEUE_65_C Register .............................................................................................. 2595

16-638. QUEUE_65_D Register .............................................................................................. 2596
16-639. QUEUE_66_A Register .............................................................................................. 2597
16-640. QUEUE_66_B Register .............................................................................................. 2598
16-641. QUEUE_66_C Register .............................................................................................. 2599

16-642. QUEUE_66_D Register .............................................................................................. 2600
16-643. QUEUE_67_A Register .............................................................................................. 2601
16-644. QUEUE_67_B Register .............................................................................................. 2602
16-645. QUEUE_67_C Register .............................................................................................. 2603

16-646. QUEUE_67_D Register .............................................................................................. 2604
16-647. QUEUE_68_A Register .............................................................................................. 2605
16-648. QUEUE_68_B Register .............................................................................................. 2606
16-649. QUEUE_68_C Register .............................................................................................. 2607

16-650. QUEUE_68_D Register .............................................................................................. 2608
16-651. QUEUE_69_A Register .............................................................................................. 2609
16-652. QUEUE_69_B Register .............................................................................................. 2610
16-653. QUEUE_69_C Register .............................................................................................. 2611

16-654. QUEUE_69_D Register .............................................................................................. 2612
16-655. QUEUE_70_A Register .............................................................................................. 2613
16-656. QUEUE_70_B Register .............................................................................................. 2614
16-657. QUEUE_70_C Register .............................................................................................. 2615

16-658. QUEUE_70_D Register .............................................................................................. 2616
16-659. QUEUE_71_A Register .............................................................................................. 2617
16-660. QUEUE_71_B Register .............................................................................................. 2618
16-661. QUEUE_71_C Register .............................................................................................. 2619

16-662. QUEUE_71_D Register .............................................................................................. 2620
16-663. QUEUE_72_A Register .............................................................................................. 2621
16-664. QUEUE_72_B Register .............................................................................................. 2622
16-665. QUEUE_72_C Register .............................................................................................. 2623

List of Figures
53
www.ti.com
16-666. QUEUE_72_D Register .............................................................................................. 2624

16-667. QUEUE_73_A Register .............................................................................................. 2625
16-668. QUEUE_73_B Register .............................................................................................. 2626
16-669. QUEUE_73_C Register .............................................................................................. 2627

16-670. QUEUE_73_D Register .............................................................................................. 2628
16-671. QUEUE_74_A Register .............................................................................................. 2629
16-672. QUEUE_74_B Register .............................................................................................. 2630
16-673. QUEUE_74_C Register .............................................................................................. 2631

16-674. QUEUE_74_D Register .............................................................................................. 2632
16-675. QUEUE_75_A Register .............................................................................................. 2633
16-676. QUEUE_75_B Register .............................................................................................. 2634
16-677. QUEUE_75_C Register .............................................................................................. 2635

16-678. QUEUE_75_D Register .............................................................................................. 2636
16-679. QUEUE_76_A Register .............................................................................................. 2637
16-680. QUEUE_76_B Register .............................................................................................. 2638
16-681. QUEUE_76_C Register .............................................................................................. 2639

16-682. QUEUE_76_D Register .............................................................................................. 2640
16-683. QUEUE_77_A Register .............................................................................................. 2641
16-684. QUEUE_77_B Register .............................................................................................. 2642
16-685. QUEUE_77_C Register .............................................................................................. 2643

16-686. QUEUE_77_D Register .............................................................................................. 2644
16-687. QUEUE_78_A Register .............................................................................................. 2645
16-688. QUEUE_78_B Register .............................................................................................. 2646
16-689. QUEUE_78_C Register .............................................................................................. 2647

16-690. QUEUE_78_D Register .............................................................................................. 2648
16-691. QUEUE_79_A Register .............................................................................................. 2649
16-692. QUEUE_79_B Register .............................................................................................. 2650
16-693. QUEUE_79_C Register .............................................................................................. 2651

16-694. QUEUE_79_D Register .............................................................................................. 2652
16-695. QUEUE_80_A Register .............................................................................................. 2653
16-696. QUEUE_80_B Register .............................................................................................. 2654
16-697. QUEUE_80_C Register .............................................................................................. 2655

16-698. QUEUE_80_D Register .............................................................................................. 2656
16-699. QUEUE_81_A Register .............................................................................................. 2657
16-700. QUEUE_81_B Register .............................................................................................. 2658
16-701. QUEUE_81_C Register .............................................................................................. 2659

16-702. QUEUE_81_D Register .............................................................................................. 2660
16-703. QUEUE_82_A Register .............................................................................................. 2661
16-704. QUEUE_82_B Register .............................................................................................. 2662
16-705. QUEUE_82_C Register .............................................................................................. 2663

16-706. QUEUE_82_D Register .............................................................................................. 2664
16-707. QUEUE_83_A Register .............................................................................................. 2665
16-708. QUEUE_83_B Register .............................................................................................. 2666
16-709. QUEUE_83_C Register .............................................................................................. 2667

16-710. QUEUE_83_D Register .............................................................................................. 2668
16-711. QUEUE_84_A Register .............................................................................................. 2669
16-712. QUEUE_84_B Register .............................................................................................. 2670
16-713. QUEUE_84_C Register .............................................................................................. 2671

16-714. QUEUE_84_D Register .............................................................................................. 2672
54
List of Figures

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16-715. QUEUE_85_A Register .............................................................................................. 2673

16-716. QUEUE_85_B Register .............................................................................................. 2674
16-717. QUEUE_85_C Register .............................................................................................. 2675

16-718. QUEUE_85_D Register .............................................................................................. 2676
16-719. QUEUE_86_A Register .............................................................................................. 2677
16-720. QUEUE_86_B Register .............................................................................................. 2678
16-721. QUEUE_86_C Register .............................................................................................. 2679

16-722. QUEUE_86_D Register .............................................................................................. 2680
16-723. QUEUE_87_A Register .............................................................................................. 2681
16-724. QUEUE_87_B Register .............................................................................................. 2682
16-725. QUEUE_87_C Register .............................................................................................. 2683

16-726. QUEUE_87_D Register .............................................................................................. 2684
16-727. QUEUE_88_A Register .............................................................................................. 2685
16-728. QUEUE_88_B Register .............................................................................................. 2686
16-729. QUEUE_88_C Register .............................................................................................. 2687

16-730. QUEUE_88_D Register .............................................................................................. 2688
16-731. QUEUE_89_A Register .............................................................................................. 2689
16-732. QUEUE_89_B Register .............................................................................................. 2690
16-733. QUEUE_89_C Register .............................................................................................. 2691

16-734. QUEUE_89_D Register .............................................................................................. 2692
16-735. QUEUE_90_A Register .............................................................................................. 2693
16-736. QUEUE_90_B Register .............................................................................................. 2694
16-737. QUEUE_90_C Register .............................................................................................. 2695

16-738. QUEUE_90_D Register .............................................................................................. 2696
16-739. QUEUE_91_A Register .............................................................................................. 2697
16-740. QUEUE_91_B Register .............................................................................................. 2698
16-741. QUEUE_91_C Register .............................................................................................. 2699

16-742. QUEUE_91_D Register .............................................................................................. 2700
16-743. QUEUE_92_A Register .............................................................................................. 2701
16-744. QUEUE_92_B Register .............................................................................................. 2702
16-745. QUEUE_92_C Register .............................................................................................. 2703

16-746. QUEUE_92_D Register .............................................................................................. 2704
16-747. QUEUE_93_A Register .............................................................................................. 2705
16-748. QUEUE_93_B Register .............................................................................................. 2706
16-749. QUEUE_93_C Register .............................................................................................. 2707

16-750. QUEUE_93_D Register .............................................................................................. 2708
16-751. QUEUE_94_A Register .............................................................................................. 2709
16-752. QUEUE_94_B Register .............................................................................................. 2710
16-753. QUEUE_94_C Register .............................................................................................. 2711

16-754. QUEUE_94_D Register .............................................................................................. 2712
16-755. QUEUE_95_A Register .............................................................................................. 2713
16-756. QUEUE_95_B Register .............................................................................................. 2714
16-757. QUEUE_95_C Register .............................................................................................. 2715

16-758. QUEUE_95_D Register .............................................................................................. 2716
16-759. QUEUE_96_A Register .............................................................................................. 2717
16-760. QUEUE_96_B Register .............................................................................................. 2718
16-761. QUEUE_96_C Register .............................................................................................. 2719

16-762. QUEUE_96_D Register .............................................................................................. 2720
16-763. QUEUE_97_A Register .............................................................................................. 2721
List of Figures
55
www.ti.com
16-764. QUEUE_97_B Register .............................................................................................. 2722
16-765. QUEUE_97_C Register .............................................................................................. 2723

16-766. QUEUE_97_D Register .............................................................................................. 2724
16-767. QUEUE_98_A Register .............................................................................................. 2725
16-768. QUEUE_98_B Register .............................................................................................. 2726
16-769. QUEUE_98_C Register .............................................................................................. 2727

16-770. QUEUE_98_D Register .............................................................................................. 2728
16-771. QUEUE_99_A Register .............................................................................................. 2729
16-772. QUEUE_99_B Register .............................................................................................. 2730
16-773. QUEUE_99_C Register .............................................................................................. 2731

16-774. QUEUE_99_D Register .............................................................................................. 2732
16-775. QUEUE_100_A Register ............................................................................................. 2733

16-776. QUEUE_100_B Register ............................................................................................. 2734
16-777. QUEUE_100_C Register ............................................................................................. 2735
16-778. QUEUE_100_D Register ............................................................................................. 2736
16-779. QUEUE_101_A Register ............................................................................................. 2737

16-780. QUEUE_101_B Register ............................................................................................. 2738
16-781. QUEUE_101_C Register ............................................................................................. 2739
16-782. QUEUE_101_D Register ............................................................................................. 2740
16-783. QUEUE_102_A Register ............................................................................................. 2741

16-784. QUEUE_102_B Register ............................................................................................. 2742
16-785. QUEUE_102_C Register ............................................................................................. 2743
16-786. QUEUE_102_D Register ............................................................................................. 2744
16-787. QUEUE_103_A Register ............................................................................................. 2745

16-788. QUEUE_103_B Register ............................................................................................. 2746
16-789. QUEUE_103_C Register ............................................................................................. 2747
16-790. QUEUE_103_D Register ............................................................................................. 2748
16-791. QUEUE_104_A Register ............................................................................................. 2749

16-792. QUEUE_104_B Register ............................................................................................. 2750
16-793. QUEUE_104_C Register ............................................................................................. 2751
16-794. QUEUE_104_D Register ............................................................................................. 2752
16-795. QUEUE_105_A Register ............................................................................................. 2753

16-796. QUEUE_105_B Register ............................................................................................. 2754
16-797. QUEUE_105_C Register ............................................................................................. 2755
16-798. QUEUE_105_D Register ............................................................................................. 2756
16-799. QUEUE_106_A Register ............................................................................................. 2757

16-800. QUEUE_106_B Register ............................................................................................. 2758
16-801. QUEUE_106_C Register ............................................................................................. 2759
16-802. QUEUE_106_D Register ............................................................................................. 2760
16-803. QUEUE_107_A Register ............................................................................................. 2761

16-804. QUEUE_107_B Register ............................................................................................. 2762
16-805. QUEUE_107_C Register ............................................................................................. 2763
16-806. QUEUE_107_D Register ............................................................................................. 2764
16-807. QUEUE_108_A Register ............................................................................................. 2765

16-808. QUEUE_108_B Register ............................................................................................. 2766
16-809. QUEUE_108_C Register ............................................................................................. 2767
16-810. QUEUE_108_D Register ............................................................................................. 2768
16-811. QUEUE_109_A Register ............................................................................................. 2769

16-812. QUEUE_109_B Register ............................................................................................. 2770
56
List of Figures

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16-813. QUEUE_109_C Register ............................................................................................. 2771
16-814. QUEUE_109_D Register ............................................................................................. 2772
16-815. QUEUE_110_A Register ............................................................................................. 2773

16-816. QUEUE_110_B Register ............................................................................................. 2774
16-817. QUEUE_110_C Register ............................................................................................. 2775
16-818. QUEUE_110_D Register ............................................................................................. 2776
16-819. QUEUE_111_A Register ............................................................................................. 2777

16-820. QUEUE_111_B Register ............................................................................................. 2778
16-821. QUEUE_111_C Register ............................................................................................. 2779
16-822. QUEUE_111_D Register ............................................................................................. 2780
16-823. QUEUE_112_A Register ............................................................................................. 2781

16-824. QUEUE_112_B Register ............................................................................................. 2782
16-825. QUEUE_112_C Register ............................................................................................. 2783
16-826. QUEUE_112_D Register ............................................................................................. 2784
16-827. QUEUE_113_A Register ............................................................................................. 2785

16-828. QUEUE_113_B Register ............................................................................................. 2786
16-829. QUEUE_113_C Register ............................................................................................. 2787
16-830. QUEUE_113_D Register ............................................................................................. 2788
16-831. QUEUE_114_A Register ............................................................................................. 2789

16-832. QUEUE_114_B Register ............................................................................................. 2790
16-833. QUEUE_114_C Register ............................................................................................. 2791
16-834. QUEUE_114_D Register ............................................................................................. 2792
16-835. QUEUE_115_A Register ............................................................................................. 2793

16-836. QUEUE_115_B Register ............................................................................................. 2794
16-837. QUEUE_115_C Register ............................................................................................. 2795
16-838. QUEUE_115_D Register ............................................................................................. 2796
16-839. QUEUE_116_A Register ............................................................................................. 2797

16-840. QUEUE_116_B Register ............................................................................................. 2798
16-841. QUEUE_116_C Register ............................................................................................. 2799
16-842. QUEUE_116_D Register ............................................................................................. 2800
16-843. QUEUE_117_A Register ............................................................................................. 2801

16-844. QUEUE_117_B Register ............................................................................................. 2802
16-845. QUEUE_117_C Register ............................................................................................. 2803
16-846. QUEUE_117_D Register ............................................................................................. 2804
16-847. QUEUE_118_A Register ............................................................................................. 2805

16-848. QUEUE_118_B Register ............................................................................................. 2806
16-849. QUEUE_118_C Register ............................................................................................. 2807
16-850. QUEUE_118_D Register ............................................................................................. 2808
16-851. QUEUE_119_A Register ............................................................................................. 2809

16-852. QUEUE_119_B Register ............................................................................................. 2810
16-853. QUEUE_119_C Register ............................................................................................. 2811
16-854. QUEUE_119_D Register ............................................................................................. 2812
16-855. QUEUE_120_A Register ............................................................................................. 2813

16-856. QUEUE_120_B Register ............................................................................................. 2814
16-857. QUEUE_120_C Register ............................................................................................. 2815
16-858. QUEUE_120_D Register ............................................................................................. 2816
16-859. QUEUE_121_A Register ............................................................................................. 2817

16-860. QUEUE_121_B Register ............................................................................................. 2818
16-861. QUEUE_121_C Register ............................................................................................. 2819
List of Figures
57
www.ti.com
16-862. QUEUE_121_D Register ............................................................................................. 2820
16-863. QUEUE_122_A Register ............................................................................................. 2821

16-864. QUEUE_122_B Register ............................................................................................. 2822
16-865. QUEUE_122_C Register ............................................................................................. 2823
16-866. QUEUE_122_D Register ............................................................................................. 2824
16-867. QUEUE_123_A Register ............................................................................................. 2825

16-868. QUEUE_123_B Register ............................................................................................. 2826
16-869. QUEUE_123_C Register ............................................................................................. 2827
16-870. QUEUE_123_D Register ............................................................................................. 2828
16-871. QUEUE_124_A Register ............................................................................................. 2829

16-872. QUEUE_124_B Register ............................................................................................. 2830
16-873. QUEUE_124_C Register ............................................................................................. 2831
16-874. QUEUE_124_D Register ............................................................................................. 2832
16-875. QUEUE_125_A Register ............................................................................................. 2833

16-876. QUEUE_125_B Register ............................................................................................. 2834
16-877. QUEUE_125_C Register ............................................................................................. 2835
16-878. QUEUE_125_D Register ............................................................................................. 2836
16-879. QUEUE_126_A Register ............................................................................................. 2837

16-880. QUEUE_126_B Register ............................................................................................. 2838
16-881. QUEUE_126_C Register ............................................................................................. 2839
16-882. QUEUE_126_D Register ............................................................................................. 2840
16-883. QUEUE_127_A Register ............................................................................................. 2841

16-884. QUEUE_127_B Register ............................................................................................. 2842
16-885. QUEUE_127_C Register ............................................................................................. 2843
16-886. QUEUE_127_D Register ............................................................................................. 2844
16-887. QUEUE_128_A Register ............................................................................................. 2845

16-888. QUEUE_128_B Register ............................................................................................. 2846
16-889. QUEUE_128_C Register ............................................................................................. 2847
16-890. QUEUE_128_D Register ............................................................................................. 2848
16-891. QUEUE_129_A Register ............................................................................................. 2849

16-892. QUEUE_129_B Register ............................................................................................. 2850
16-893. QUEUE_129_C Register ............................................................................................. 2851
16-894. QUEUE_129_D Register ............................................................................................. 2852
16-895. QUEUE_130_A Register ............................................................................................. 2853

16-896. QUEUE_130_B Register ............................................................................................. 2854
16-897. QUEUE_130_C Register ............................................................................................. 2855
16-898. QUEUE_130_D Register ............................................................................................. 2856
16-899. QUEUE_131_A Register ............................................................................................. 2857

16-900. QUEUE_131_B Register ............................................................................................. 2858
16-901. QUEUE_131_C Register ............................................................................................. 2859
16-902. QUEUE_131_D Register ............................................................................................. 2860
16-903. QUEUE_132_A Register ............................................................................................. 2861

16-904. QUEUE_132_B Register ............................................................................................. 2862
16-905. QUEUE_132_C Register ............................................................................................. 2863
16-906. QUEUE_132_D Register ............................................................................................. 2864
16-907. QUEUE_133_A Register ............................................................................................. 2865

16-908. QUEUE_133_B Register ............................................................................................. 2866
16-909. QUEUE_133_C Register ............................................................................................. 2867
16-910. QUEUE_133_D Register ............................................................................................. 2868
58
List of Figures

www.ti.com
16-911. QUEUE_134_A Register ............................................................................................. 2869
16-912. QUEUE_134_B Register ............................................................................................. 2870

16-913. QUEUE_134_C Register ............................................................................................. 2871
16-914. QUEUE_134_D Register ............................................................................................. 2872
16-915. QUEUE_135_A Register ............................................................................................. 2873

16-916. QUEUE_135_B Register ............................................................................................. 2874
16-917. QUEUE_135_C Register ............................................................................................. 2875
16-918. QUEUE_135_D Register ............................................................................................. 2876
16-919. QUEUE_136_A Register ............................................................................................. 2877

16-920. QUEUE_136_B Register ............................................................................................. 2878
16-921. QUEUE_136_C Register ............................................................................................. 2879
16-922. QUEUE_136_D Register ............................................................................................. 2880
16-923. QUEUE_137_A Register ............................................................................................. 2881

16-924. QUEUE_137_B Register ............................................................................................. 2882
16-925. QUEUE_137_C Register ............................................................................................. 2883
16-926. QUEUE_137_D Register ............................................................................................. 2884
16-927. QUEUE_138_A Register ............................................................................................. 2885

16-928. QUEUE_138_B Register ............................................................................................. 2886
16-929. QUEUE_138_C Register ............................................................................................. 2887
16-930. QUEUE_138_D Register ............................................................................................. 2888
16-931. QUEUE_139_A Register ............................................................................................. 2889

16-932. QUEUE_139_B Register ............................................................................................. 2890
16-933. QUEUE_139_C Register ............................................................................................. 2891
16-934. QUEUE_139_D Register ............................................................................................. 2892
16-935. QUEUE_140_A Register ............................................................................................. 2893

16-936. QUEUE_140_B Register ............................................................................................. 2894
16-937. QUEUE_140_C Register ............................................................................................. 2895
16-938. QUEUE_140_D Register ............................................................................................. 2896
16-939. QUEUE_141_A Register ............................................................................................. 2897

16-940. QUEUE_141_B Register ............................................................................................. 2898
16-941. QUEUE_141_C Register ............................................................................................. 2899
16-942. QUEUE_141_D Register ............................................................................................. 2900
16-943. QUEUE_142_A Register ............................................................................................. 2901

16-944. QUEUE_142_B Register ............................................................................................. 2902
16-945. QUEUE_142_C Register ............................................................................................. 2903
16-946. QUEUE_142_D Register ............................................................................................. 2904
16-947. QUEUE_143_A Register ............................................................................................. 2905

16-948. QUEUE_143_B Register ............................................................................................. 2906
16-949. QUEUE_143_C Register ............................................................................................. 2907
16-950. QUEUE_143_D Register ............................................................................................. 2908
16-951. QUEUE_144_A Register ............................................................................................. 2909

16-952. QUEUE_144_B Register ............................................................................................. 2910
16-953. QUEUE_144_C Register ............................................................................................. 2911
16-954. QUEUE_144_D Register ............................................................................................. 2912
16-955. QUEUE_145_A Register ............................................................................................. 2913

16-956. QUEUE_145_B Register ............................................................................................. 2914
16-957. QUEUE_145_C Register ............................................................................................. 2915
16-958. QUEUE_145_D Register ............................................................................................. 2916
16-959. QUEUE_146_A Register ............................................................................................. 2917

List of Figures
59
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16-960. QUEUE_146_B Register ............................................................................................. 2918
16-961. QUEUE_146_C Register ............................................................................................. 2919

16-962. QUEUE_146_D Register ............................................................................................. 2920
16-963. QUEUE_147_A Register ............................................................................................. 2921

16-964. QUEUE_147_B Register ............................................................................................. 2922
16-965. QUEUE_147_C Register ............................................................................................. 2923
16-966. QUEUE_147_D Register ............................................................................................. 2924
16-967. QUEUE_148_A Register ............................................................................................. 2925

16-968. QUEUE_148_B Register ............................................................................................. 2926
16-969. QUEUE_148_C Register ............................................................................................. 2927
16-970. QUEUE_148_D Register ............................................................................................. 2928
16-971. QUEUE_149_A Register ............................................................................................. 2929

16-972. QUEUE_149_B Register ............................................................................................. 2930
16-973. QUEUE_149_C Register ............................................................................................. 2931
16-974. QUEUE_149_D Register ............................................................................................. 2932
16-975. QUEUE_150_A Register ............................................................................................. 2933

16-976. QUEUE_150_B Register ............................................................................................. 2934
16-977. QUEUE_150_C Register ............................................................................................. 2935
16-978. QUEUE_150_D Register ............................................................................................. 2936
16-979. QUEUE_151_A Register ............................................................................................. 2937

16-980. QUEUE_151_B Register ............................................................................................. 2938
16-981. QUEUE_151_C Register ............................................................................................. 2939
16-982. QUEUE_151_D Register ............................................................................................. 2940
16-983. QUEUE_152_A Register ............................................................................................. 2941

16-984. QUEUE_152_B Register ............................................................................................. 2942
16-985. QUEUE_152_C Register ............................................................................................. 2943
16-986. QUEUE_152_D Register ............................................................................................. 2944
16-987. QUEUE_153_A Register ............................................................................................. 2945

16-988. QUEUE_153_B Register ............................................................................................. 2946
16-989. QUEUE_153_C Register ............................................................................................. 2947
16-990. QUEUE_153_D Register ............................................................................................. 2948
16-991. QUEUE_154_A Register ............................................................................................. 2949

16-992. QUEUE_154_B Register ............................................................................................. 2950
16-993. QUEUE_154_C Register ............................................................................................. 2951
16-994. QUEUE_154_D Register ............................................................................................. 2952
16-995. QUEUE_155_A Register ............................................................................................. 2953

16-996. QUEUE_155_B Register ............................................................................................. 2954
16-997. QUEUE_155_C Register ............................................................................................. 2955
16-998. QUEUE_155_D Register ............................................................................................. 2956
16-999. QUEUE_0_STATUS_A Register .................................................................................... 2957

16-1000. QUEUE_0_STATUS_B Register .................................................................................. 2958
16-1001. QUEUE_0_STATUS_C Register .................................................................................. 2959
16-1002. QUEUE_1_STATUS_A Register .................................................................................. 2960
60
List of Figures

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16-1029. QUEUE_10_STATUS_A Register ................................................................................. 2987

16-1030. QUEUE_10_STATUS_B Register ................................................................................. 2988
16-1031. QUEUE_10_STATUS_C Register................................................................................. 2989
List of Figures
61
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62
List of Figures

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List of Figures
63
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64
List of Figures

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List of Figures
65
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16-1299. QUEUE_100_STATUS_A Register ............................................................................... 3257
16-1300. QUEUE_100_STATUS_B Register ............................................................................... 3258

16-1301. QUEUE_100_STATUS_C Register ............................................................................... 3259
66
List of Figures

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List of Figures
67
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68
List of Figures

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List of Figures
69
www.ti.com

17-1.
17-2.
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
Mailbox Integration ..................................................................................................... 3427
Mailbox Block Diagram ................................................................................................ 3429
REVISION Register .................................................................................................... 3438

SYSCONFIG Register ................................................................................................. 3439
MESSAGE_0 Register ................................................................................................. 3440
17-10. MESSAGE_5 Register ................................................................................................. 3445

3448
17-14. FIFOSTATUS_1 Register
3449
17-15.
3450
17-16.
17-17.
17-18.
17-19.
17-20.
17-21.
17-22.
17-23.
17-24.
17-25.
17-26.
17-27.
17-28.
17-29.
17-30.
17-31.
17-32.
70
.............................................................................................
.............................................................................................
FIFOSTATUS_2 Register .............................................................................................
MSGSTATUS_0 Register .............................................................................................
IRQSTATUS_RAW_0 Register .......................................................................................
IRQSTATUS_CLR_0 Register ........................................................................................
IRQENABLE_SET_0 Register ........................................................................................
IRQENABLE_CLR_0 Register ........................................................................................
17-13. FIFOSTATUS_0 Register
List of Figures
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3466
3468
3470

www.ti.com
17-33. IRQSTATUS_RAW_1 Register ....................................................................................... 3472
17-34. IRQSTATUS_CLR_1 Register ........................................................................................ 3474

17-35. IRQENABLE_SET_1 Register ........................................................................................ 3476
17-36. IRQENABLE_CLR_1 Register ........................................................................................ 3478



17-45. REV Register............................................................................................................ 3499
17-46. SYSCONFIG Register ................................................................................................. 3500
17-47. SYSTATUS Register ................................................................................................... 3501
...............................................................................................
LOCK_REG_1 Register ...............................................................................................
LOCK_REG_10 Register ..............................................................................................
MMCHS Module SDIO Application ...................................................................................
MMCHS SD (4-bit) Card Application .................................................................................
17-48. LOCK_REG_0 Register
3502
17-49.
3503
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
17-58.
17-59.
17-60.
17-61.
17-62.
17-63.
17-64.
17-65.
17-66.
17-67.
17-68.
17-69.
17-70.
17-71.
17-72.
17-73.
17-74.
17-75.
17-76.
17-77.
17-78.
17-79.
18-1.
18-2.

List of Figures
3504
3505
3506
3507
3508
3509
3510
3511
3512
3513
3514
3515
3516
3517
3518
3519
3520
3521
3522
3523
3524
3525
3526
3527
3528
3529
3530
3531
3532
3533
3536
3536
71
www.ti.com
18-3.
18-4.
18-5.
18-6.
MMC/SD1/2 Connectivity to an MMC/SD Card
....................................................................
3540
MMC/SD0 Connectivity to an MMC/SD Card ....................................................................... 3540

Sequential Read Operation (MMC Cards Only) .................................................................... 3543
18-7.
Sequential Write Operation (MMC Cards Only) .................................................................... 3543
18-8.
Multiple Block Read Operation (MMC Cards Only)
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
18-24.
18-25.
18-26.
18-27.
18-28.
18-29.
18-30.
18-31.
18-32.
18-33.
18-34.
18-35.
18-36.
18-37.
18-38.
18-39.
18-40.
18-41.
18-42.
18-43.
18-44.
18-45.
18-46.
18-47.
18-48.
18-49.
18-50.
18-51.
72
MMCHS Module MMC Application ................................................................................... 3537
...............................................................
Multiple Block Write Operation (MMC Cards Only) ...............................................................
Command Token Format ..............................................................................................
48-Bit Response Packet (R1, R3, R4, R5, R6) .....................................................................
136-Bit Response Packet (R2) .......................................................................................
Data Packet for Sequential Transfer (1-Bit) ........................................................................
Data Packet for Block Transfer (1-Bit) ..............................................................................
Data Packet for Block Transfer (4-Bit) ...............................................................................
Data Packet for Block Transfer (8-Bit) ...............................................................................
DMA Receive Mode ....................................................................................................
DMA Transmit Mode ...................................................................................................
Buffer Management for a Write .......................................................................................
Buffer Management for a Read .......................................................................................
Busy Timeout for R1b, R5b Responses .............................................................................
Busy Timeout After Write CRC Status ...............................................................................
Write CRC Status Timeout ............................................................................................
Read Data Timeout ....................................................................................................
Boot Acknowledge Timeout When Using CMD0 ...................................................................
Boot Acknowledge Timeout When CMD Held Low ................................................................
Auto CMD12 Timing During Write Transfer .........................................................................
Auto Command 12 Timings During Read Transfer ................................................................
Output Driven on Falling Edge........................................................................................
Output Driven on Rising Edge ........................................................................................
Boot Mode With CMD0 ................................................................................................
Boot Mode With CMD Line Tied to 0 ................................................................................
MMC/SD/SDIO Controller Software Reset Flow ...................................................................
MMC/SD/SDIO Controller Bus Configuration Flow ................................................................
MMC/SD/SDIO Controller Card Identification and Selection - Part 1............................................
MMC/SD/SDIO Controller Card Identification and Selection - Part 2............................................
System Configuration Register (SD_SYSCONFIG)................................................................
System Status Register (SD_SYSSTATUS) ........................................................................
Card Status Response Error (SD_CSRE)...........................................................................
System Test Register (SD_SYSTEST) ..............................................................................
Configuration Register (SD_CON) ...................................................................................
Power Counter Register (SD_PWCNT) .............................................................................
Card Status Response Error (SD_SDMASA) .......................................................................
Transfer Length Configuration Register (SD_BLK) ................................................................
Command Argument Register (SD_ARG) ..........................................................................
Command and Transfer Mode Register (SD_CMD) ...............................................................
Command Response[31:0] Register (SD_RSP10).................................................................
Command Response[63:32] Register (SD_RSP32) ...............................................................
Command Response[95:64] Register (SD_RSP54) ...............................................................
Command Response[127:96] Register (SD_RSP76)..............................................................
Data Register (SD_DATA) ............................................................................................
List of Figures
3544
3544
3545
3545
3545
3546
3546
3546
3547
3554
3555
3557
3558
3561
3561
3562
3562
3563
3563
3565
3566
3568
3569
3570
3570
3574
3575
3576
3577
3579
3581
3581
3582
3585
3588
3588
3589
3590
3590
3594
3594
3595
3595
3596

www.ti.com
..............................................................................
Control Register (SD_HCTL)..........................................................................................
SD System Control Register (SD_SYSCTL) ........................................................................
Interrupt Status Register (SD_STAT) ................................................................................
Interrupt SD Enable Register (SD_IE) ...............................................................................
Interrupt Signal Enable Register (SD_ISE) .........................................................................
Auto CMD12 Error Status Register (SD_AC12) ....................................................................
Capabilities Register (SD_CAPA) ....................................................................................
Maximum Current Capabilities Register (SD_CUR_CAPA) ......................................................
Interrupt Signal Enable Register (SD_ISE) .........................................................................
ADMA Error Status Register (SD_ADMAES) .......................................................................
ADMA System Address Low Bits (SD_ADMASAL) ................................................................
ADMA System Address High Bits Register (SD_ADMASAH) ....................................................
Versions Register (SD_REV) .........................................................................................
UART/IrDA Module UART Application ...........................................................................
UART/IrDA Module IrDA/CIR Application ........................................................................
UART/IrDA/CIR Functional Specification Block Diagram .........................................................
FIFO Management Registers .........................................................................................
RX FIFO Interrupt Request Generation .............................................................................
TX FIFO Interrupt Request Generation ..............................................................................
Receive FIFO DMA Request Generation (32 Characters) ........................................................
Transmit FIFO DMA Request Generation (56 Spaces) ...........................................................
Transmit FIFO DMA Request Generation (8 Spaces) .............................................................
Transmit FIFO DMA Request Generation (1 Space) ..............................................................
18-52. Present State Register (SD_PSTATE)

18-53.
18-54.
18-55.
18-56.
18-57.
18-58.
18-59.
18-60.
18-61.
18-62.
18-63.
18-64.
18-65.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
3597
3600
3603
3605
3610
3613
3616
3617
3619
3620
3622
3623
3623
3624
3628
3628
3633
3638
3640
3641
3642
3643
3644
3644
19-11. Transmit FIFO DMA Request Generation Using Direct TX DMA Threshold Programming. (Threshold = 3;
Spaces = 8) ............................................................................................................. 3645
19-12. DMA Transmission ..................................................................................................... 3645

19-13. DMA Reception ......................................................................................................... 3646
19-14. UART Data Format ..................................................................................................... 3653

19-15. Baud Rate Generation ................................................................................................. 3653
19-16. IrDA SIR Frame Format ............................................................................................... 3659
19-17. IrDA Encoding Mechanism ............................................................................................ 3660

19-18. IrDA Decoding Mechanism ............................................................................................ 3661
19-19. SIR Free Format Mode ................................................................................................ 3662
19-20. MIR Transmit Frame Format .......................................................................................... 3662
19-21. MIR BAUD Rate Adjustment Mechanism ........................................................................... 3663

19-22. SIP Pulse ................................................................................................................ 3663
..........................................................................................
Baud Rate Generator ..................................................................................................
RC-5 Bit Encoding ......................................................................................................
SIRC Bit Encoding .....................................................................................................
RC-5 Standard Packet Format .......................................................................................
SIRC Packet Format ...................................................................................................
SIRC Bit Transmission Example .....................................................................................
CIR Mode Block Components ........................................................................................
CIR Pulse Modulation ..................................................................................................
CIR Modulation Duty Cycle ...........................................................................................
Variable Pulse Duration Definitions ..................................................................................
Receiver Holding Register (RHR) ....................................................................................
19-23. FIR Transmit Frame Format

19-24.
19-25.
19-26.
19-27.
19-28.
19-29.
19-30.
19-31.
19-32.
19-33.
19-34.

List of Figures
3663
3664
3668
3669
3669
3669
3670
3670
3672
3672
3674
3686
73
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19-35. Transmit Holding Register (THR)..................................................................................... 3686
19-36. UART Interrupt Enable Register (IER) ............................................................................... 3687

19-37. IrDA Interrupt Enable Register (IER)................................................................................. 3688
19-38. CIR Interrupt Enable Register (IER) ................................................................................. 3689
19-39. UART Interrupt Identification Register (IIR) ......................................................................... 3690
19-40. IrDA Interrupt Identification Register (IIR) ........................................................................... 3691
19-41. CIR Interrupt Identification Register (IIR) ............................................................................ 3692
19-42. FIFO Control Register (FCR) ......................................................................................... 3693
3694
19-44.
3695
19-45.
19-46.
19-47.
19-48.
19-49.
19-50.
19-51.
19-52.
19-53.
19-54.
19-55.
19-56.
19-57.
19-58.
19-59.
19-60.
19-61.
19-62.
19-63.
19-64.
19-65.
19-66.
19-67.
19-68.
19-69.
19-70.
19-71.
19-72.
19-73.
19-74.
19-75.
19-76.
19-77.
19-78.
19-79.
19-80.
19-81.
19-82.
19-83.
74
..........................................................................................
Modem Control Register (MCR) ......................................................................................
UART Line Status Register (LSR)....................................................................................
IrDA Line Status Register (LSR) .....................................................................................
CIR Line Status Register (LSR) ......................................................................................
Modem Status Register (MSR) .......................................................................................
Transmission Control Register (TCR) ...............................................................................
Scratchpad Register (SPR) ...........................................................................................
Trigger Level Register (TLR) ..........................................................................................
Mode Definition Register 1 (MDR1) ..................................................................................
Mode Definition Register 2 (MDR2) ..................................................................................
Status FIFO Line Status Register (SFLSR) .........................................................................
RESUME Register......................................................................................................
Status FIFO Register Low (SFREGL) ...............................................................................
Status FIFO Register High (SFREGH) ..............................................................................
BOF Control Register (BLR) ..........................................................................................
Auxiliary Control Register (ACREG) .................................................................................
Supplementary Control Register (SCR) .............................................................................
Supplementary Status Register (SSR) ..............................................................................
BOF Length Register (EBLR) .........................................................................................
Module Version Register (MVR) ......................................................................................
System Configuration Register (SYSC) .............................................................................
System Status Register (SYSS) ......................................................................................
Wake-Up Enable Register (WER) ....................................................................................
Carrier Frequency Prescaler Register (CFPS) .....................................................................
Divisor Latches Low Register (DLL) .................................................................................
Divisor Latches High Register (DLH) ................................................................................
Enhanced Feature Register (EFR) ...................................................................................
XON1/ADDR1 Register ................................................................................................
XON2/ADDR2 Register ................................................................................................
XOFF1 Register ........................................................................................................
XOFF2 Register ........................................................................................................
Transmit Frame Length Low Register (TXFLL) ....................................................................
Transmit Frame Length High Register (TXFLH) ...................................................................
Received Frame Length Low Register (RXFLL) ...................................................................
Received Frame Length High Register (RXFLH) ..................................................................
UART Autobauding Status Register (UASR) .......................................................................
RXFIFO_LVL Register .................................................................................................
TXFIFO_LVL Register .................................................................................................
IER2 Register ...........................................................................................................
ISR2 Register ...........................................................................................................
19-43. Line Control Register (LCR)
List of Figures
3696
3697
3698
3699
3700
3700
3701
3702
3703
3704
3704
3705
3705
3706
3707
3708
3709
3710
3711
3712
3712
3713
3714
3715
3715
3716
3717
3717
3718
3718
3719
3719
3720
3720
3721
3722
3723
3724
3725

www.ti.com
19-84. FREQ_SEL Register ................................................................................................... 3726

19-85. Mode Definition Register 3 (MDR3) Register ....................................................................... 3727
20-1.
20-2.
20-3.
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
Timer Block Diagram ................................................................................................... 3730
TCRR Timing Value .................................................................................................... 3733

Capture Wave Example for CAPT_MODE = 0 ..................................................................... 3734
Capture Wave Example for CAPT_MODE = 1 ..................................................................... 3735
Timing Diagram of Pulse-Width Modulation with SCPWM = 0 ................................................... 3736

Timing Diagram of Pulse-Width Modulation with SCPWM = 1 ................................................... 3737
TIDR Register ........................................................................................................... 3743

TIOCP_CFG Register .................................................................................................. 3744
IRQSTATUS_RAW Register .......................................................................................... 3745
20-10. IRQSTATUS Register .................................................................................................. 3746

20-11. IRQENABLE_SET Register ........................................................................................... 3747
20-12. IRQENABLE_CLR Register ........................................................................................... 3748

20-13. IRQWAKEEN Register ................................................................................................. 3749
20-14. TCLR Register .......................................................................................................... 3750

20-15. TCRR Register .......................................................................................................... 3752
20-16. TLDR Register .......................................................................................................... 3753

20-17. TTGR Register .......................................................................................................... 3754
20-18. TWPS Register ......................................................................................................... 3755
.........................................................................................................
TCAR1 Register ........................................................................................................
TSICR Register .........................................................................................................
TCAR2 Register ........................................................................................................
Block Diagram ..........................................................................................................
DMTimer 1 ms Integration .............................................................................................
TCRR Timing Value ....................................................................................................
1ms Module Block Diagram ...........................................................................................
Capture Wave Example for CAPT_MODE 0 .......................................................................
Capture Wave Example for CAPT_MODE 1 .......................................................................
Timing Diagram of Pulse-Width Modulation, SCPWM Bit = 0 ....................................................
Timing Diagram of Pulse-Width Modulation, SCPWM Bit = 1 ....................................................
Wake-up Request Generation ........................................................................................
TIDR Register ...........................................................................................................
TIOCP_CFG Register ..................................................................................................
TISTAT Register ........................................................................................................
TISR Register ...........................................................................................................
TIER Register ...........................................................................................................
TWER Register .........................................................................................................
TCLR Register ..........................................................................................................
TCRR Register ..........................................................................................................
TLDR Register ..........................................................................................................
TTGR Register ..........................................................................................................
TWPS Register .........................................................................................................
TMAR Register .........................................................................................................
TCAR1 Register ........................................................................................................
TSICR Register .........................................................................................................
TCAR2 Register ........................................................................................................
TPIR Register ...........................................................................................................
20-19. TMAR Register

20-20.
20-21.
20-22.
20-23.
20-24.
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
20-39.
20-40.
20-41.
20-42.
20-43.
20-44.
20-45.
20-46.
20-47.

List of Figures
3756
3757
3758
3759
3761
3762
3764
3765
3767
3767
3769
3769
3771
3774
3775
3776
3777
3778
3779
3780
3782
3783
3784
3785
3787
3788
3789
3790
3791
75
www.ti.com
20-48. TNIR Register ........................................................................................................... 3792
20-49. TCVR Register .......................................................................................................... 3793

20-50. TOCR Register
.........................................................................................................
3794
20-51. TOWR Register ......................................................................................................... 3795

20-52. RTC Block Diagram .................................................................................................... 3798
20-53. RTC Functional Block Diagram ....................................................................................... 3798

20-54. Kick Register State Machine Diagram ............................................................................... 3801
20-55. Flow Control for Updating RTC Registers ........................................................................... 3803
.............................................................................................
SECONDS_REG Register ............................................................................................
MINUTES_REG Register ..............................................................................................
HOURS_REG Register ................................................................................................
DAYS_REG Register ..................................................................................................
MONTHS_REG Register ..............................................................................................
YEARS_REG Register .................................................................................................
WEEKS_REG Register ................................................................................................
ALARM_SECONDS_REG Register ..................................................................................
ALARM_MINUTES_REG Register ...................................................................................
ALARM_HOURS_REG Register .....................................................................................
ALARM_DAYS_REG Register ........................................................................................
ALARM_MONTHS_REG Register ...................................................................................
ALARM_YEARS_REG Register ......................................................................................
RTC_CTRL_REG Register ............................................................................................
RTC_STATUS_REG Register ........................................................................................
RTC_INTERRUPTS_REG Register .................................................................................
RTC_COMP_LSB_REG Register ....................................................................................
RTC_COMP_MSB_REG Register ...................................................................................
RTC_OSC_REG Register .............................................................................................
RTC_SCRATCH0_REG Register ....................................................................................
KICK0R Register .......................................................................................................
KICK1R Register .......................................................................................................
RTC_REVISION Register .............................................................................................
RTC_SYSCONFIG Register ..........................................................................................
RTC_IRQWAKEEN Register..........................................................................................
ALARM2_SECONDS_REG Register ................................................................................
ALARM2_MINUTES_REG Register .................................................................................
ALARM2_HOURS_REG Register ....................................................................................
ALARM2_DAYS_REG Register ......................................................................................
ALARM2_MONTHS_REG Register ..................................................................................
ALARM2_YEARS_REG Register ....................................................................................
RTC_PMIC Register ...................................................................................................
RTC_DEBOUNCE Register ...........................................................................................
32-Bit Watchdog Timer Functional Block Diagram.................................................................
Watchdog Timers General Functional View ........................................................................
WDT_WIDR Register ..................................................................................................
WDT_WDSC Register .................................................................................................
WDT_WDST Register..................................................................................................
20-56. Compensation Illustration

20-57.
20-58.
20-59.
20-60.
20-61.
20-62.
20-63.
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
20-71.
20-72.
20-73.
20-74.
20-75.
20-76.
20-77.
20-78.
20-79.
20-80.
20-81.
20-82.
20-83.
20-84.
20-85.
20-86.
20-87.
20-88.
20-89.
20-90.
20-91.
20-92.
20-93.
20-94.
20-95.
20-96.
76
List of Figures
3804
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842
3843
3846
3847
3855
3855
3856

www.ti.com
..................................................................................................
20-98. WDT_WIER Register ..................................................................................................
20-99. WDT_WCLR Register..................................................................................................
20-100. WDT_WCRR Register ................................................................................................
20-101. WDT_WLDR Register ................................................................................................
20-102. WDT_WTGR Register ................................................................................................
20-103. WDT_WWPS Register ...............................................................................................
20-104. WDT_WDLY ...........................................................................................................
20-105. WDT_WSPR Register ................................................................................................
20-106. WDT_WIRQSTATRAW Register....................................................................................
20-107. WDT_WIRQSTAT Register ..........................................................................................
20-108. WDT_WIRQENSET Register ........................................................................................
20-109. WDT_WIRQENCLR Register ........................................................................................
21-1. I2C0 Integration and Bus Application ................................................................................
21-2. I2C(12) Integration and Bus Application ...........................................................................
21-3. I2C Functional Block Diagram ........................................................................................
21-4. Multiple I2C Modules Connected .....................................................................................
21-5. Bit Transfer on the I2C Bus ...........................................................................................
21-6. Start and Stop Condition Events .....................................................................................
21-7. I2C Data Transfer ......................................................................................................
21-8. I2C Data Transfer Formats ............................................................................................
21-9. Arbitration Procedure Between Two Master Transmitters ........................................................
21-10. Synchronization of Two I2C Clock Generators .....................................................................
21-11. Receive FIFO Interrupt Request Generation .......................................................................
21-12. Transmit FIFO Interrupt Request Generation .......................................................................
21-13. Receive FIFO DMA Request Generation ...........................................................................
21-14. Transmit FIFO DMA Request Generation (High Threshold) ......................................................
21-15. Transmit FIFO DMA Request Generation (Low Threshold) ......................................................
21-16. I2C_REVNB_LO Register (Module Revision) (LOW BYTES) ...................................................
21-17. I2C_REVNB_HI Register (HIGH BYTES) (Module Revision) ....................................................
21-18. I2C_SYSC Register (System Configuration) ........................................................................
21-19. I2C_IRQSTATUS_RAW Register (I2C Status Raw) ...............................................................
21-20. I2C_IRQSTATUS Register (I2C Status) .............................................................................
21-21. I2C_IRQENABLE_SET Register (I2C Interrupt Enable Set) .....................................................
21-22. I2C_IRQENABLE_CLR Register (I2C Interrupt Enable Clear) ..................................................
21-23. I2C_WE Register (I2C Wakeup Enable) ............................................................................
21-24. I2C_DMARXENABLE_SET Register (Receive DMA Enable Set) ...............................................
21-25. I2C_DMATXENABLE_SET Register (Transmit DMA Enable Set) ...............................................
21-26. I2C_DMARXENABLE_CLR Register (Receive DMA Enable Clear).............................................
21-27. I2C_DMATXENABLE_CLR Register (Transmit DMA Enable Clear) ............................................
21-28. I2C_DMARXWAKE_EN Register (Receive DMA Wakeup) .......................................................
21-29. I2C_DMATXWAKE_EN Register (Transmit DMA Wakeup) ......................................................
21-30. I2C_SYSS Register (System Status) ................................................................................
21-31. I2C_BUF Register (Buffer Configuration) ...........................................................................
21-32. I2C_CNT Register (Data Counter) ...................................................................................
21-33. I2C_DATA Register (Data Access) ..................................................................................
21-34. I2C_CON Register (I2C Configuration) ..............................................................................
21-35. I2C_OA Register (I2C Own Address) ................................................................................
21-36. I2C_SA Register (I2C Own Address) ................................................................................
20-97. WDT_WISR Register

List of Figures
3856
3857
3857
3858
3858
3858
3859
3860
3860
3861
3862
3863
3864
3867
3867
3869
3870
3871
3872
3872
3873
3874
3874
3876
3877
3878
3878
3879
3883
3884
3885
3886
3890
3892
3894
3896
3899
3899
3900
3900
3901
3903
3905
3906
3908
3909
3910
3912
3913
77
www.ti.com
21-37. I2C_PSC Register (I2C Own Address) .............................................................................. 3914
21-38. Clock Divider ............................................................................................................ 3914
21-39. I2C_SCLL Register (I2C SCL Low Time) ........................................................................... 3915

21-40. I2C_SCLH Register (I2C SCL High Time) .......................................................................... 3915
21-41. I2C_SYSTEST Register (System Test)
.............................................................................
3916
21-42. I2C_BUFSTAT Register (I2C Buffer Status) ........................................................................ 3919
21-43. I2C_OA1 Register (OA1) (Own Address 1) ......................................................................... 3920

21-44. I2C_OA2 Register (I2C Own Address 2) ............................................................................ 3921
21-45. I2C_OA3 Register (I2C Own Address 3) ............................................................................ 3922
21-46. I2C_ACTOA Register (Active Own Address) ....................................................................... 3923
21-47. I2C_SBLOCK Register (I2C Clock Blocking Enable) .............................................................. 3924
22-1.
22-2.
22-3.
22-4.
McASP Block Diagram
................................................................................................
3931
McASP to Parallel 2-Channel DACs ................................................................................. 3932

McASP to 6-Channel DAC and 2-Channel DAC ................................................................... 3932
22-5.
McASP to Digital Amplifier ............................................................................................ 3933
22-6.
McASP as Digital Audio Encoder
22-7.
McASP as 16 Channel Digital Processor
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
22-21.
22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
22-35.
22-36.
22-37.
22-38.
78
McASP01 Integration ................................................................................................. 3928
....................................................................................
...........................................................................
TDM Format6 Channel TDM Example .............................................................................
TDM Format Bit Delays from Frame Sync ..........................................................................
Inter-Integrated Sound (I2S) Format .................................................................................
Biphase-Mark Code (BMC) ...........................................................................................
S/PDIF Subframe Format .............................................................................................
S/PDIF Frame Format .................................................................................................
Definition of Bit, Word, and Slot ......................................................................................
Bit Order and Word Alignment Within a Slot Examples ...........................................................
Definition of Frame and Frame Sync Width .........................................................................
Transmit Clock Generator Block Diagram...........................................................................
Receive Clock Generator Block Diagram ...........................................................................
Frame Sync Generator Block Diagram ..............................................................................
Burst Frame Sync Mode ...............................................................................................
Transmit DMA Event (AXEVT) Generation in TDM Time Slots ..................................................
Individual Serializer and Connections Within McASP .............................................................
Receive Format Unit ...................................................................................................
Transmit Format Unit...................................................................................................
McASP I/O Pin Control Block Diagram ..............................................................................
Processor Service Time Upon Transmit DMA Event (AXEVT) ...................................................
Processor Service Time Upon Receive DMA Event (AREVT) ...................................................
McASP Audio FIFO (AFIFO) Block Diagram .......................................................................
Data Flow Through Transmit Format Unit, Illustrated .............................................................
Data Flow Through Receive Format Unit, Illustrated ..............................................................
Transmit Clock Failure Detection Circuit Block Diagram ..........................................................
Receive Clock Failure Detection Circuit Block Diagram...........................................................
Serializers in Loopback Mode ........................................................................................
Interrupt Multiplexing ...................................................................................................
Audio Mute (AMUTE) Block Diagram ................................................................................
DMA Events in an Audio ExampleTwo Events (Scenario 1) ....................................................
DMA Events in an Audio ExampleFour Events (Scenario 2)....................................................
DMA Events in an Audio Example ...................................................................................
List of Figures
3933
3933
3934
3935
3935
3936
3937
3938
3939
3939
3940
3941
3942
3943
3945
3947
3952
3953
3953
3955
3957
3958
3960
3963
3965
3969
3971
3972
3978
3979
3981
3981
3982

www.ti.com
22-39. Revision Identification Register (REV) ............................................................................... 3985
22-40. Pin Function Register (PFUNC) ...................................................................................... 3986
22-41. Pin Direction Register (PDIR) ......................................................................................... 3988

22-42. Pin Data Output Register (PDOUT) .................................................................................. 3990
22-43. Pin Data Input Register (PDIN) ....................................................................................... 3992

22-44. Pin Data Set Register (PDSET) ...................................................................................... 3994
22-45. Pin Data Clear Register (PDCLR) .................................................................................... 3996

22-46. Global Control Register (GBLCTL) ................................................................................... 3998
22-47. Audio Mute Control Register (AMUTE) .............................................................................. 4000

22-48. Digital Loopback Control Register (DLBCTL) ....................................................................... 4002
............................................................................
Receiver Global Control Register (RGBLCTL) .....................................................................
Receive Format Unit Bit Mask Register (RMASK) .................................................................
Receive Bit Stream Format Register (RFMT) ......................................................................
Receive Frame Sync Control Register (AFSRCTL)................................................................
Receive Clock Control Register (ACLKRCTL) ......................................................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) ................................................
Receive TDM Time Slot Register (RTDM) ..........................................................................
Receiver Interrupt Control Register (RINTCTL) ....................................................................
Receiver Status Register (RSTAT)...................................................................................
Current Receive TDM Time Slot Registers (RSLOT) ..............................................................
Receive Clock Check Control Register (RCLKCHK) ..............................................................
Receiver DMA Event Control Register (REVTCTL)................................................................
Transmitter Global Control Register (XGBLCTL) ..................................................................
Transmit Format Unit Bit Mask Register (XMASK) ................................................................
Transmit Bit Stream Format Register (XFMT) ......................................................................
Transmit Frame Sync Control Register (AFSXCTL) ...............................................................
Transmit Clock Control Register (ACLKXCTL) .....................................................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) ...............................................
Transmit TDM Time Slot Register (XTDM) .........................................................................
Transmitter Interrupt Control Register (XINTCTL) .................................................................
Transmitter Status Register (XSTAT) ................................................................................
Current Transmit TDM Time Slot Register (XSLOT) ..............................................................
Transmit Clock Check Control Register (XCLKCHK) ..............................................................
Transmitter DMA Event Control Register (XEVTCTL) .............................................................
Serializer Control Registers (SRCTLn) ..............................................................................
DIT Left Channel Status Registers (DITCSRA0-DITCSRA5) .....................................................
DIT Right Channel Status Registers (DITCSRB0-DITCSRB5) ...................................................
DIT Left Channel User Data Registers (DITUDRA0-DITUDRA5) ................................................
DIT Right Channel User Data Registers (DITUDRB0-DITUDRB5) ..............................................
Transmit Buffer Registers (XBUFn) ..................................................................................
Receive Buffer Registers (RBUFn)...................................................................................
Write FIFO Control Register (WFIFOCTL) ..........................................................................
Write FIFO Status Register (WFIFOSTS) ...........................................................................
Read FIFO Control Register (RFIFOCTL) ..........................................................................
Read FIFO Status Register (RFIFOSTS) ...........................................................................
DCAN Integration .......................................................................................................
DCAN Block Diagram ..................................................................................................
CAN Module General Initialization Flow .............................................................................
22-49. Digital Mode Control Register (DITCTL)
4003
22-50.
4004
22-51.
22-52.
22-53.
22-54.
22-55.
22-56.
22-57.
22-58.
22-59.
22-60.
22-61.
22-62.
22-63.
22-64.
22-65.
22-66.
22-67.
22-68.
22-69.
22-70.
22-71.
22-72.
22-73.
22-74.
22-75.
22-76.
22-77.
22-78.
22-79.
22-80.
22-81.
22-82.
22-83.
22-84.
23-1.
23-2.
23-3.

List of Figures
4005
4006
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4031
4031
4031
4031
4032
4032
4033
4034
4035
4036
4039
4041
4043
79
www.ti.com
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.
23-18.
23-19.
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
23-41.
23-42.
23-43.
23-44.
23-45.
23-46.
23-47.
23-48.
23-49.
23-50.
24-1.
24-2.
80
........................................................................................
CAN Core in Silent Mode..............................................................................................
CAN Core in Loopback Mode .........................................................................................
CAN Core in External Loopback Mode ..............................................................................
CAN Core in Loop Back Combined With Silent Mode .............................................................
CAN Interrupt Topology 1 .............................................................................................
CAN Interrupt Topology 2 .............................................................................................
Local Power-Down Mode Flow Diagram ............................................................................
CPU Handling of a FIFO Buffer (Interrupt Driven) .................................................................
Bit Timing ................................................................................................................
The Propagation Time Segment......................................................................................
Synchronization on Late and Early Edges ..........................................................................
Filtering of Short Dominant Spikes ...................................................................................
Structure of the CAN Cores CAN Protocol Controller.............................................................
Data Transfer Between IF1/IF2 Registers and Message RAM ...................................................
CAN Control Register (DCAN CTL) ..................................................................................
Error and Status Register (DCAN ES) ...............................................................................
Error Counter Register (DCAN ERRC) ..............................................................................
Bit Timing Register (DCAN BTR) .....................................................................................
Interrupt Register (DCAN INT) ........................................................................................
Test Register (DCAN TEST) ..........................................................................................
Parity Error Code Register (DCAN PERR) ..........................................................................
Auto-Bus-On Time Register (DCAN ABOTR) ......................................................................
Transmission Request X Register (DCAN TXRQ X) ..............................................................
Transmission Request X Register (DCAN TXRQ X) ..............................................................
Interrupt Pending X Register (DCAN INTPND X) ..................................................................
Message Valid X Register (DCAN MSGVAL X) ....................................................................
IF1 Command Registers (DCAN IF1CMD)..........................................................................
IF2 Command Registers (DCAN IF2CMD)..........................................................................
IF1 Mask Register (DCAN IF1MSK) .................................................................................
IF1 Arbitration Register (DCAN IF1ARB) ............................................................................
IF1 Message Control Register (DCAN IF1MCTL) ..................................................................
IF1 Data A Register (DCAN IF1DATA) ..............................................................................
IF1 Data B Register (DCAN IF1DATA) ..............................................................................
IF2 Data B Register (DCAN IF2DATA) ..............................................................................
IF3 Observation Register (DCAN IF3OBS) .........................................................................
IF3 Data A Register (DCAN IF3DATB) ..............................................................................
CAN TX I/O Control Register (DCAN TIOC) ........................................................................
CAN RX IO control register (DCAN RIOC)..........................................................................
SPI Master Application.................................................................................................
SPI Slave Application ..................................................................................................
CAN Bit-Timing Configuration
List of Figures
4044
4046
4047
4048
4049
4051
4051
4053
4062
4063
4064
4066
4067
4068
4072
4080
4082
4084
4085
4086
4087
4088
4089
4090
4092
4094
4096
4099
4099
4102
4102
4103
4103
4105
4105
4107
4107
4107
4107
4108
4110
4111
4112
4114
4114
4116
4118
4122
4122

www.ti.com
24-3.
24-4.
24-5.
24-6.
24-7.
SPI Full-Duplex Transmission ........................................................................................ 4125
SPI Half-Duplex Transmission (Receive-only Slave) .............................................................. 4126

SPI Half-Duplex Transmission (Transmit-Only Slave) ............................................................. 4126
Phase and Polarity Combinations .................................................................................... 4128

Full Duplex Single Transfer Format with PHA = 0 ................................................................. 4129
24-8.
Full Duplex Single Transfer Format With PHA = 1 ................................................................. 4130
24-9.
Continuous Transfers With SPIEN Maintained Active (Single-Data-Pin Interface Mode)
....................
......................
Extended SPI Transfer With Start Bit PHA = 1 .....................................................................
Chip-Select SPIEN Timing Controls .................................................................................
Transmit/Receive Mode With No FIFO Used .......................................................................
Transmit/Receive Mode With Only Receive FIFO Enabled ......................................................
Transmit/Receive Mode With Only Transmit FIFO Used .........................................................
Transmit/Receive Mode With Both FIFO Direction Used .........................................................
Transmit-Only Mode With FIFO Used ...............................................................................
Receive-Only Mode With FIFO Used ...............................................................................
Buffer Almost Full Level (AFL) ........................................................................................
Buffer Almost Empty Level (AEL) ....................................................................................
Master Single Channel Initial Delay ..................................................................................
3-Pin Mode System Overview ........................................................................................
Example of SPI Slave with One Master and Multiple Slave Devices on Channel 0 ...........................
SPI Half-Duplex Transmission (Receive-Only Slave)..............................................................
SPI Half-Duplex Transmission (Transmit-Only Slave) .............................................................
McSPI Revision Register (MCSPI_REVISION) ....................................................................
McSPI System Configuration Register (MCSPI_SYSCONFIG) ..................................................
McSPI System Status Register (MCSPI_SYSSTATUS) ..........................................................
McSPI Interrupt Status Register (MCSPI_IRQSTATUS) ..........................................................
McSPI Interrupt Enable Register (MCSPI_IRQENABLE) .........................................................
McSPI System Register (MCSPI_SYST) ............................................................................
McSPI Module Control Register (MCSPI_MODULCTRL).........................................................
McSPI Channel (i ) Configuration Register (MCSPI_CH(i)CONF) ...............................................
McSPI Channel (i) Status Register (MCSPI_CH(i)STAT) .........................................................
McSPI Channel (i) Control Register (MCSPI_CH(I)CTRL) .......................................................
McSPI Channel (i) Transmit Register (MCSPI_TX(i)) .............................................................
McSPI Channel (i) Receive Register (MCSPI_RX(i)) ..............................................................
McSPI Transfer Levels Register (MCSPI_XFERLEVEL) .........................................................
McSPI DMA Address Aligned FIFO Transmitter Register (MCSPI_DAFTX) ...................................
McSPI DMA Address Aligned FIFO Receiver Register (MCSPI_DAFRX) ......................................
GPIO0 Module Integration ............................................................................................
GPIO[13] Module Integration ........................................................................................
Interrupt Request Generation .........................................................................................
Write @ GPIO_CLEARDATAOUT Register Example .............................................................
Write @ GPIO_SETIRQENABLEx Register Example .............................................................
General-Purpose Interface Used as a Keyboard Interface .......................................................
GPIO_REVISION Register ............................................................................................
GPIO_SYSCONFIG Register .........................................................................................
GPIO_IRQSTATUS_RAW_0 Register ...............................................................................
GPIO_IRQSTATUS_RAW_1 Register ...............................................................................
GPIO_IRQSTATUS_0 Register ......................................................................................
4135
24-10. Continuous Transfers With SPIEN Maintained Active (Dual-Data-Pin Interface Mode)
4135
24-11.
4137
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
24-24.
24-25.
24-26.
24-27.
24-28.
24-29.
24-30.
24-31.
24-32.
24-33.
24-34.
24-35.
24-36.
24-37.
24-38.
24-39.
24-40.
25-1.
25-2.
25-3.
25-4.
25-5.
25-6.
25-7.
25-8.
25-9.
25-10.
25-11.

List of Figures
4138
4142
4142
4143
4143
4144
4144
4145
4146
4147
4148
4150
4152
4153
4161
4162
4163
4164
4167
4169
4171
4173
4177
4178
4179
4179
4180
4181
4182
4185
4185
4190
4192
4193
4194
4196
4197
4198
4199
4200
81
www.ti.com
4201
25-13.
4202
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
25-27.
25-28.
25-29.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
26-19.
26-20.
26-21.
26-22.
26-23.
26-24.
26-25.
26-26.
26-27.
82
......................................................................................
GPIO_IRQSTATUS_SET_0 Register ................................................................................
GPIO_IRQSTATUS_SET_1 Register ................................................................................
GPIO_IRQSTATUS_CLR_0 Register................................................................................
GPIO_IRQSTATUS_CLR_1 Register................................................................................
GPIO_SYSSTATUS Register .........................................................................................
GPIO_CTRL Register ..................................................................................................
GPIO_OE Register .....................................................................................................
GPIO_DATAIN Register ...............................................................................................
GPIO_DATAOUT Register ............................................................................................
GPIO_LEVELDETECT0 Register ....................................................................................
GPIO_LEVELDETECT1 Register ....................................................................................
GPIO_RISINGDETECT Register .....................................................................................
GPIO_FALLINGDETECT Register ...................................................................................
GPIO_DEBOUNCENABLE Register .................................................................................
GPIO_DEBOUNCINGTIME Register ................................................................................
GPIO_CLEARDATAOUT Register ...................................................................................
GPIO_SETDATAOUT Register .......................................................................................
Public ROM Code Architecture .......................................................................................
Public ROM Code Boot Procedure ...................................................................................
ROM Memory Map .....................................................................................................
Public RAM Memory Map .............................................................................................
ROM Code Startup Sequence ........................................................................................
ROM Code Booting Procedure .......................................................................................
Fast External Boot ......................................................................................................
Memory Booting ........................................................................................................
GPMC XIP Timings ....................................................................................................
Image Shadowing on GP Device .....................................................................................
GPMC NAND Timings .................................................................................................
NAND Device Detection ...............................................................................................
NAND Invalid Blocks Detection .......................................................................................
NAND Read Sector Procedure .......................................................................................
ECC Data Mapping for 2 KB Page and 8b BCH Encoding .......................................................
ECC Data Mapping for 4 KB Page and 16b BCH Encoding ......................................................
MMC/SD Booting .......................................................................................................
MMC/SD Detection Procedure........................................................................................
MMC/SD Booting, Get Booting File ..................................................................................
MBR Detection Procedure.............................................................................................
MBR, Get Partition .....................................................................................................
FAT Detection Procedure .............................................................................................
Peripheral Booting Procedure ........................................................................................
USB Initialization Procedure ..........................................................................................
Image Transfer for USB Boot .........................................................................................
Image Formats on GP Devices .......................................................................................
Wakeup Booting by ROM .............................................................................................
25-12. GPIO_IRQSTATUS_1 Register
List of Figures
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4220
4221
4222
4224
4226
4227
4237
4238
4240
4242
4243
4247
4248
4249
4250
4251
4253
4254
4256
4257
4258
4261
4265
4269
4270
4270
4273

www.ti.com
List of Tables
1-1.
1-2.
Device Features .......................................................................................................... 154
Device_ID (Address 0x44E10600) Bit Field Descriptions .......................................................... 155
1-3.
Device ID Register Values .............................................................................................. 155
1-4.
DEV_FEATURE (Address 0x44E10604) Register Values
2-1.
2-2.
2-3.
2-4.
2-5.
3-1.
.........................................................
157
L3 Memory Map .......................................................................................................... 158

L4_WKUP Peripheral Memory Map ................................................................................... 160
L4_PER Peripheral Memory Map ...................................................................................... 161
L4 Fast Peripheral Memory Map ....................................................................................... 165

M3 Processor Memory Map ............................................................................................ 167
MPU Subsystem Clock Frequencies .................................................................................. 173
3-2.
Reset Scheme of the MPU Subsystem ............................................................................... 174
3-3.
ARM Core Supported Features
3-4.
3-5.
3-6.
5-1.
5-2.
6-1.
6-2.
6-3.
6-4.
6-5.
6-6.
6-7.
6-8.
6-9.
6-10.
6-11.
6-12.
6-13.
6-14.
6-15.
6-16.
6-17.
6-18.
6-19.
6-20.
6-21.
6-22.
6-23.
6-24.
6-25.
6-26.
6-27.
6-28.
6-29.
6-30.
.......................................................................................
Overview of the MPU Subsystem Power Domain ...................................................................
MPU Power States.......................................................................................................
MPU Subsystem Operation Power Modes ...........................................................................
SGX530 Connectivity Attributes........................................................................................
SGX530 Clock Signals ..................................................................................................
ARM Cortex-A8 Interrupts ..............................................................................................
ARM Cortex-M3 Wakeup Processor Interrupts ......................................................................
Timer and eCAP Event Capture .......................................................................................
INTC REGISTERS .......................................................................................................
INTC_REVISION Register Field Descriptions ........................................................................
INTC_SYSCONFIG Register Field Descriptions .....................................................................
INTC_SYSSTATUS Register Field Descriptions ....................................................................
INTC_SIR_IRQ Register Field Descriptions ..........................................................................
INTC_SIR_FIQ Register Field Descriptions ..........................................................................
INTC_CONTROL Register Field Descriptions .......................................................................
INTC_PROTECTION Register Field Descriptions ...................................................................
INTC_IDLE Register Field Descriptions...............................................................................
INTC_IRQ_PRIORITY Register Field Descriptions .................................................................
INTC_FIQ_PRIORITY Register Field Descriptions ..................................................................
INTC_THRESHOLD Register Field Descriptions ....................................................................
INTC_ITR0 Register Field Descriptions ...............................................................................
INTC_MIR0 Register Field Descriptions ..............................................................................
INTC_MIR_CLEAR0 Register Field Descriptions....................................................................
INTC_MIR_SET0 Register Field Descriptions .......................................................................
INTC_ISR_SET0 Register Field Descriptions ........................................................................
INTC_ISR_CLEAR0 Register Field Descriptions ....................................................................
INTC_PENDING_IRQ0 Register Field Descriptions ................................................................
INTC_PENDING_FIQ0 Register Field Descriptions .................................................................
INTC_ITR1 Register Field Descriptions ...............................................................................
INTC_MIR1 Register Field Descriptions ..............................................................................
INTC_MIR_CLEAR1 Register Field Descriptions....................................................................
INTC_MIR_SET1 Register Field Descriptions .......................................................................
INTC_ISR_SET1 Register Field Descriptions ........................................................................
INTC_ISR_CLEAR1 Register Field Descriptions ....................................................................
INTC_PENDING_IRQ1 Register Field Descriptions ................................................................

List of Tables
175
177
178
179
187
187
204
208
210
211
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
83
www.ti.com
6-31.
6-32.
6-33.
INTC_ITR2 Register Field Descriptions ............................................................................... 242

INTC_MIR2 Register Field Descriptions .............................................................................. 243
6-34.
INTC_MIR_CLEAR2 Register Field Descriptions.................................................................... 244
6-35.
INTC_MIR_SET2 Register Field Descriptions
6-36.
.......................................................................
245
INTC_ISR_SET2 Register Field Descriptions ........................................................................ 246
6-37.
INTC_ISR_CLEAR2 Register Field Descriptions .................................................................... 247
6-38.
INTC_PENDING_IRQ2 Register Field Descriptions
6-39.
6-40.
6-41.
................................................................
248
INTC_PENDING_FIQ2 Register Field Descriptions ................................................................. 249

INTC_ITR3 Register Field Descriptions ............................................................................... 250
INTC_MIR3 Register Field Descriptions .............................................................................. 251
6-42.
INTC_MIR_CLEAR3 Register Field Descriptions.................................................................... 252
6-43.
INTC_MIR_SET3 Register Field Descriptions
6-44.
.......................................................................
253
INTC_ISR_SET3 Register Field Descriptions ........................................................................ 254
6-45.
INTC_ISR_CLEAR3 Register Field Descriptions .................................................................... 255
6-46.
INTC_PENDING_IRQ3 Register Field Descriptions
6-47.
6-48.
6-49.
6-50.
6-51.
6-52.
6-53.
6-54.
6-55.
6-56.
6-57.
6-58.
6-59.
6-60.
6-61.
6-62.
6-63.
6-64.
6-65.
6-66.
6-67.
6-68.
6-69.
6-70.
6-71.
6-72.
6-73.
6-74.
6-75.
6-76.
6-77.
6-78.
6-79.
84
INTC_PENDING_FIQ1 Register Field Descriptions ................................................................. 241
................................................................
INTC_PENDING_FIQ3 Register Field Descriptions .................................................................
INTC_ILR0 Register Field Descriptions ...............................................................................
INTC_ILR10 Register Field Descriptions .............................................................................
List of Tables
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289

www.ti.com
6-80.
6-81.
6-82.
6-83.
6-84.
6-85.
6-86.
6-87.
6-88.
6-89.
6-90.
6-91.
6-92.
6-93.
6-94.
6-95.
6-96.
6-97.
6-98.
6-99.
INTC_ILR32 Register Field Descriptions ............................................................................. 290

6-100. INTC_ILR52 Register Field Descriptions ............................................................................. 310

List of Tables
85
www.ti.com

6-148. INTC_ILR100 Register Field Descriptions ............................................................................ 358

7-1.
7-2.
86
Unsupported GPMC Features .......................................................................................... 389
GPMC Connectivity Attributes .......................................................................................... 390
List of Tables

www.ti.com
7-3.
GPMC Clock Signals .................................................................................................... 390
7-4.
GPMC Signal List ........................................................................................................ 391
7-5.
GPMC Pin Multiplexing Options
392
7-6.
GPMC Clocks
397
7-7.
7-8.
7-9.
7-10.
7-11.
7-12.
7-13.
7-14.
7-15.
7-16.
7-17.
7-18.
7-19.
7-20.
7-21.
7-22.
7-23.
7-24.
7-25.
7-26.
7-27.
7-28.
7-29.
7-30.
7-31.
7-32.
7-33.
7-34.
7-35.
7-36.
7-37.
7-38.
7-39.
7-40.
7-41.
7-42.
7-43.
7-44.
7-45.
7-46.
7-47.
7-48.
7-49.
7-50.
7-51.
.......................................................................................
............................................................................................................
GPMC_CONFIG1_i Configuration .....................................................................................
GPMC Local Power Management Features ..........................................................................
GPMC Interrupt Events .................................................................................................
Idle Cycle Insertion Configuration......................................................................................
Chip-Select Configuration for NAND Interfacing .....................................................................
ECC Enable Settings ....................................................................................................
Flattened BCH Codeword Mapping (512 Bytes + 104 Bits) ........................................................
Aligned Message Byte Mapping in 8-bit NAND ......................................................................
Aligned Message Byte Mapping in 16-bit NAND ....................................................................
Aligned Nibble Mapping of Message in 8-bit NAND .................................................................
Misaligned Nibble Mapping of Message in 8-bit NAND .............................................................
Aligned Nibble Mapping of Message in 16-bit NAND ...............................................................
Misaligned Nibble Mapping of Message in 16-bit NAND (1 Unused Nibble).....................................
Prefetch Mode Configuration ...........................................................................................
Write-Posting Mode Configuration .....................................................................................
GPMC Configuration in NOR Mode ...................................................................................
GPMC Configuration in NAND Mode ..................................................................................
Reset GPMC..............................................................................................................
NOR Memory Type ......................................................................................................
NOR Chip-Select Configuration ........................................................................................
NOR Timings Configuration ............................................................................................
WAIT Pin Configuration .................................................................................................
Enable Chip-Select ......................................................................................................
NAND Memory Type ....................................................................................................
NAND Chip-Select Configuration ......................................................................................
Asynchronous Read and Write Operations ...........................................................................
ECC Engine...............................................................................................................
Prefetch and Write-Posting Engine ....................................................................................
WAIT Pin Configuration .................................................................................................
Enable Chip-Select ......................................................................................................
Mode Parameters Check List Table ...................................................................................
Access Type Parameters Check List Table ..........................................................................
Timing Parameters .......................................................................................................
NAND Formulas Description Table ....................................................................................
Synchronous NOR Formulas Description Table .....................................................................
Asynchronous NOR Formulas Description Table ....................................................................
GPMC Signals ............................................................................................................
Useful Timing Parameters on the Memory Side .....................................................................
Calculating GPMC Timing Parameters................................................................................
AC Characteristics for Asynchronous Read Access ................................................................
GPMC Timing Parameters for Asynchronous Read Access .......................................................
AC Characteristics for Asynchronous Single Write (Memory Side) ...............................................
GPMC Timing Parameters for Asynchronous Single Write ........................................................

List of Tables
397
397
398
409
438
447
452
452
453
453
453
453
454
454
454
465
467
473
473
473
474
474
474
474
475
475
475
475
475
477
477
477
478
478
480
482
483
489
491
493
494
495
496
497
498
87
www.ti.com
7-52.
NAND Interface Bus Operations Summary ........................................................................... 499
7-53.
NOR Interface Bus Operations Summary
7-54.
7-55.
7-56.
7-57.
7-58.
7-59.
7-60.
............................................................................
499
GPMC Registers ......................................................................................................... 502

GPMC_REVISION Field Descriptions ................................................................................. 503
GPMC_SYSCONFIG Field Descriptions .............................................................................. 503
GPMC_SYSSTATUS Field Descriptions.............................................................................. 504
GPMC_IRQSTATUS Field Descriptions .............................................................................. 505

GPMC_IRQENABLE Field Descriptions .............................................................................. 506
GPMC_TIMEOUT_CONTROL Field Descriptions ................................................................... 507
7-61.
GPMC_ERR_ADDRESS Field Descriptions ......................................................................... 507
7-62.
GPMC_ERR_TYPE Field Descriptions
7-63.
7-64.
7-65.
7-66.
7-67.
7-68.
7-69.
7-70.
7-71.
7-72.
7-73.
7-74.
7-75.
7-76.
7-77.
7-78.
7-79.
7-80.
7-81.
7-82.
7-83.
7-84.
7-85.
7-86.
7-87.
7-88.
7-89.
7-90.
7-91.
7-92.
7-93.
7-94.
7-95.
7-96.
7-97.
7-98.
7-99.
...............................................................................
GPMC_CONFIG Field Descriptions ...................................................................................
GPMC_STATUS Field Descriptions ...................................................................................
GPMC_CONFIG1_i Field Descriptions ...............................................................................
GPMC_NAND_COMMAND_i Field Descriptions ....................................................................
GPMC_NAND_ADDRESS_i Field Descriptions .....................................................................
GPMC_NAND_DATA_i Field Descriptions ...........................................................................
GPMC_PREFETCH_CONFIG1 Field Descriptions..................................................................
GPMC_PREFETCH_CONFIG2 Field Descriptions..................................................................
GPMC_PREFETCH_CONTROL Field Descriptions ................................................................
GPMC_PREFETCH_STATUS Field Descriptions ...................................................................
GPMC_ECC_CONFIG Field Descriptions ............................................................................
GPMC_ECC_CONTROL Field Descriptions .........................................................................
GPMC_ECC_SIZE_CONFIG Field Descriptions ....................................................................
GPMC_ECCj_RESULT Field Descriptions ...........................................................................
GPMC_BCH_RESULT0_i Field Descriptions ........................................................................
GPMC_BCH_SWDATA Field Descriptions ...........................................................................
OCMC RAM Connectivity Attributes ...................................................................................
OCMC RAM Clock Signals .............................................................................................
Unsupported EMIF Features ...........................................................................................
EMIF Connectivity Attributes ...........................................................................................
EMIF Clock Signals ......................................................................................................
EMIF Pin List .............................................................................................................
DDR2/3/mDDR Memory Controller Signal Descriptions ............................................................
Digital Filter Configuration ..............................................................................................
IBANK, RSIZE and PAGESIZE Fields Information ..................................................................
508
509
510
511
514
515
517
519
520
521
522
522
522
523
525
525
526
527
528
529
531
532
532
532
533
533
533
534
534
536
536
538
539
539
539
541
545
546
7-100. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=0 and

88
List of Tables

www.ti.com
REG_EBANK_POS=0 ................................................................................................... 547

REG_EBANK_POS=0 ................................................................................................... 548
REG_EBANK_POS=0 ................................................................................................... 548
REG_EBANK_POS=0 ................................................................................................... 549
REG_EBANK_POS=1 ................................................................................................... 549
7-105. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=1 and REG_EBANK_POS =
1 ............................................................................................................................ 549
7-106. OCP Address to DDR2/3/mDDR Address Mapping for REG_IBANK_POS=2 and REG_EBANK_POS =
1 ............................................................................................................................ 550
REG_EBANK_POS=1 ................................................................................................... 550
7-108. Refresh Modes ........................................................................................................... 553

7-109. EMIF4D REGISTERS ................................................................................................... 559
7-110. EMIF_MOD_ID_REV Register Field Descriptions ................................................................... 560

7-111. STATUS Register Field Descriptions .................................................................................. 561
7-112. SDRAM_CONFIG Register Field Descriptions....................................................................... 562
7-113. SDRAM_CONFIG_2 Register Field Descriptions.................................................................... 564
7-114. SDRAM_REF_CTRL Register Field Descriptions ................................................................... 565
.........................................................
.........................................................................
SDRAM_TIM_1_SHDW Register Field Descriptions ................................................................
SDRAM_TIM_2 Register Field Descriptions .........................................................................
SDRAM_TIM_3 Register Field Descriptions .........................................................................
PWR_MGMT_CTRL Register Field Descriptions ....................................................................
PWR_MGMT_CTRL_SHDW Register Field Descriptions ..........................................................
PERF_CNT_1 Register Field Descriptions ...........................................................................
PERF_CNT_2 Register Field Descriptions ...........................................................................
PERF_CNT_CFG Register Field Descriptions .......................................................................
PERF_CNT_SEL Register Field Descriptions .......................................................................
PERF_CNT_TIM Register Field Descriptions ........................................................................
READ_IDLE_CTRL Register Field Descriptions .....................................................................
READ_IDLE_CTRL_SHDW Register Field Descriptions ...........................................................
IRQSTATUS_RAW_SYS Register Field Descriptions ..............................................................
IRQSTATUS_SYS Register Field Descriptions ......................................................................
IRQENABLE_SET_SYS Register Field Descriptions ...............................................................
IRQENABLE_CLR_SYS Register Field Descriptions ...............................................................
ZQ_CONFIG Register Field Descriptions.............................................................................
Read-Write Leveling Ramp Window Register Register Field Descriptions.......................................
Read-Write Leveling Ramp Control Register Register Field Descriptions .......................................
Read-Write Leveling Control Register Register Field Descriptions ...............................................
DDR_PHY_CTRL_1 Register Field Descriptions ....................................................................
DDR_PHY_CTRL_1_SHDW Register Field Descriptions ..........................................................
Priority to Class of Service Mapping Register Register Field Descriptions ......................................
Connection ID to Class of Service 1 Mapping Register Register Field Descriptions ...........................
Connection ID to Class of Service 2 Mapping Register Register Field Descriptions ...........................
7-115. SDRAM_REF_CTRL_SHDW Register Field Descriptions
566
7-116. SDRAM_TIM_1 Register Field Descriptions
567
7-117.
568
7-118.
7-119.
7-120.
7-121.
7-122.
7-123.
7-124.
7-125.
7-126.
7-127.
7-128.
7-129.
7-130.
7-131.
7-132.
7-133.
7-134.
7-135.
7-136.
7-137.
7-138.
7-139.
7-140.
7-141.
7-142.
7-143.

List of Tables
569
570
571
572
573
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
593
595
596
597
89
www.ti.com
..........................................
Memory-Mapped Registers for DDR2/3/mDDR PHY ...............................................................
7-144. Read Write Execution Threshold Register Register Field Descriptions
599
7-145.
600
7-146. DDR PHY Command 0/1/2 Address/Command Slave Ratio Register

(CMD0/1/2_REG_PHY_CTRL_SLAVE_RATIO_0) Field Descriptions
...........................................
602
7-147. DDR PHY Command 0/1/2 Address/Command DLL Lock Difference Register(
CMD0/1/2_REG_PHY_DLL_LOCK_DIFF_0) Field Descriptions .................................................. 602
7-148. DDR PHY Command 0/1/2 Invert Clockout Selection Register(
CMD0/1/2_REG_PHY_INVERT_CLKOUT_0) Field Descriptions ................................................. 603
7-149. DDR PHY Data Macro 0/1 Read DQS Slave Ratio Register
(DATA0/1_REG_PHY_RD_DQS_SLAVE_RATIO_0) Field Descriptions ........................................ 603
7-150. DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register
(DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) .............................................................. 604
7-151. DDR PHY Data Macro 0/1 Write DQS Slave Ratio Register(
DATA0/1_REG_PHY_WR_DQS_SLAVE_RATIO_0) Field Descriptions ......................................... 604
7-152. DDR PHY Data Macro 0/1 Write Leveling Init Ratio Register (
DATA0/1_REG_PHY_WRLVL_INIT_RATIO_0) Field Descriptions ............................................... 604
7-153. DDR PHY Data Macro 0 Write Leveling Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_WRLVL_INIT_MODE_0) .................................................................... 605
7-154. DDR PHY Data Macro 0 DQS Gate Training Init Ratio Register
(DATA0_REG_PHY_GATELVL_INIT_RATIO_0) Field Descriptions ............................................. 605
7-155. DDR PHY Data Macro 0/1 DQS Gate Training Init Mode Ratio Selection Register
(DATA0/1_REG_PHY_GATELVL_INIT_MODE_0) Field Descriptions ........................................... 606
7-156. DDR PHY Data Macro 0/1 DQS Gate Slave Ratio Register
(DATA0/1_REG_PHY_FIFO_WE_SLAVE_RATIO_0) Field Descriptions........................................ 606
7-157. DDR PHY Data Macro 0/1 Write Data Slave Ratio Register
(DATA0/1_REG_PHY_WR_DATA_SLAVE_RATIO_0) Field Descriptions
......................................
607
7-158. DDR PHY Data Macro 0/1 Delay Selection Register (DATA0/1_REG_PHY_USE_RANK0_DELAYS)
Field Descriptions ........................................................................................................ 608
7-159. ELM Connectivity Attributes ............................................................................................ 610
7-160. ELM Clock Signals ....................................................................................................... 610
7-161. Local Power Management Features................................................................................... 611
7-162. Events ..................................................................................................................... 611

7-163. ELM_LOCATION_STATUS_i Value Decoding Table ............................................................... 613
7-164. ELM Processing Initialization ........................................................................................... 614
7-165. ELM Processing Completion for Continuous Mode ................................................................. 614
7-166. ELM Processing Completion for Page Mode ......................................................................... 615

7-167. Use Case: Continuous Mode ........................................................................................... 615
7-168. 16-bit NAND Sector Buffer Address Map ............................................................................. 617
7-169. Use Case: Page Mode .................................................................................................. 617

7-170. ELM Registers ............................................................................................................ 620
7-171. ELM Revision Register (ELM_REVISION) Field Descriptions ..................................................... 621

7-172. ELM System Configuration Register (ELM_SYSCONFIG) Field Descriptions................................... 621
7-173. ELM System Status Register (ELM_SYSSTATUS) Field Descriptions ........................................... 622
7-174. ELM Interrupt Status Register (ELM_IRQSTATUS) Field Descriptions
..........................................
623
.......................
626
7-175. ELM Interrupt Enable Register (ELM_IRQENABLE) Field Descriptions .......................................... 625
7-176. ELM Location Configuration Register (ELM_LOCATION_CONFIG) Field Descriptions
7-177. ELM Page Definition Register (ELM_PAGE_CTRL) Field Descriptions .......................................... 627
7-178. ELM_SYNDROME_FRAGMENT_0_i Register Field Descriptions ................................................ 628
90
List of Tables

www.ti.com

7-185. ELM_LOCATION_STATUS_i Register Field Descriptions ......................................................... 630
7-186. ELM_ERROR_LOCATION_0-15_i Registers Field Descriptions .................................................. 631

8-1.
8-2.
8-3.
8-4.
8-5.
8-6.
8-7.
8-8.
8-9.
8-10.
8-11.
8-12.
8-13.
8-14.
8-15.
8-16.
8-17.
8-18.
8-19.
8-20.
8-21.
8-22.
8-23.
8-24.
8-25.
8-26.
8-27.
8-28.
8-29.
8-30.
8-31.
8-32.
8-33.
8-34.
8-35.
8-36.
8-37.
8-38.
8-39.
8-40.
8-41.
8-42.
8-43.
8-44.
8-45.
Master Module Standby-Mode Settings ............................................................................... 634
........................................................................................
Module Idle Mode Settings .............................................................................................
Idle States for a Slave Module .........................................................................................
Slave Module Mode Settings in PRCM ...............................................................................
Module Clock Enabling Condition......................................................................................
Clock Domain Functional Clock States ...............................................................................
Clock Domain States ....................................................................................................
Clock Transition Mode Settings ........................................................................................
States of a Memory Area in a Power Domain ........................................................................
States of a Logic Area in a Power Domain ...........................................................................
Power Domain Control and Status Registers ........................................................................
Typical Power Modes....................................................................................................
M3 Interrupts 13 ........................................................................................................
Output Clocks in Locked Condition ....................................................................................
Output Clocks Before Lock and During Relock Modes .............................................................
Output Clocks in Locked Condition ....................................................................................
Output Clocks Before Lock and During Relock Modes .............................................................
PLL and Clock Frequences .............................................................................................
Core PLL Typical Frequencies (MHz) .................................................................................
Bus Interface Clocks .....................................................................................................
Per PLL Typical Frequencies (MHz) ..................................................................................
Reset Sources ............................................................................................................
Core Logic Voltage and Power Domains .............................................................................
Power Domain State Table .............................................................................................
Power Domain of Various Modules ....................................................................................
CM_PER REGISTERS ..................................................................................................
CM_PER_L4LS_CLKSTCTRL Register Field Descriptions ........................................................
CM_PER_L3S_CLKSTCTRL Register Field Descriptions..........................................................
CM_PER_L3_CLKSTCTRL Register Field Descriptions ...........................................................
CM_PER_CPGMAC0_CLKCTRL Register Field Descriptions ....................................................
CM_PER_LCDC_CLKCTRL Register Field Descriptions ..........................................................
CM_PER_USB0_CLKCTRL Register Field Descriptions ...........................................................
CM_PER_TPTC0_CLKCTRL Register Field Descriptions .........................................................
CM_PER_EMIF_CLKCTRL Register Field Descriptions ...........................................................
CM_PER_OCMCRAM_CLKCTRL Register Field Descriptions....................................................
CM_PER_GPMC_CLKCTRL Register Field Descriptions ..........................................................
CM_PER_MCASP0_CLKCTRL Register Field Descriptions .......................................................
CM_PER_UART5_CLKCTRL Register Field Descriptions .........................................................
CM_PER_MMC0_CLKCTRL Register Field Descriptions ..........................................................
CM_PER_ELM_CLKCTRL Register Field Descriptions ............................................................
CM_PER_I2C2_CLKCTRL Register Field Descriptions ............................................................
CM_PER_I2C1_CLKCTRL Register Field Descriptions ............................................................
CM_PER_SPI0_CLKCTRL Register Field Descriptions ............................................................
CM_PER_SPI1_CLKCTRL Register Field Descriptions ............................................................
Master Module Standby Status

List of Tables
635
635
636
636
637
638
639
639
640
640
640
641
645
650
651
653
653
655
655
656
657
671
674
674
674
677
679
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
91
www.ti.com
8-46.
8-47.
8-48.
8-49.
8-50.
8-51.
8-52.
8-53.
8-54.
8-55.
8-56.
8-57.
8-58.
8-59.
8-60.
8-61.
8-62.
8-63.
8-64.
8-65.
8-66.
8-67.
8-68.
8-69.
8-70.
8-71.
8-72.
8-73.
8-74.
8-75.
8-76.
8-77.
8-78.
8-79.
8-80.
8-81.
8-82.
8-83.
8-84.
8-85.
8-86.
8-87.
8-88.
8-89.
8-90.
8-91.
8-92.
8-93.
8-94.
92
...........................................................
CM_PER_L4FW_CLKCTRL Register Field Descriptions...........................................................
CM_PER_MCASP1_CLKCTRL Register Field Descriptions .......................................................
CM_PER_TIMER7_CLKCTRL Register Field Descriptions ........................................................
CM_PER_GPIO1_CLKCTRL Register Field Descriptions..........................................................
CM_PER_TPCC_CLKCTRL Register Field Descriptions ..........................................................
CM_PER_DCAN0_CLKCTRL Register Field Descriptions .........................................................
CM_PER_DCAN1_CLKCTRL Register Field Descriptions .........................................................
CM_PER_EPWMSS1_CLKCTRL Register Field Descriptions ....................................................
CM_PER_L3_INSTR_CLKCTRL Register Field Descriptions .....................................................
CM_PER_L3_CLKCTRL Register Field Descriptions ...............................................................
CM_PER_IEEE5000_CLKCTRL Register Field Descriptions ......................................................
CM_PER_PRU_ICSS_CLKCTRL Register Field Descriptions ....................................................
CM_PER_SPINLOCK_CLKCTRL Register Field Descriptions ....................................................
CM_PER_MAILBOX0_CLKCTRL Register Field Descriptions ....................................................
CM_PER_L4HS_CLKSTCTRL Register Field Descriptions........................................................
CM_PER_L4HS_CLKCTRL Register Field Descriptions ...........................................................
CM_PER_OCPWP_L3_CLKSTCTRL Register Field Descriptions ................................................
CM_PER_OCPWP_CLKCTRL Register Field Descriptions........................................................
CM_PER_PRU_ICSS_CLKSTCTRL Register Field Descriptions .................................................
CM_PER_CPSW_CLKSTCTRL Register Field Descriptions ......................................................
CM_PER_LCDC_CLKSTCTRL Register Field Descriptions .......................................................
CM_PER_CLKDIV32K_CLKCTRL Register Field Descriptions ...................................................
CM_PER_CLK_24MHZ_CLKSTCTRL Register Field Descriptions ...............................................
CM_WKUP REGISTERS ...............................................................................................
CM_WKUP_CLKSTCTRL Register Field Descriptions .............................................................
CM_WKUP_CONTROL_CLKCTRL Register Field Descriptions ..................................................
CM_WKUP_GPIO0_CLKCTRL Register Field Descriptions .......................................................
CM_WKUP_L4WKUP_CLKCTRL Register Field Descriptions ....................................................
CM_WKUP_TIMER0_CLKCTRL Register Field Descriptions .....................................................
CM_WKUP_DEBUGSS_CLKCTRL Register Field Descriptions ..................................................
CM_L3_AON_CLKSTCTRL Register Field Descriptions ...........................................................
CM_PER_L4LS_CLKCTRL Register Field Descriptions
List of Tables
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
739
743
745
746
747
748
749
750

www.ti.com
8-95.
8-96.
8-97.
8-98.
8-99.
8-100.
8-101.
8-102.
8-103.
8-104.
8-105.
8-106.
8-107.
8-108.
8-109.
8-110.
8-111.
8-112.
8-113.
8-114.
8-115.
8-116.
8-117.
8-118.
8-119.
8-120.
8-121.
8-122.
8-123.
8-124.
8-125.
8-126.
8-127.
8-128.
8-129.
8-130.
8-131.
8-132.
8-133.
8-134.
8-135.
8-136.
8-137.
8-138.
8-139.
8-140.
8-141.
8-142.
8-143.
.........................................................
CM_IDLEST_DPLL_MPU Register Field Descriptions .............................................................
CM_SSC_DELTAMSTEP_DPLL_MPU Register Field Descriptions ..............................................
CM_SSC_MODFREQDIV_DPLL_MPU Register Field Descriptions..............................................
CM_CLKSEL_DPLL_MPU Register Field Descriptions.............................................................
CM_AUTOIDLE_DPLL_DDR Register Field Descriptions..........................................................
CM_IDLEST_DPLL_DDR Register Field Descriptions..............................................................
CM_SSC_DELTAMSTEP_DPLL_DDR Register Field Descriptions ..............................................
CM_SSC_MODFREQDIV_DPLL_DDR Register Field Descriptions ..............................................
CM_CLKSEL_DPLL_DDR Register Field Descriptions .............................................................
CM_AUTOIDLE_DPLL_DISP Register Field Descriptions .........................................................
CM_IDLEST_DPLL_DISP Register Field Descriptions .............................................................
CM_SSC_DELTAMSTEP_DPLL_DISP Register Field Descriptions..............................................
CM_SSC_MODFREQDIV_DPLL_DISP Register Field Descriptions .............................................
CM_CLKSEL_DPLL_DISP Register Field Descriptions ............................................................
CM_AUTOIDLE_DPLL_CORE Register Field Descriptions........................................................
CM_IDLEST_DPLL_CORE Register Field Descriptions ............................................................
CM_SSC_DELTAMSTEP_DPLL_CORE Register Field Descriptions ............................................
CM_SSC_MODFREQDIV_DPLL_CORE Register Field Descriptions ............................................
CM_CLKSEL_DPLL_CORE Register Field Descriptions ...........................................................
CM_AUTOIDLE_DPLL_PER Register Field Descriptions ..........................................................
CM_IDLEST_DPLL_PER Register Field Descriptions ..............................................................
CM_SSC_DELTAMSTEP_DPLL_PER Register Field Descriptions ..............................................
CM_SSC_MODFREQDIV_DPLL_PER Register Field Descriptions ..............................................
CM_CLKDCOLDO_DPLL_PER Register Field Descriptions.......................................................
CM_DIV_M4_DPLL_CORE Register Field Descriptions ...........................................................
CM_CLKMODE_DPLL_MPU Register Field Descriptions..........................................................
CM_CLKMODE_DPLL_PER Register Field Descriptions ..........................................................
CM_CLKMODE_DPLL_CORE Register Field Descriptions ........................................................
CM_CLKMODE_DPLL_DDR Register Field Descriptions ..........................................................
CM_CLKMODE_DPLL_DISP Register Field Descriptions .........................................................
CM_CLKSEL_DPLL_PERIPH Register Field Descriptions ........................................................
CM_DIV_M2_DPLL_DDR Register Field Descriptions .............................................................
CM_DIV_M2_DPLL_DISP Register Field Descriptions .............................................................
CM_DIV_M2_DPLL_MPU Register Field Descriptions .............................................................
CM_DIV_M2_DPLL_PER Register Field Descriptions..............................................................
CM_WKUP_WKUP_M3_CLKCTRL Register Field Descriptions ..................................................
CM_WKUP_UART0_CLKCTRL Register Field Descriptions ......................................................
CM_WKUP_I2C0_CLKCTRL Register Field Descriptions..........................................................
CM_WKUP_ADC_TSC_CLKCTRL Register Field Descriptions ...................................................
CM_WKUP_SMARTREFLEX0_CLKCTRL Register Field Descriptions ..........................................
CM_WKUP_TIMER1_CLKCTRL Register Field Descriptions .....................................................
CM_WKUP_SMARTREFLEX1_CLKCTRL Register Field Descriptions ..........................................
CM_L4_WKUP_AON_CLKSTCTRL Register Field Descriptions .................................................
CM_WKUP_WDT1_CLKCTRL Register Field Descriptions........................................................
CM_DPLL REGISTERS .................................................................................................
CLKSEL_TIMER7_CLK Register Field Descriptions ................................................................
CM_AUTOIDLE_DPLL_MPU Register Field Descriptions

List of Tables
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
780
782
784
786
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
93
www.ti.com
8-144. CLKSEL_TIMER2_CLK Register Field Descriptions ................................................................ 805

8-147. CM_MAC_CLKSEL Register Field Descriptions ..................................................................... 808

8-150. CM_CPTS_RFT_CLKSEL Register Field Descriptions ............................................................. 811
8-151. CLKSEL_TIMER1MS_CLK Register Field Descriptions ............................................................ 812
8-152. CLKSEL_GFX_FCLK Register Field Descriptions................................................................... 813
8-153. CLKSEL_PRU_ICSS_OCP_CLK Register Field Descriptions ..................................................... 814

8-154. CLKSEL_LCDC_PIXEL_CLK Register Field Descriptions ......................................................... 815
8-155. CLKSEL_WDT1_CLK Register Field Descriptions .................................................................. 816
8-156. CLKSEL_GPIO0_DBCLK Register Field Descriptions .............................................................. 817
817
8-158.
818
8-159.
8-160.
8-161.
8-162.
8-163.
8-164.
8-165.
8-166.
8-167.
8-168.
8-169.
8-170.
8-171.
8-172.
8-173.
8-174.
8-175.
8-176.
8-177.
8-178.
8-179.
8-180.
8-181.
8-182.
8-183.
8-184.
8-185.
8-186.
8-187.
8-188.
8-189.
8-190.
8-191.
8-192.
94
.................................................................................................
CM_MPU_CLKSTCTRL Register Field Descriptions ...............................................................
CM_MPU_MPU_CLKCTRL Register Field Descriptions ...........................................................
CM_DEVICE REGISTERS .............................................................................................
CM_CLKOUT_CTRL Register Field Descriptions ...................................................................
CM_RTC REGISTERS ..................................................................................................
CM_RTC_RTC_CLKCTRL Register Field Descriptions ............................................................
CM_RTC_CLKSTCTRL Register Field Descriptions ................................................................
CM_GFX REGISTERS ..................................................................................................
CM_GFX_L3_CLKSTCTRL Register Field Descriptions ...........................................................
CM_GFX_GFX_CLKCTRL Register Field Descriptions ............................................................
CM_GFX_L4LS_GFX_CLKSTCTRL Register Field Descriptions .................................................
CM_GFX_MMUCFG_CLKCTRL Register Field Descriptions ......................................................
CM_GFX_MMUDATA_CLKCTRL Register Field Descriptions ....................................................
CM_CEFUSE REGISTERS ............................................................................................
CM_CEFUSE_CLKSTCTRL Register Field Descriptions ..........................................................
CM_CEFUSE_CEFUSE_CLKCTRL Register Field Descriptions .................................................
PRM_IRQ REGISTERS .................................................................................................
REVISION_PRM Register Field Descriptions ........................................................................
PRM_IRQSTATUS_MPU Register Field Descriptions ..............................................................
PRM_IRQENABLE_MPU Register Field Descriptions ..............................................................
PRM_IRQSTATUS_M3 Register Field Descriptions ................................................................
PRM_IRQENABLE_M3 Register Field Descriptions ................................................................
PRM_PER REGISTERS ................................................................................................
RM_PER_RSTCTRL Register Field Descriptions ...................................................................
PM_PER_PWRSTST Register Field Descriptions...................................................................
PM_PER_PWRSTCTRL Register Field Descriptions ...............................................................
PRM_WKUP REGISTERS .............................................................................................
RM_WKUP_RSTCTRL Register Field Descriptions.................................................................
PM_WKUP_PWRSTCTRL Register Field Descriptions ............................................................
PM_WKUP_PWRSTST Register Field Descriptions ................................................................
RM_WKUP_RSTST Register Field Descriptions ....................................................................
PRM_MPU REGISTERS................................................................................................
PM_MPU_PWRSTCTRL Register Field Descriptions ..............................................................
PM_MPU_PWRSTST Register Field Descriptions ..................................................................
RM_MPU_RSTST Register Field Descriptions ......................................................................
8-157. CM_MPU REGISTERS
List of Tables
819
819
821
822
823
824
825
826
827
828
829
830
830
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
848
850
852
853

www.ti.com
8-193. PRM_DEVICE REGISTERS............................................................................................ 853

8-194. PRM_RSTCTRL Register Field Descriptions
........................................................................
855
8-195. PRM_RSTTIME Register Field Descriptions ......................................................................... 856

8-196. PRM_RSTST Register Field Descriptions ............................................................................ 857
8-197. PRM_SRAM_COUNT Register Field Descriptions .................................................................. 858
8-198. PRM_LDO_SRAM_CORE_SETUP Register Field Descriptions .................................................. 859

8-199. PRM_LDO_SRAM_CORE_CTRL Register Field Descriptions .................................................... 861
8-200. PRM_LDO_SRAM_MPU_SETUP Register Field Descriptions .................................................... 862
8-201. PRM_LDO_SRAM_MPU_CTRL Register Field Descriptions ...................................................... 864

8-202. PRM_RTC REGISTERS ................................................................................................ 864
8-203. PM_RTC_PWRSTCTRL Register Field Descriptions ............................................................... 866
8-204. PM_RTC_PWRSTST Register Field Descriptions................................................................... 867
8-205. PRM_GFX REGISTERS ................................................................................................ 867

8-206. PM_GFX_PWRSTCTRL Register Field Descriptions ............................................................... 869
8-207. RM_GFX_RSTCTRL Register Field Descriptions ................................................................... 870

8-208. PM_GFX_PWRSTST Register Field Descriptions................................................................... 871
8-209. RM_GFX_RSTST Register Field Descriptions ....................................................................... 872

8-210. PRM_CEFUSE REGISTERS ........................................................................................... 872
8-211. PM_CEFUSE_PWRSTCTRL Register Field Descriptions.......................................................... 873
8-212. PM_CEFUSE_PWRSTST Register Field Descriptions ............................................................. 874
9-1.
9-2.
9-3.
9-4.
9-5.
9-6.
9-7.
9-8.
9-9.
9-10.
9-11.
9-12.
9-13.
9-14.
9-15.
9-16.
9-17.
9-18.
9-19.
9-20.
9-21.
9-22.
9-23.
9-24.
9-25.
9-26.
9-27.
9-28.
9-29.
Pad Control Register Field Descriptions .............................................................................. 876

Mode Selection ........................................................................................................... 877
Pull Selection ............................................................................................................. 877
............................................................................................
Available Sources for Timer[57] and eCAP[02] Events ..........................................................
Selection Mux Values ...................................................................................................
DDR Slew Rate Control Settings ......................................................................................
DDR Impedance Control Settings .....................................................................................
DDR PHY to IO Pin Mapping ...........................................................................................
CONTROL_MODULE REGISTERS ...................................................................................
control_revision Register Field Descriptions .........................................................................
device_id Register Field Descriptions .................................................................................
control_hwinfo Register Field Descriptions ...........................................................................
control_sysconfig Register Field Descriptions .......................................................................
control_status Register Field Descriptions............................................................................
cortex_vbbldo_ctrl Register Field Descriptions ......................................................................
core_sldo_ctrl Register Field Descriptions............................................................................
mpu_sldo_ctrl Register Field Descriptions............................................................................
clk32kdivratio_ctrl Register Field Descriptions .......................................................................
bandgap_ctrl Register Field Descriptions .............................................................................
bandgap_trim Register Field Descriptions ............................................................................
pll_clkinpulow_ctrl Register Field Descriptions.......................................................................
mosc_ctrl Register Field Descriptions .................................................................................
rcosc_ctrl Register Field Descriptions .................................................................................
deepsleep_ctrl Register Field Descriptions ...........................................................................
dev_feature Register Field Descriptions ..............................................................................
init_priority_0 Register Field Descriptions ............................................................................
init_priority_1 Register Field Descriptions ............................................................................
mmu_cfg Register Field Descriptions .................................................................................
Interconnect Priority Values

List of Tables
879
881
883
884
884
884
885
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
95
www.ti.com
9-30.
9-31.
9-32.
9-33.
9-34.
9-35.
9-36.
9-37.
9-38.
9-39.
9-40.
9-41.
9-42.
9-43.
9-44.
9-45.
9-46.
9-47.
9-48.
9-49.
9-50.
9-51.
9-52.
9-53.
9-54.
9-55.
9-56.
9-57.
9-58.
9-59.
9-60.
9-61.
9-62.
9-63.
9-64.
9-65.
9-66.
9-67.
9-68.
9-69.
9-70.
9-71.
9-72.
9-73.
9-74.
9-75.
9-76.
9-77.
9-78.
96
tptc_cfg Register Field Descriptions ................................................................................... 911
.................................................................................
.................................................................................
usb_ctrl1 Register Field Descriptions .................................................................................
usb_sts1 Register Field Descriptions .................................................................................
mac_id0_lo Register Field Descriptions...............................................................................
mac_id0_hi Register Field Descriptions...............................................................................
mac_id1_lo Register Field Descriptions...............................................................................
mac_id1_hi Register Field Descriptions...............................................................................
dcan_raminit Register Field Descriptions .............................................................................
usb_wkup_ctrl Register Field Descriptions ...........................................................................
gmii_sel Register Field Descriptions ..................................................................................
pwmss_ctrl Register Field Descriptions ...............................................................................
mreqprio_0 Register Field Descriptions ...............................................................................
mreqprio_1 Register Field Descriptions ...............................................................................
hw_event_sel_grp1 Register Field Descriptions .....................................................................
smrt_ctrl Register Field Descriptions ..................................................................................
mpuss_hw_debug_sel Register Field Descriptions .................................................................
mpuss_hw_dbg_info Register Field Descriptions....................................................................
vdd_mpu_opp_050 Register Field Descriptions .....................................................................
vdd_mpu_opp_turbo Register Field Descriptions....................................................................
vdd_core_opp_050 Register Field Descriptions .....................................................................
vdd_core_opp_100 Register Field Descriptions .....................................................................
bb_scale Register Field Descriptions .................................................................................
usb_vid_pid Register Field Descriptions ..............................................................................
conf_<module>_<pin> Register Field Descriptions .................................................................
cqdetect_status Register Field Descriptions .........................................................................
ddr_io_ctrl Register Field Descriptions ................................................................................
vtp_ctrl Register Field Descriptions ....................................................................................
vref_ctrl Register Field Descriptions ...................................................................................
tpcc_evt_mux_0_3 Register Field Descriptions ......................................................................
tpcc_evt_mux_4_7 Register Field Descriptions ......................................................................
tpcc_evt_mux_8_11 Register Field Descriptions ....................................................................
tpcc_evt_mux_12_15 Register Field Descriptions ...................................................................
usb_ctrl0 Register Field Descriptions
912
usb_sts0 Register Field Descriptions
914
List of Tables
915
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961

www.ti.com
9-79.
9-80.
9-81.
9-82.
tpcc_evt_mux_56_59 Register Field Descriptions ................................................................... 962

tpcc_evt_mux_60_63 Register Field Descriptions ................................................................... 963
timer_evt_capt Register Field Descriptions ........................................................................... 964
ecap_evt_capt Register Field Descriptions ........................................................................... 965
9-83.
adc_evt_capt Register Field Descriptions ............................................................................ 966
9-84.
reset_iso Register Field Descriptions
9-85.
9-86.
9-87.
9-88.
9-89.
9-90.
9-91.
9-92.
9-93.
9-94.
9-95.
9-96.
9-97.
9-98.
9-99.
9-100.
10-1.
10-2.
11-1.
11-2.
11-3.
11-4.
11-5.
11-6.
11-7.
11-8.
11-9.
11-10.
11-11.
11-12.
11-13.
11-14.
11-15.
11-16.
11-17.
11-18.
11-19.
11-20.
11-21.
11-22.
11-23.
11-24.
11-25.
................................................................................. 967
ddr_cke_ctrl Register Field Descriptions .............................................................................. 968
sma2 Register Field Descriptions ...................................................................................... 969
m3_txev_eoi Register Field Descriptions ............................................................................. 970
ipc_msg_reg0 Register Field Descriptions ........................................................................... 971
ddr_cmd0_ioctrl Register Field Descriptions ......................................................................... 979
ddr_data0_ioctrl Register Field Descriptions ......................................................................... 985
ddr_data1_ioctrl Register Field Descriptions ......................................................................... 987
L3 Master Slave Connectivity ....................................................................................... 992
MConnID Assignment ................................................................................................... 992
TPCC Connectivity Attributes .......................................................................................... 999
TPCC Clock Signals ..................................................................................................... 999
TPTC Connectivity Attributes ......................................................................................... 1000
TPTC Clock Signals .................................................................................................... 1000
EDMA3 Parameter RAM Contents ................................................................................... 1008
EDMA3 Channel Parameter Description ............................................................................ 1010
Channel Options Parameters (OPT) Field Descriptions ........................................................... 1011
Dummy and Null Transfer Request .................................................................................. 1015
Parameter Updates in EDMA3CC (for Non-Null, Non-Dummy PaRAM Set) ................................... 1016
Expected Number of Transfers for Non-Null Transfer ............................................................. 1022
Shadow Region Registers ............................................................................................. 1026
Chain Event Triggers .................................................................................................. 1028
EDMA3 Transfer Completion Interrupts ............................................................................. 1028
EDMA3 Error Interrupts ................................................................................................ 1028
Transfer Complete Code (TCC) to EDMA3CC Interrupt Mapping ............................................... 1029
Number of Interrupts ................................................................................................... 1029
Allowed Accesses ...................................................................................................... 1034
MPPA Registers to Region Assignment ............................................................................. 1034
Example Access Denied ............................................................................................... 1035
Example Access Allowed .............................................................................................. 1036
Read/Write Command Optimization Rules .......................................................................... 1040
EDMA3 Transfer Controller Configurations ......................................................................... 1042
Direct Mapped .......................................................................................................... 1062
Crossbar Mapped ...................................................................................................... 1063
EDMACC Registers .................................................................................................... 1065

List of Tables
97
www.ti.com
11-26. Peripheral ID Register (PID) Field Descriptions .................................................................... 1068
11-27. EDMA3CC Configuration Register (CCCFG) Field Descriptions................................................. 1069

1071
11-29. DMA Channel Map n Registers (DCHMAPn) Field Descriptions
1072
11-30.
1073
11-31.
11-32.
11-33.
11-34.
11-35.
11-36.
11-37.
11-38.
11-39.
11-40.
11-41.
11-42.
11-43.
11-44.
11-45.
11-46.
11-47.
11-48.
11-49.
11-50.
11-51.
11-52.
11-53.
11-54.
11-55.
11-56.
11-57.
11-58.
11-59.
11-60.
11-61.
11-62.
11-63.
11-64.
11-65.
11-66.
11-67.
11-68.
11-69.
11-70.
11-71.
11-72.
11-73.
11-74.
98
................................
................................................
QDMA Channel Map n Registers (QCHMAPn) Field Descriptions ..............................................
DMA Channel Queue n Number Registers (DMAQNUMn) Field Descriptions .................................
Bits in DMAQNUMn ...................................................................................................
QDMA Channel Queue Number Register (QDMAQNUM) Field Descriptions ..................................
Queue Priority Register (QUEPRI) Field Descriptions.............................................................
Event Missed Register (EMR) Field Descriptions ..................................................................
Event Missed Register High (EMRH) Field Descriptions ..........................................................
Event Missed Clear Register (EMCR) Field Descriptions .........................................................
Event Missed Clear Register High (EMCRH) Field Descriptions ................................................
QDMA Event Missed Register (QEMR) Field Descriptions .......................................................
QDMA Event Missed Clear Register (QEMCR) Field Descriptions ..............................................
EDMA3CC Error Register (CCERR) Field Descriptions ...........................................................
EDMA3CC Error Clear Register (CCERRCLR) Field Descriptions ..............................................
Error Evaluation Register (EEVAL) Field Descriptions ............................................................
DMA Region Access Enable Registers for Region M (DRAEm/DRAEHm) Field Descriptions ..............
QDMA Region Access Enable for Region M (QRAEm) Field Descriptions .....................................
Event Queue Entry Registers (QxEy) Field Descriptions .........................................................
Queue Status Register n (QSTATn) Field Descriptions ...........................................................
Queue Watermark Threshold A Register (QWMTHRA) Field Descriptions ....................................
EDMA3CC Status Register (CCSTAT) Field Descriptions ........................................................
Memory Protection Fault Address Register (MPFAR) Field Descriptions.......................................
Memory Protection Fault Status Register (MPFSR) Field Descriptions .........................................
Memory Protection Fault Command Register (MPFCR) Field Descriptions ....................................
Memory Protection Page Attribute Register (MPPAn) Field Descriptions ......................................
Event Register (ER) Field Descriptions..............................................................................
Event Register High (ERH) Field Descriptions .....................................................................
Event Clear Register (ECR) Field Descriptions ....................................................................
Event Clear Register High (ECRH) Field Descriptions ............................................................
Event Set Register (ESR) Field Descriptions .......................................................................
Event Set Register High (ESRH) Field Descriptions...............................................................
Chained Event Register (CER) Field Descriptions .................................................................
Chained Event Register High (CERH) Field Descriptions ........................................................
Event Enable Register (EER) Field Descriptions...................................................................
Event Enable Register High (EERH) Field Descriptions ..........................................................
Event Enable Clear Register (EECR) Field Descriptions .........................................................
Event Enable Clear Register High (EECRH) Field Descriptions .................................................
Event Enable Set Register (EESR) Field Descriptions ...........................................................
Event Enable Set Register High (EESRH) Field Descriptions....................................................
Secondary Event Register (SER) Field Descriptions ..............................................................
Secondary Event Register High (SERH) Field Descriptions ......................................................
Secondary Event Clear Register (SECR) Field Descriptions .....................................................
Secondary Event Clear Register High (SECRH) Field Descriptions.............................................
Interrupt Enable Register (IER) Field Descriptions ................................................................
Interrupt Enable Register High (IERH) Field Descriptions ........................................................
Interrupt Enable Clear Register (IECR) Field Descriptions .......................................................
11-28. EDMA3CC System Configuration Register (SYSCONFIG) Field Descriptions
List of Tables
1074
1074
1075
1076
1077
1077
1078
1078
1079
1080
1081
1081
1083
1084
1085
1086
1087
1088
1089
1091
1092
1093
1094
1096
1096
1097
1097
1098
1099
1100
1101
1102
1102
1103
1103
1104
1104
1105
1105
1106
1106
1107
1107
1108

www.ti.com
11-75. Interrupt Enable Clear Register High (IECRH) Field Descriptions ............................................... 1108
11-76. Interrupt Enable Set Register (IESR) Field Descriptions .......................................................... 1109
11-77. Interrupt Enable Set Register High (IESRH) Field Descriptions
.................................................
1109
11-78. Interrupt Pending Register (IPR) Field Descriptions ............................................................... 1110

11-79. Interrupt Pending Register High (IPRH) Field Descriptions ....................................................... 1110
11-80. Interrupt Clear Register (ICR) Field Descriptions .................................................................. 1111

11-81. Interrupt Clear Register High (ICRH) Field Descriptions .......................................................... 1111
11-82. Interrupt Evaluate Register (IEVAL) Field Descriptions ........................................................... 1112
11-83. QDMA Event Register (QER) Field Descriptions................................................................... 1113

11-84. QDMA Event Enable Register (QEER) Field Descriptions........................................................ 1114
..............................................
11-86. QDMA Event Enable Set Register (QEESR) Field Descriptions .................................................
11-87. QDMA Secondary Event Register (QSER) Field Descriptions ...................................................
11-88. QDMA Secondary Event Clear Register (QSECR) Field Descriptions ..........................................
11-89. EDMA3TC Registers ...................................................................................................
11-90. Peripheral ID Register (PID) Field Descriptions ....................................................................
11-91. EDMA3TC Configuration Register (TCCFG) Field Descriptions .................................................
11-92. EDMA3TC Channel Status Register (TCSTAT) Field Descriptions .............................................
11-93. Error Register (ERRSTAT) Field Descriptions ......................................................................
11-94. Error Enable Register (ERREN) Field Descriptions................................................................
11-95. Error Clear Register (ERRCLR) Field Descriptions ................................................................
11-96. Error Details Register (ERRDET) Field Descriptions ..............................................................
11-97. Error Interrupt Command Register (ERRCMD) Field Descriptions ..............................................
11-98. Read Rate Register (RDRATE) Field Descriptions ................................................................
11-99. Source Active Options Register (SAOPT) Field Descriptions ....................................................
11-100. Source Active Source Address Register (SASRC) Field Descriptions .........................................
11-101. Source Active Count Register (SACNT) Field Descriptions .....................................................
11-102. Source Active Destination Address Register (SADST) Field Descriptions ....................................
11-103. Source Active Source B-Dimension Index Register (SABIDX) Field Descriptions ...........................
11-104. Source Active Memory Protection Proxy Register (SAMPPRXY) Field Descriptions ........................
11-105. Source Active Count Reload Register (SACNTRLD) Field Descriptions ......................................
11-106. Source Active Source Address B-Reference Register (SASRCBREF) Field Descriptions ..................
11-107. Source Active Destination Address B-Reference Register (SADSTBREF) Field Descriptions .............
11-108. Destination FIFO Options Register (DFOPTn) Field Descriptions ..............................................
11-109. Destination FIFO Source Address Register (DFSRCn) Field Descriptions....................................
11-110. Destination FIFO Count Register (DFCNTn) Field Descriptions ................................................
11-111. Destination FIFO Destination Address Register (DFDSTn) Field Descriptions ...............................
11-112. Destination FIFO B-Index Register (DFBIDXn) Field Descriptions .............................................
11-113. Destination FIFO Memory Protection Proxy Register (DFMPPRXYn) Field Descriptions ...................
11-114. Destination FIFO Count Reload Register (DFCNTRLDn) Field Descriptions .................................
11-115. Destination FIFO Source Address B-Reference Register (DFSRCBREFn) Field Descriptions ............
11-116. Destination FIFO Destination Address B-Reference Register (DFDSTBREFn) Field Descriptions ........
11-117. Debug List ..............................................................................................................
12-1. TSC_ADC Connectivity Attributes ....................................................................................
12-2. TSC_ADC Clock Signals ..............................................................................................
12-3. TSC_ADC Pin List ......................................................................................................
12-4. TSC_ADC_SS REGISTERS ..........................................................................................
12-5. REVISION Register Field Descriptions ..............................................................................
12-6. SYSCONFIG Register Field Descriptions ...........................................................................
11-85. QDMA Event Enable Clear Register (QEECR) Field Descriptions

List of Tables
1115
1116
1117
1118
1119
1120
1121
1122
1124
1125
1126
1127
1128
1129
1130
1132
1132
1133
1133
1134
1135
1135
1136
1137
1139
1139
1140
1140
1141
1142
1142
1143
1143
1149
1150
1150
1157
1159
1160
99
www.ti.com
12-7.
IRQSTATUS_RAW Register Field Descriptions.................................................................... 1161
12-8.
IRQSTATUS Register Field Descriptions
...........................................................................
1163
12-10. IRQENABLE_CLR Register Field Descriptions
1167
12-11.
....................................................................
IRQWAKEUP Register Field Descriptions ..........................................................................
DMAENABLE_SET Register Field Descriptions ...................................................................
DMAENABLE_CLR Register Field Descriptions ...................................................................
CTRL Register Field Descriptions ....................................................................................
ADCSTAT Register Field Descriptions ..............................................................................
ADCRANGE Register Field Descriptions............................................................................
ADC_CLKDIV Register Field Descriptions ..........................................................................
ADC_MISC Register Field Descriptions .............................................................................
STEPENABLE Register Field Descriptions .........................................................................
IDLECONFIG Register Field Descriptions ..........................................................................
TS_CHARGE_STEPCONFIG Register Field Descriptions .......................................................
TS_CHARGE_DELAY Register Field Descriptions ................................................................
STEPCONFIG1 Register Field Descriptions ........................................................................
STEPDELAY1 Register Field Descriptions .........................................................................
STEPCONFIG10 Register Field Descriptions ......................................................................
STEPDELAY10 Register Field Descriptions ........................................................................
FIFO0COUNT Register Field Descriptions..........................................................................
1169
12-9.
12-12.
12-13.
12-14.
12-15.
12-16.
12-17.
12-18.
12-19.
12-20.
12-21.
12-22.
12-23.
12-24.
12-25.
12-26.
12-27.
12-28.
12-29.
12-30.
12-31.
12-32.
12-33.
12-34.
12-35.
12-36.
12-37.
12-38.
12-39.
12-40.
12-41.
12-42.
12-43.
12-44.
12-45.
12-46.
12-47.
12-48.
12-49.
12-50.
12-51.
12-52.
12-53.
12-54.
12-55.
100
IRQENABLE_SET Register Field Descriptions ..................................................................... 1165
List of Tables
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213

www.ti.com
12-56. FIFO0THRESHOLD Register Field Descriptions................................................................... 1214

12-57. DMA0REQ Register Field Descriptions
.............................................................................
1215
12-58. FIFO1COUNT Register Field Descriptions.......................................................................... 1216
12-59. FIFO1THRESHOLD Register Field Descriptions................................................................... 1217

12-60. DMA1REQ Register Field Descriptions
.............................................................................
1218
12-61. FIFO0DATA Register Field Descriptions ............................................................................ 1219

12-62. FIFO1DATA Register Field Descriptions ............................................................................ 1220
13-1.
..............................................................................
1224
................................................................................................
1225
LCD Controller Connectivity Attributes
13-2.
LCD Controller Clock Signals ......................................................................................... 1225
13-3.
LCD Controller Pin List
13-4.
LCD External I/O Signals .............................................................................................. 1228
13-5.
Register Configuration for DMA Engine Programming ............................................................ 1229
13-6.
LIDD I/O Name Map
13-7.
13-8.
13-9.
...................................................................................................
1231
Operation Modes Supported by Raster Controller ................................................................. 1232

Bits-Per-Pixel Encoding for Palette Entry 0 Buffer ................................................................. 1234
Frame Buffer Size According to BPP ................................................................................ 1235
13-10. Color/Grayscale Intensities and Modulation Rates
................................................................
1239
13-11. Number of Colors/Shades of Gray Available on Screen .......................................................... 1239
13-12. Highlander 0.8 Interrupt Module Control Registers ................................................................ 1243

13-13. LCD REGISTERS ...................................................................................................... 1252
13-14. PID Register Field Descriptions ...................................................................................... 1254
13-15. CTRL Register Field Descriptions .................................................................................... 1255

13-16. LIDD_CTRL Register Field Descriptions ............................................................................ 1256
13-17. LIDD_CS0_CONF Register Field Descriptions ..................................................................... 1257
13-18. LIDD_CS0_ADDR Register Field Descriptions ..................................................................... 1258
13-19. LIDD_CS0_DATA Register Field Descriptions ..................................................................... 1259

13-20. LIDD_CS1_CONF Register Field Descriptions ..................................................................... 1260
13-21. LIDD_CS1_ADDR Register Field Descriptions ..................................................................... 1261
13-22. LIDD_CS1_DATA Register Field Descriptions ..................................................................... 1262

13-23. RASTER_CTRL Register Field Descriptions
.......................................................................
1263
13-24. RASTER_TIMING_0 Register Field Descriptions .................................................................. 1266

13-27. RASTER_SUBPANEL Register Field Descriptions ................................................................ 1270

13-28. RASTER_SUBPANEL2 Register Field Descriptions
..............................................................
1271
13-29. LCDDMA_CTRL Register Field Descriptions ....................................................................... 1272
13-30. LCDDMA_FB0_BASE Register Field Descriptions ................................................................ 1274

13-31. LCDDMA_FB0_CEILING Register Field Descriptions ............................................................. 1275
13-32. LCDDMA_FB1_BASE Register Field Descriptions ................................................................ 1276

13-33. LCDDMA_FB1_CEILING Register Field Descriptions ............................................................. 1277
13-34. SYSCONFIG Register Field Descriptions ........................................................................... 1278

13-35. IRQSTATUS_RAW Register Field Descriptions.................................................................... 1280
13-36. IRQSTATUS Register Field Descriptions
...........................................................................
1282
13-37. IRQENABLE_SET Register Field Descriptions ..................................................................... 1284
13-38. IRQENABLE_CLEAR Register Field Descriptions ................................................................. 1286
.......................................................................
CLKC_RESET Register Field Descriptions .........................................................................
Unsupported CPGMAC Features ....................................................................................
Ethernet Switch Connectivity Attributes .............................................................................
13-39. CLKC_ENABLE Register Field Descriptions

13-40.
14-1.
14-2.

List of Tables
1288
1289
1292
1294
101
www.ti.com
14-3.
14-4.
14-5.
14-6.
14-7.
14-8.
14-9.
14-10.
14-11.
14-12.
14-13.
14-14.
14-15.
14-16.
14-17.
14-18.
14-19.
14-20.
14-21.
14-22.
14-23.
14-24.
14-25.
14-26.
14-27.
14-28.
14-29.
14-30.
14-31.
14-32.
14-33.
14-34.
14-35.
14-36.
14-37.
14-38.
14-39.
14-40.
14-41.
14-42.
14-43.
14-44.
14-45.
14-46.
14-47.
14-48.
14-49.
14-50.
14-51.
102
Ethernet Switch Clock Signals ........................................................................................ 1295
Ethernet Switch Pin List ............................................................................................... 1296
...................................................
..................................................
RMII Interface Signal Descriptions ...................................................................................
RGMII Interface Signal Descriptions .................................................................................
VLAN Header Encapsulation Word Field Descriptions ............................................................
Learned Address Control Bits.........................................................................................
Free (Unused) Address Table Entry Bit Values ....................................................................
Multicast Address Table Entry Bit Values ...........................................................................
VLAN/Multicast Address Table Entry Bit Values ...................................................................
Unicast Address Table Entry Bit Values.............................................................................
OUI Unicast Address Table Entry Bit Values .......................................................................
Unicast Address Table Entry Bit Values.............................................................................
VLAN Table Entry ......................................................................................................
Operations of Emulation Control Input and Register Bits .........................................................
Rx Statistics Summary .................................................................................................
Tx Statistics Summary .................................................................................................
Values of messageType field .........................................................................................
MDIO Read Frame Format ............................................................................................
MDIO Write Frame Format ............................................................................................
CPSW_ALE REGISTERS .............................................................................................
IDVER Register Field Descriptions...................................................................................
CONTROL Register Field Descriptions ..............................................................................
PRESCALE Register Field Descriptions ............................................................................
UNKNOWN_VLAN Register Field Descriptions ....................................................................
TBLCTL Register Field Descriptions .................................................................................
TBLW2 Register Field Descriptions ..................................................................................
PORTCTL0 Register Field Descriptions .............................................................................
CPSW_CPDMA REGISTERS ........................................................................................
TX_IDVER Register Field Descriptions ..............................................................................
TX_CONTROL Register Field Descriptions .........................................................................
TX_TEARDOWN Register Field Descriptions ......................................................................
RX_IDVER Register Field Descriptions .............................................................................
RX_CONTROL Register Field Descriptions ........................................................................
RX_TEARDOWN Register Field Descriptions ......................................................................
CPDMA_SOFT_RESET Register Field Descriptions ..............................................................
DMACONTROL Register Field Descriptions ........................................................................
DMASTATUS Register Field Descriptions ..........................................................................
RX_BUFFER_OFFSET Register Field Descriptions ...............................................................
EMCONTROL Register Field Descriptions..........................................................................
TX_PRI0_RATE Register Field Descriptions .......................................................................
GMII Interface Signal Descriptions in GIG (1000Mbps) Mode
1298
GMII Interface Signal Descriptions in MII (100/10Mbps) Mode
1299
List of Tables
1300
1302
1321
1322
1322
1323
1323
1324
1325
1326
1327
1337
1346
1347
1360
1361
1361
1368
1369
1370
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1386
1387
1388
1389
1390
1391
1392
1393
1395
1397
1398
1399

www.ti.com
14-52. TX_PRI1_RATE Register Field Descriptions ....................................................................... 1400

14-59. TX_INTSTAT_RAW Register Field Descriptions ................................................................... 1407

14-60. TX_INTSTAT_MASKED Register Field Descriptions .............................................................. 1408
14-61. TX_INTMASK_SET Register Field Descriptions ................................................................... 1409
...............................................................
14-63. CPDMA_IN_VECTOR Register Field Descriptions ................................................................
14-64. CPDMA_EOI_VECTOR Register Field Descriptions ..............................................................
14-65. RX_INTSTAT_RAW Register Field Descriptions...................................................................
14-66. RX_INTSTAT_MASKED Register Field Descriptions .............................................................
14-67. RX_INTMASK_SET Register Field Descriptions ...................................................................
14-68. RX_INTMASK_CLEAR Register Field Descriptions ...............................................................
14-69. DMA_INTSTAT_RAW Register Field Descriptions ................................................................
14-70. DMA_INTSTAT_MASKED Register Field Descriptions ...........................................................
14-71. DMA_INTMASK_SET Register Field Descriptions.................................................................
14-72. DMA_INTMASK_CLEAR Register Field Descriptions .............................................................
14-73. RX0_PENDTHRESH Register Field Descriptions .................................................................
14-81. RX0_FREEBUFFER Register Field Descriptions ..................................................................
14-89. CPSW_CPTS REGISTERS ...........................................................................................
14-90. CPTS_IDVER Register Field Descriptions ..........................................................................
14-91. CPTS_CONTROL Register Field Descriptions .....................................................................
14-92. CPTS_TS_PUSH Register Field Descriptions ......................................................................
14-93. CPTS_TS_LOAD_VAL Register Field Descriptions ...............................................................
14-94. CPTS_TS_LOAD_EN Register Field Descriptions.................................................................
14-95. CPTS_INTSTAT_RAW Register Field Descriptions ...............................................................
14-96. CPTS_INTSTAT_MASKED Register Field Descriptions ..........................................................
14-97. CPTS_INT_ENABLE Register Field Descriptions ..................................................................
14-98. CPTS_EVENT_POP Register Field Descriptions ..................................................................
14-99. CPTS_EVENT_LOW Register Field Descriptions .................................................................
14-100. CPTS_EVENT_HIGH Register Field Descriptions ...............................................................
14-62. TX_INTMASK_CLEAR Register Field Descriptions

List of Tables
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434
1435
1436
1436
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
103
www.ti.com
14-101. CPSW_STATS REGISTERS ........................................................................................ 1449

14-102. CPDMA_STATERAM REGISTERS ................................................................................ 1449
14-103. TX0_HDP Register Field Descriptions ............................................................................. 1452
14-111. RX0_HDP Register Field Descriptions ............................................................................. 1460
14-119. TX0_CP Register Field Descriptions ............................................................................... 1468

14-127. RX0_CP Register Field Descriptions ............................................................................... 1476
14-135. CPSW_PORT REGISTERS ......................................................................................... 1483
.......................................................................
P0_MAX_BLKS Register Field Descriptions ......................................................................
P0_BLK_CNT Register Field Descriptions ........................................................................
P0_TX_IN_CTL Register Field Descriptions ......................................................................
P0_PORT_VLAN Register Field Descriptions.....................................................................
P0_TX_PRI_MAP Register Field Descriptions ....................................................................
P0_CPDMA_TX_PRI_MAP Register Field Descriptions.........................................................
P0_CPDMA_RX_CH_MAP Register Field Descriptions .........................................................
P0_RX_DSCP_PRI_MAP0 Register Field Descriptions .........................................................
14-136. P0_CONTROL Register Field Descriptions

14-137.
14-138.
14-139.
14-140.
14-141.
14-142.
14-143.
14-144.
14-145.
14-146.
14-147.
14-148.
14-149.
104
List of Tables
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499

www.ti.com
14-150. P0_RX_DSCP_PRI_MAP6 Register Field Descriptions ......................................................... 1500
14-151. P0_RX_DSCP_PRI_MAP7 Register Field Descriptions ......................................................... 1501
.......................................................................
......................................................................
P1_TS_SEQ_MTYPE Register Field Descriptions ...............................................................
P1_SA_LO Register Field Descriptions ............................................................................
P1_SA_HI Register Field Descriptions .............................................................................
P1_SEND_PERCENT Register Field Descriptions ...............................................................
P2_CONTROL Register Field Descriptions .......................................................................
P2_MAX_BLKS Register Field Descriptions ......................................................................
P2_TS_SEQ_MTYPE Register Field Descriptions ...............................................................
P2_SA_LO Register Field Descriptions ............................................................................
P2_SA_HI Register Field Descriptions .............................................................................
P2_SEND_PERCENT Register Field Descriptions ...............................................................
CPSW_SL REGISTERS .............................................................................................
IDVER Register Field Descriptions .................................................................................
MACCONTROL Register Field Descriptions ......................................................................
MACSTATUS Register Field Descriptions .........................................................................
SOFT_RESET Register Field Descriptions ........................................................................
RX_MAXLEN Register Field Descriptions .........................................................................
BOFFTEST Register Field Descriptions ...........................................................................
RX_PAUSE Register Field Descriptions ...........................................................................
TX_PAUSE Register Field Descriptions ...........................................................................
EMCONTROL Register Field Descriptions ........................................................................
RX_PRI_MAP Register Field Descriptions ........................................................................
14-152. P1_CONTROL Register Field Descriptions
1502
14-153. P1_MAX_BLKS Register Field Descriptions
1504
14-154.
1505
14-155.
14-156.
14-157.
14-158.
14-159.
14-160.
14-161.
14-162.
14-163.
14-164.
14-165.
14-166.
14-167.
14-168.
14-169.
14-170.
14-171.
14-172.
14-173.
14-174.
14-175.
14-176.
14-177.
14-178.
14-179.
14-180.
14-181.
14-182.
14-183.
14-184.
14-185.
14-186.
14-187.
14-188.
14-189.
14-190.
14-191.
14-192.
14-193.
14-194.
14-195.
14-196.
14-197.
14-198.

List of Tables
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1545
1546
1547
1548
1549
1550
1551
1552
105
www.ti.com
14-199. TX_GAP Register Field Descriptions ............................................................................... 1553
14-200. CPSW_SS REGISTERS ............................................................................................. 1553

14-201. ID_VER Register Field Descriptions ................................................................................ 1554
14-202. CONTROL Register Field Descriptions ............................................................................ 1555

14-203. SOFT_RESET Register Field Descriptions ........................................................................ 1556
14-204. STAT_PORT_EN Register Field Descriptions .................................................................... 1557

14-205. PTYPE Register Field Descriptions................................................................................. 1558
14-206. SOFT_IDLE Register Field Descriptions ........................................................................... 1559
14-207. THRU_RATE Register Field Descriptions ......................................................................... 1560
14-208. GAP_THRESH Register Field Descriptions ....................................................................... 1561
14-209. TX_START_WDS Register Field Descriptions .................................................................... 1562
14-210. FLOW_CONTROL Register Field Descriptions ................................................................... 1563

14-211. VLAN_LTYPE Register Field Descriptions ........................................................................ 1564
14-212. TS_LTYPE Register Field Descriptions ............................................................................ 1565

14-213. DLR_LTYPE Register Field Descriptions .......................................................................... 1566
14-214. CPSW_WR REGISTERS ............................................................................................ 1566

14-215. IDVER Register Field Descriptions ................................................................................. 1568
14-216. SOFT_RESET Register Field Descriptions ........................................................................ 1569
14-217. CONTROL Register Field Descriptions ............................................................................ 1570
......................................................................
1571
...........................................................................
1573
14-222. C0_MISC_EN Register Field Descriptions
1575
14-223.
........................................................................
C1_RX_THRESH_EN Register Field Descriptions ...............................................................
C1_RX_EN Register Field Descriptions ...........................................................................
C1_TX_EN Register Field Descriptions ............................................................................
C1_MISC_EN Register Field Descriptions ........................................................................
C2_RX_THRESH_EN Register Field Descriptions ...............................................................
C2_RX_EN Register Field Descriptions ...........................................................................
C2_TX_EN Register Field Descriptions ............................................................................
C2_MISC_EN Register Field Descriptions ........................................................................
C0_RX_THRESH_STAT Register Field Descriptions ............................................................
C0_RX_STAT Register Field Descriptions ........................................................................
C0_TX_STAT Register Field Descriptions .........................................................................
C0_MISC_STAT Register Field Descriptions .....................................................................
C0_RX_IMAX Register Field Descriptions .........................................................................
C0_TX_IMAX Register Field Descriptions .........................................................................
C1_TX_IMAX Register Field Descriptions .........................................................................
1576
14-218. INT_CONTROL Register Field Descriptions
14-219. C0_RX_THRESH_EN Register Field Descriptions ............................................................... 1572

14-220. C0_RX_EN Register Field Descriptions
14-221. C0_TX_EN Register Field Descriptions ............................................................................ 1574
14-224.
14-225.
14-226.
14-227.
14-228.
14-229.
14-230.
14-231.
14-232.
14-233.
14-234.
14-235.
14-236.
14-237.
14-238.
14-239.
14-240.
14-241.
14-242.
14-243.
14-244.
14-245.
14-246.
14-247.
106
List of Tables
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600

www.ti.com
14-248. C2_TX_IMAX Register Field Descriptions ......................................................................... 1601
14-249. RGMII_CTL Register Field Descriptions ........................................................................... 1602

14-250. Management Data Input/Output (MDIO) Registers ............................................................... 1602
14-251. MDIO Version Register (MDIOVER) Field Descriptions ......................................................... 1603

14-252. MDIO Control Register (MDIOCONTROL) Field Descriptions .................................................. 1604
14-253. PHY Acknowledge Status Register (MDIOALIVE) Field Descriptions ......................................... 1605
14-254. PHY Link Status Register (MDIOLINK) Field Descriptions ...................................................... 1605
14-255. MDIO Link Status Change Interrupt Register (MDIOLINKINTRAW) Field Descriptions ..................... 1606
14-256. MDIO Link Status Change Interrupt Register (Masked Value) (MDIOLINKINTMASKED) Field
Descriptions ............................................................................................................. 1606
14-257. MDIO User Command Complete Interrupt Register (Raw Value) (MDIOUSERINTRAW) Field
Descriptions ............................................................................................................. 1607
14-258. MDIO User Command Complete Interrupt Register (Masked Value) (MDIOUSERINTMASKED) Field
Descriptions ............................................................................................................. 1607
14-259. MDIO User Command Complete Interrupt Mask Set Register (MDIOUSERINTMASKSET) Field
Descriptions ............................................................................................................. 1608
14-260. MDIO User Command Complete Interrupt Mask Clear Register (MDIOUSERINTMASKCLR) Field
Descriptions ............................................................................................................. 1608
14-261. MDIO User Access Register 0 (MDIOUSERACCESS0) Field Descriptions
..................................
1609
14-263. MDIO User Access Register 1 (MDIOUSERACCESS1) Field Descriptions
..................................
1611
14-262. MDIO User PHY Select Register 0 (MDIOUSERPHYSEL0) Field Descriptions .............................. 1610
14-264. MDIO User PHY Select Register 1 (MDIOUSERPHYSEL1) Field Descriptions .............................. 1612
15-1.
15-2.
15-3.
Unsupported Features ................................................................................................. 1614
PWMSS Connectivity Attributes ...................................................................................... 1616

PWMSS Clock Signals................................................................................................. 1617
15-4.
PWMSS Pin List ........................................................................................................ 1617
15-5.
PWMSS Submodule Register Map
15-6.
15-7.
15-8.
15-9.
15-10.
15-11.
15-12.
15-13.
15-14.
15-15.
15-16.
15-17.
15-18.
15-19.
15-20.
15-21.
15-22.
15-23.
15-24.
15-25.
15-26.
15-27.
15-28.
..................................................................................
IP Revision Register (IDVER) Field Descriptions ..................................................................
System Configuration Register (SYSCONFIG) Field Descriptions ..............................................
Clock Configuration Register (CLKCONFG) Field Descriptions ..................................................
Clock Status Register (CLKSTATUS) Field Descriptions .........................................................
Submodule Configuration Parameters ...............................................................................
Time-Base Submodule Registers ....................................................................................
Key Time-Base Signals ................................................................................................
Counter-Compare Submodule Registers ...........................................................................
Counter-Compare Submodule Key Signals .........................................................................
Action-Qualifier Submodule Registers ...............................................................................
Action-Qualifier Submodule Possible Input Events ................................................................
Action-Qualifier Event Priority for Up-Down-Count Mode .........................................................
Action-Qualifier Event Priority for Up-Count Mode .................................................................
Action-Qualifier Event Priority for Down-Count Mode .............................................................
Behavior if CMPA/CMPB is Greater than the Period ..............................................................
EPWMx Initialization for ...............................................................................................
EPWMx Run Time Changes for .....................................................................................

List of Tables
1618
1619
1620
1621
1622
1627
1632
1633
1641
1641
1645
1646
1648
1648
1648
1649
1652
1652
1654
1654
1656
1656
1658
1658
107
www.ti.com
1660
15-30.
1660
15-31.
15-32.
15-33.
15-34.
15-35.
15-36.
15-37.
15-38.
15-39.
15-40.
15-41.
15-42.
15-43.
15-44.
15-45.
15-46.
15-47.
15-48.
15-49.
15-50.
15-51.
15-52.
15-53.
15-54.
15-55.
15-56.
15-57.
15-58.
15-59.
15-60.
15-61.
15-62.
15-63.
15-64.
15-65.
15-66.
15-67.
15-68.
15-69.
15-70.
15-71.
15-72.
15-73.
15-74.
15-75.
15-76.
15-77.
108
...............................................................................................
Dead-Band Generator Submodule Registers .......................................................................
Classical Dead-Band Operating Modes ............................................................................
PWM-Chopper Submodule Registers ...............................................................................
Trip-Zone Submodule Registers ......................................................................................
Possible Actions On a Trip Event ....................................................................................
Event-Trigger Submodule Registers ................................................................................
Resolution for PWM and HRPWM ...................................................................................
HRPWM Submodule Registers .......................................................................................
Relationship Between MEP Steps, PWM Frequency and Resolution ...........................................
CMPA vs Duty (left), and [CMPA:CMPAHR] vs Duty (right) ......................................................
EPWM1 Initialization for ..............................................................................................
ePWM Module Control and Status Registers Grouped by Submodule .........................................
Time-Base Submodule Registers ....................................................................................
Time-Base Control Register (TBCTL) Field Descriptions .........................................................
Time-Base Status Register (TBSTS) Field Descriptions ..........................................................
Time-Base Phase Register (TBPHS) Field Descriptions ..........................................................
Time-Base Counter Register (TBCNT) Field Descriptions ........................................................
Time-Base Period Register (TBPRD) Field Descriptions .........................................................
Counter-Compare Submodule Registers ............................................................................
Counter-Compare Control Register (CMPCTL) Field Descriptions .............................................
Counter-Compare A Register (CMPA) Field Descriptions ........................................................
Counter-Compare B Register (CMPB) Field Descriptions ........................................................
Action-Qualifier Submodule Registers ...............................................................................
Action-Qualifier Output A Control Register (AQCTLA) Field Descriptions .....................................
Action-Qualifier Output B Control Register (AQCTLB) Field Descriptions .....................................
Action-Qualifier Software Force Register (AQSFRC) Field Descriptions .......................................
Action-Qualifier Continuous Software Force Register (AQCSFRC) Field Descriptions .......................
Dead-Band Generator Submodule Registers .......................................................................
Dead-Band Generator Control Register (DBCTL) Field Descriptions ...........................................
Dead-Band Generator Rising Edge Delay Register (DBRED) Field Descriptions .............................
Dead-Band Generator Falling Edge Delay Register (DBFED) Field Descriptions .............................
15-29. EPWMx Initialization for
List of Tables
1662
1662
1663
1665
1667
1672
1673
1675
1680
1681
1682
1683
1690
1690
1690
1693
1693
1696
1696
1699
1699
1700
1705
1705
1706
1709
1709
1710
1711
1711
1713
1714
1714
1715
1715
1716
1717
1718
1718
1719
1720
1721
1722
1722
1723
1724
1724

www.ti.com
15-78. Trip-Zone Submodule Registers ...................................................................................... 1725

15-79. Trip-Zone Submodule Select Register (TZSEL) Field Descriptions
.............................................
1725
15-80. Trip-Zone Control Register (TZCTL) Field Descriptions ........................................................... 1726

15-81. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions ............................................... 1726
15-82. Trip-Zone Flag Register (TZFLG) Field Descriptions .............................................................. 1727
............................................................
15-84. Trip-Zone Force Register (TZFRC) Field Descriptions ............................................................
15-85. Event-Trigger Submodule Registers .................................................................................
15-86. Event-Trigger Selection Register (ETSEL) Field Descriptions ...................................................
15-87. Event-Trigger Prescale Register (ETPS) Field Descriptions .....................................................
15-88. Event-Trigger Flag Register (ETFLG) Field Descriptions .........................................................
15-89. Event-Trigger Clear Register (ETCLR) Field Descriptions ........................................................
15-90. Event-Trigger Force Register (ETFRC) Field Descriptions ......................................................
15-91. PWM-Chopper Control Register (PCCTL) Bit Descriptions .......................................................
15-92. High-Resolution PWM Submodule Registers .......................................................................
15-93. Time-Base Phase High-Resolution Register (TBPHSHR) Field Descriptions ..................................
15-94. Counter-Compare A High-Resolution Register (CMPAHR) Field Descriptions ................................
15-95. HRPWM Control Register (HRCTL) Field Descriptions ...........................................................
15-96. ECAP Initialization for CAP Mode Absolute Time, Rising Edge Trigger ........................................
15-97. ECAP Initialization for CAP Mode Absolute Time, Rising and Falling Edge Trigger ..........................
15-98. ECAP Initialization for CAP Mode Delta Time, Rising Edge Trigger ............................................
15-99. ECAP Initialization for CAP Mode Delta Time, Rising and Falling Edge Triggers .............................
15-100. ECAP Initialization for APWM Mode ................................................................................
15-101. ECAP1 Initialization for Multichannel PWM Generation with Synchronization ................................
15-105. ECAP1 Initialization for Multichannel PWM Generation with Phase Control ..................................
15-108. Control and Status Register Set ....................................................................................
15-109. Time-Stamp Counter Register (TSCTR) Field Descriptions .....................................................
15-110. Counter Phase Control Register (CTRPHS) Field Descriptions ................................................
15-111. Capture 1 Register (CAP1) Field Descriptions ....................................................................
15-112. Capture 2 Register (CAP2) Field Descriptions ...................................................................
15-113. Capture 3 Register (CAP3) Field Descriptions ...................................................................
15-114. Capture 4 Register (CAP4) Field Descriptions ....................................................................
15-115. ECAP Control Register 1 (ECCTL1) Field Descriptions .........................................................
15-116. ECAP Control Register 2 (ECCTL2) Field Descriptions .........................................................
15-117. ECAP Interrupt Enable Register (ECEINT) Field Descriptions .................................................
15-118. ECAP Interrupt Flag Register (ECFLG) Field Descriptions......................................................
15-119. ECAP Interrupt Clear Register (ECCLR) Field Descriptions ...................................................
15-120. ECAP Interrupt Forcing Register (ECFRC) Field Descriptions..................................................
15-121. Revision ID Register (REVID) Field Descriptions .................................................................
15-122. Quadrature Decoder Truth Table ..................................................................................
15-123. eQEP Registers .......................................................................................................
15-124. eQEP Position Counter Register (QPOSCNT) Field Descriptions .............................................
15-125. eQEP Position Counter Initialization Register (QPOSINIT) Field Descriptions ..............................
15-126. eQEP Maximum Position Count Register (QPOSMAX) Field Descriptions ..................................
15-83. Trip-Zone Clear Register (TZCLR) Field Descriptions

List of Tables
1728
1728
1729
1729
1730
1731
1731
1732
1733
1733
1734
1734
1735
1749
1751
1753
1755
1757
1759
1759
1759
1759
1762
1762
1762
1763
1763
1764
1764
1765
1765
1766
1766
1768
1770
1771
1772
1773
1774
1781
1796
1797
1797
1797
109
www.ti.com
15-127. eQEP Position-Compare Register (QPOSCMP) Field Descriptions ........................................... 1798

15-128. eQEP Index Position Latch Register (QPOSILAT) Field Descriptions ........................................ 1798
15-129. eQEP Strobe Position Latch Register (QPOSSLAT) Field Descriptions ...................................... 1798
15-130. eQEP Position Counter Latch Register (QPOSLAT) Field Descriptions ...................................... 1799
15-131. eQEP Unit Timer Register (QUTMR) Field Descriptions ........................................................ 1799
15-132. eQEP Unit Period Register (QUPRD) Field Descriptions ........................................................ 1799
15-133. eQEP Watchdog Timer Register (QWDTMR) Field Descriptions .............................................. 1800
15-134. eQEP Watchdog Period Register (QWDPRD) Field Description .............................................. 1800
.............................................
15-136. eQEP Control Register (QEPCTL) Field Descriptions ...........................................................
15-137. eQEP Capture Control Register (QCAPCTL) Field Descriptions ...............................................
15-138. eQEP Position-Compare Control Register (QPOSCTL) Field Descriptions ..................................
15-139. eQEP Interrupt Enable Register (QEINT) Field Descriptions ...................................................
15-140. eQEP Interrupt Flag Register (QFLG) Field Descriptions .......................................................
15-141. eQEP Interrupt Clear Register (QCLR) Field Descriptions ......................................................
15-142. eQEP Interrupt Force Register (QFRC) Field Descriptions .....................................................
15-143. eQEP Status Register (QEPSTS) Field Descriptions ...........................................................
15-144. eQEP Capture Time Register (QCTMR) Field Descriptions.....................................................
15-145. eQEP Capture Period Register (QCPRD) Field Descriptions ...................................................
15-146. eQEP Capture Timer Latch Register (QCTMRLAT) Field Descriptions .......................................
15-147. eQEP Capture Period Latch Register (QCPRDLAT) Field Descriptions ......................................
15-148. eQEP Revision ID Register (REVID) Field Descriptions ........................................................
16-1. USB Connectivity Attributes ...........................................................................................
16-2. USB Clock Signals .....................................................................................................
16-3. USB Pin List .............................................................................................................
16-4. PERI_TXCSR Register Bit Configuration for Bulk IN Transactions .............................................
16-5. PERI_RXCSR Register Bit Configuration for Bulk OUT Transactions ..........................................
16-6. PERI_TXCSR Register Bit Configuration for Isochronous IN Transactions ....................................
16-7. PERI_RXCSR Register Bit Configuration for Isochronous OUT Transactions .................................
16-8. Isochronous OUT Error Handling: Peripheral Mode ...............................................................
16-9. Packet Descriptor Word 0 (PD0) Bit Field Descriptions ...........................................................
16-17. Buffer Descriptor Word 0 (BD0) Bit Field Descriptions ............................................................
16-25. Teardown Descriptor Word 0 Bit Field Descriptions ...............................................................
16-26. Teardown Descriptor Words 1 to 7 Bit Field Descriptions ........................................................
16-27. Queue-Endpoint Assignments ........................................................................................
15-135. eQEP Decoder Control Register (QDECCTL) Field Descriptions
110
List of Tables
1801
1802
1804
1805
1806
1807
1808
1810
1811
1812
1812
1812
1813
1813
1818
1819
1819
1835
1837
1839
1840
1841
1860
1861
1861
1861
1862
1862
1862
1862
1863
1863
1863
1863
1864
1864
1864
1864
1865
1865
1866

www.ti.com
16-28. 53 Bytes Test Packet Content ........................................................................................ 1883
..................................................................................................
...............................................................................
SYSCONFIG Register Field Descriptions ...........................................................................
IRQSTATRAW Register Field Descriptions .........................................................................
IRQSTAT Register Field Descriptions ...............................................................................
IRQENABLER Register Field Descriptions .........................................................................
IRQCLEARR Register Field Descriptions ...........................................................................
IRQDMATHOLDTX00 Register Field Descriptions ................................................................
IRQDMATHOLDRX00 Register Field Descriptions ................................................................
IRQDMAENABLE0 Register Field Descriptions ....................................................................
IRQDMAENABLE1 Register Field Descriptions ....................................................................
IRQFRAMETHOLDTX00 Register Field Descriptions .............................................................
IRQFRAMETHOLDRX00 Register Field Descriptions .............................................................
IRQFRAMEENABLE0 Register Field Descriptions ................................................................
IRQFRAMEENABLE1 Register Field Descriptions ................................................................
USB0_CTRL REGISTERS ............................................................................................
USB0REV Register Field Descriptions ..............................................................................
USB0CTRL Register Field Descriptions .............................................................................
USB0STAT Register Field Descriptions .............................................................................
USB0IRQMSTAT Register Field Descriptions ......................................................................
16-29. USBSS REGISTERS
1885
16-30. REVREG Register Field Descriptions
1887
16-31.
1888
16-32.
16-33.
16-34.
16-35.
16-36.
16-37.
16-38.
16-39.
16-40.
16-41.
16-42.
16-43.
16-44.
16-45.
16-46.
16-47.
16-48.
16-49.
16-50.
16-51.
16-52.
16-53.
16-54.
16-55.
16-56.
16-57.
16-58.
16-59.
16-60.
16-61.
16-62.
16-63.
16-64.
16-65.
16-66.
16-67.
16-68.
16-69.
16-70.
16-71.
16-72.
16-73.
16-74.
16-75.
16-76.

List of Tables
1889
1890
1891
1892
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926
1927
1928
1928
1930
1931
1933
1934
111
www.ti.com
16-77. USB0IRQSTATRAW0 Register Field Descriptions ................................................................ 1935
16-78. USB0IRQSTATRAW1 Register Field Descriptions ................................................................ 1937

16-79. USB0IRQSTAT0 Register Field Descriptions....................................................................... 1939
16-80. USB0IRQSTAT1 Register Field Descriptions....................................................................... 1941
16-81. USB0IRQENABLESET0 Register Field Descriptions.............................................................. 1943

16-82. USB0IRQENABLESET1 Register Field Descriptions.............................................................. 1945
.............................................................
.............................................................
16-85. USB0TXMODE Register Field Descriptions ........................................................................
16-86. USB0RXMODE Register Field Descriptions ........................................................................
16-87. USB0GENRNDISEP1 Register Field Descriptions ................................................................
16-96. USB0GENRNDISEP10 Register Field Descriptions ...............................................................
16-100. USB0GENRNDISEP14 Register Field Descriptions..............................................................
16-101. USB0GENRNDISEP15 Register Field Descriptions..............................................................
16-102. USB0AUTOREQ Register Field Descriptions .....................................................................
16-103. USB0SRPFIXTIME Register Field Descriptions ..................................................................
16-104. USB0_TDOWN Register Field Descriptions .......................................................................
16-105. USB0UTMI Register Field Descriptions ............................................................................
16-106. USB0MGCUTMILB Register Field Descriptions ..................................................................
16-107. USB0MODE Register Field Descriptions ..........................................................................
16-108. USB1_CTRL REGISTERS...........................................................................................
16-109. USB1REV Register Field Descriptions .............................................................................
16-110. USB1CTRL Register Field Descriptions ...........................................................................
16-111. USB1STAT Register Field Descriptions ...........................................................................
16-112. USB1IRQMSTAT Register Field Descriptions ....................................................................
16-113. USB1IRQSTATRAW0 Register Field Descriptions ...............................................................
16-114. USB1IRQSTATRAW1 Register Field Descriptions ...............................................................
16-115. USB1IRQSTAT0 Register Field Descriptions .....................................................................
16-116. USB1IRQSTAT1 Register Field Descriptions .....................................................................
16-117. USB1IRQENABLESET0 Register Field Descriptions ............................................................
16-118. USB1IRQENABLESET1 Register Field Descriptions ............................................................
16-119. USB1IRQENABLECLR0 Register Field Descriptions ............................................................
16-120. USB1IRQENABLECLR1 Register Field Descriptions ............................................................
16-121. USB1TXMODE Register Field Descriptions .......................................................................
16-122. USB1RXMODE Register Field Descriptions.......................................................................
112
16-83. USB0IRQENABLECLR0 Register Field Descriptions
1947
16-84. USB0IRQENABLECLR1 Register Field Descriptions
1949
List of Tables
1951
1953
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970
1971
1972
1974
1975
1976
1977
1978
1978
1980
1981
1983
1984
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2006
2007

www.ti.com
16-126. USB1GENRNDISEP4 Register Field Descriptions ............................................................... 2008

16-132. USB1GENRNDISEP10 Register Field Descriptions.............................................................. 2014

16-138. USB1AUTOREQ Register Field Descriptions ..................................................................... 2020
16-139. USB1SRPFIXTIME Register Field Descriptions .................................................................. 2022
16-140. USB1TDOWN Register Field Descriptions ........................................................................ 2023
16-141. USB1UTMI Register Field Descriptions ............................................................................ 2024

16-142. USB1UTMILB Register Field Descriptions
........................................................................
2025
16-143. USB1MODE Register Field Descriptions .......................................................................... 2026

16-144. USB2PHY REGISTERS.............................................................................................. 2026
16-145. Termination_control Register Field Descriptions.................................................................. 2028
............................................................................
DLLHS_2 Register Field Descriptions ..............................................................................
RX_TEST_2 Register Field Descriptions ..........................................................................
CHRG_DET Register Field Descriptions...........................................................................
PWR_CNTL Register Field Descriptions...........................................................................
UTMI_INTERFACE_CNTL_1 Register Field Descriptions ......................................................
UTMI_INTERFACE_CNTL_2 Register Field Descriptions ......................................................
BIST Register Field Descriptions ...................................................................................
BIST_CRC Register Field Descriptions ............................................................................
CDR_BIST2 Register Field Descriptions...........................................................................
GPIO Register Field Descriptions ...................................................................................
DLLHS Register Field Descriptions .................................................................................
USB2PHYCM_TRIM Register Field Descriptions.................................................................
USB2PHYCM_CONFIG Register Field Descriptions .............................................................
USBOTG Register Field Descriptions ..............................................................................
AD_INTERFACE_REG1 Register Field Descriptions ............................................................
ANA_CONFIG1 Register Field Descriptions ......................................................................
ANA_CONFIG2 Register Field Descriptions ......................................................................
CPPI_DMA REGISTERS ............................................................................................
DMAREVID Register Field Descriptions ...........................................................................
TDFDQ Register Field Descriptions ................................................................................
DMAEMU Register Field Descriptions .............................................................................
TXGCR0 Register Field Descriptions ..............................................................................
RXGCR0 Register Field Descriptions ..............................................................................
RXHPCRA0 Register Field Descriptions ...........................................................................
RXHPCRB0 Register Field Descriptions ...........................................................................
16-146. RX_CALIB Register Field Descriptions

16-147.
16-148.
16-149.
16-150.
16-151.
16-152.
16-153.
16-154.
16-155.
16-156.
16-157.
16-158.
16-159.
16-160.
16-161.
16-162.
16-163.
16-164.
16-165.
16-166.
16-167.
16-168.
16-169.
16-170.
16-171.
16-172.
16-173.
16-174.

List of Tables
2029
2031
2032
2033
2035
2036
2037
2039
2040
2041
2042
2043
2044
2045
2046
2047
2049
2051
2052
2053
2053
2057
2058
2059
2060
2061
2063
2064
2065
113
www.ti.com
16-175. RXGCR1 Register Field Descriptions .............................................................................. 2066
16-176. RXHPCRA1 Register Field Descriptions ........................................................................... 2068

16-177. RXHPCRB1 Register Field Descriptions ........................................................................... 2069
2070
16-179.
2071
16-180.
16-181.
16-182.
16-183.
16-184.
16-185.
16-186.
16-187.
16-188.
16-189.
16-190.
16-191.
16-192.
16-193.
16-194.
16-195.
16-196.
16-197.
16-198.
16-199.
16-200.
16-201.
16-202.
16-203.
16-204.
16-205.
16-206.
16-207.
16-208.
16-209.
16-210.
16-211.
16-212.
16-213.
16-214.
16-215.
16-216.
16-217.
16-218.
16-219.
16-220.
16-221.
16-222.
16-223.
114
..............................................................................
TXGCR10 Register Field Descriptions .............................................................................
RXGCR10 Register Field Descriptions .............................................................................
RXHPCRA10 Register Field Descriptions .........................................................................
RXHPCRB10 Register Field Descriptions .........................................................................
16-178. TXGCR2 Register Field Descriptions
List of Tables
2073
2074
2075
2076
2078
2079
2080
2081
2083
2084
2085
2086
2088
2089
2090
2091
2093
2094
2095
2096
2098
2099
2100
2101
2103
2104
2105
2106
2108
2109
2110
2111
2113
2114
2115
2116
2118
2119
2120
2121
2123
2124
2125
2126

www.ti.com
16-224. RXHPCRA13 Register Field Descriptions ......................................................................... 2128
16-225. RXHPCRB13 Register Field Descriptions ......................................................................... 2129

16-226. TXGCR14 Register Field Descriptions ............................................................................. 2130
16-227. RXGCR14 Register Field Descriptions ............................................................................. 2131












List of Tables
115
www.ti.com





16-290. CPPI_DMA_SCHEDULER REGISTERS .......................................................................... 2209
16-291. DMA_SCHED_CTRL Register Field Descriptions ................................................................ 2212

2213
16-293. WORD1 Register Field Descriptions
2214
16-294.
2215
16-295.
16-296.
16-297.
16-298.
16-299.
16-300.
16-301.
16-302.
16-303.
16-304.
16-305.
16-306.
16-307.
16-308.
16-309.
16-310.
16-311.
16-312.
16-313.
16-314.
16-315.
16-316.
16-317.
16-318.
16-319.
16-320.
16-321.
116
...............................................................................
...............................................................................
WORD2 Register Field Descriptions ...............................................................................
WORD10 Register Field Descriptions ..............................................................................
16-292. WORD0 Register Field Descriptions
List of Tables
2216
2217
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242

www.ti.com
16-322. WORD32 Register Field Descriptions .............................................................................. 2243

16-354. QUEUE_MGR REGISTERS ......................................................................................... 2274
16-355. QMGRREVID Register Field Descriptions ......................................................................... 2299
16-356. QMGRRST Register Field Descriptions ............................................................................ 2300

16-357. FDBSC0 Register Field Descriptions ............................................................................... 2301
16-365. LRAM0BASE Register Field Descriptions ......................................................................... 2309
..........................................................................
2310
16-368. PEND0 Register Field Descriptions
2313
16-370.
................................................................................
................................................................................
PEND2 Register Field Descriptions ................................................................................
2312
2314
16-366. LRAM0SIZE Register Field Descriptions
16-367. LRAM1BASE Register Field Descriptions ......................................................................... 2311

List of Tables
117
www.ti.com
2315
16-372.
2316
16-373.
16-374.
16-375.
16-376.
16-377.
16-378.
16-379.
16-380.
16-381.
16-382.
16-383.
16-384.
16-385.
16-386.
16-387.
16-388.
16-389.
16-390.
16-391.
16-392.
16-393.
16-394.
16-395.
16-396.
16-397.
16-398.
16-399.
16-400.
16-401.
16-402.
16-403.
16-404.
16-405.
16-406.
16-407.
16-408.
16-409.
16-410.
16-411.
16-412.
16-413.
16-414.
16-415.
16-416.
16-417.
16-418.
16-419.
118
................................................................................
PEND4 Register Field Descriptions ................................................................................
QMEMRBASE0 Register Field Descriptions ......................................................................
QMEMCTRL0 Register Field Descriptions ........................................................................
QUEUE_0_A Register Field Descriptions..........................................................................
QUEUE_0_B Register Field Descriptions..........................................................................
QUEUE_0_C Register Field Descriptions .........................................................................
QUEUE_0_D Register Field Descriptions .........................................................................
List of Tables
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343
2344
2345
2346
2347
2348
2349
2350
2351
2352
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362
2363

www.ti.com
.........................................................................
QUEUE_10_A Register Field Descriptions ........................................................................
QUEUE_10_B Register Field Descriptions ........................................................................
QUEUE_10_C Register Field Descriptions ........................................................................
QUEUE_10_D Register Field Descriptions ........................................................................
16-420. QUEUE_7_D Register Field Descriptions
2364
16-421.
2365
16-422.
16-423.
16-424.
16-425.
16-426.
16-427.
16-428.
16-429.
16-430.
16-431.
16-432.
16-433.
16-434.
16-435.
16-436.
16-437.
16-438.
16-439.
16-440.
16-441.
16-442.
16-443.
16-444.
16-445.
16-446.
16-447.
16-448.
16-449.
16-450.
16-451.
16-452.
16-453.
16-454.
16-455.
16-456.
16-457.
16-458.
16-459.
16-460.
16-461.
16-462.
16-463.
16-464.
16-465.
16-466.
16-467.
16-468.

List of Tables
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404
2405
2406
2407
2408
2409
2410
2411
2412
119
www.ti.com
16-469. QUEUE_20_A Register Field Descriptions ........................................................................ 2413

16-470. QUEUE_20_B Register Field Descriptions ........................................................................ 2414
16-471. QUEUE_20_C Register Field Descriptions ........................................................................ 2415
16-472. QUEUE_20_D Register Field Descriptions ........................................................................ 2416
120
List of Tables

www.ti.com

List of Tables
121
www.ti.com

122
List of Tables

www.ti.com

List of Tables
123
www.ti.com

124
List of Tables

www.ti.com

List of Tables
125
www.ti.com

16-789. QUEUE_100_A Register Field Descriptions....................................................................... 2733

16-790. QUEUE_100_B Register Field Descriptions....................................................................... 2734
......................................................................
QUEUE_100_D Register Field Descriptions ......................................................................
QUEUE_101_A Register Field Descriptions.......................................................................
QUEUE_101_B Register Field Descriptions.......................................................................
QUEUE_101_C Register Field Descriptions ......................................................................
16-791. QUEUE_100_C Register Field Descriptions

16-792.
16-793.
16-794.
16-795.
16-796.
16-797.
16-798.
16-799.
16-800.
16-801.
16-802.
16-803.
16-804.
16-805.
16-806.
16-807.
16-808.
16-809.
16-810.
16-811.
126
List of Tables
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755

www.ti.com
......................................................................
2756
16-813.
2757
16-814.
16-815.
16-816.
16-817.
16-818.
16-819.
16-820.
16-821.
16-822.
16-823.
16-824.
16-825.
16-826.
16-827.
16-828.
16-829.
16-830.
16-831.
16-832.
16-833.
16-834.
16-835.
16-836.
16-837.
16-838.
16-839.
16-840.
16-841.
16-842.
16-843.
16-844.
16-845.
16-846.
16-847.
16-848.
16-849.
16-850.
16-851.
16-852.
16-853.
16-854.
16-855.
16-856.
16-857.
16-858.
16-859.
16-860.

List of Tables
2758
2759
2760
2761
2762
2763
2764
2765
2766
2767
2768
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
127
www.ti.com
16-861. QUEUE_118_A Register Field Descriptions....................................................................... 2805

2807
2808
16-865.
2809
16-866.
16-867.
16-868.
16-869.
16-870.
16-871.
16-872.
16-873.
16-874.
16-875.
16-876.
16-877.
16-878.
16-879.
16-880.
16-881.
16-882.
16-883.
16-884.
16-885.
16-886.
16-887.
16-888.
16-889.
16-890.
16-891.
16-892.
16-893.
16-894.
16-895.
16-896.
16-897.
16-898.
16-899.
16-900.
16-901.
16-902.
16-903.
16-904.
16-905.
16-906.
16-907.
16-908.
16-909.
128
......................................................................
......................................................................
List of Tables
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830
2831
2832
2833
2834
2835
2836
2837
2838
2839
2840
2841
2842
2843
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853

www.ti.com
......................................................................
......................................................................
2855
2856
16-913.
2857
16-914.
16-915.
16-916.
16-917.
16-918.
16-919.
16-920.
16-921.
16-922.
16-923.
16-924.
16-925.
16-926.
16-927.
16-928.
16-929.
16-930.
16-931.
16-932.
16-933.
16-934.
16-935.
16-936.
16-937.
16-938.
16-939.
16-940.
16-941.
16-942.
16-943.
16-944.
16-945.
16-946.
16-947.
16-948.
16-949.
16-950.
16-951.
16-952.
16-953.
16-954.
16-955.
16-956.
16-957.
16-958.

List of Tables
2858
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874
2875
2876
2877
2878
2879
2880
2881
2882
2883
2884
2885
2886
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
129
www.ti.com
......................................................................
16-960. QUEUE_142_D Register Field Descriptions ......................................................................
16-961. QUEUE_143_A Register Field Descriptions.......................................................................
16-962. QUEUE_143_B Register Field Descriptions.......................................................................
16-963. QUEUE_143_C Register Field Descriptions ......................................................................
16-1000. QUEUE_152_D Register Field Descriptions .....................................................................
16-1001. QUEUE_153_A Register Field Descriptions .....................................................................
16-1002. QUEUE_153_B Register Field Descriptions .....................................................................
16-1003. QUEUE_153_C Register Field Descriptions .....................................................................
16-1004. QUEUE_153_D Register Field Descriptions .....................................................................
16-1005. QUEUE_154_A Register Field Descriptions .....................................................................
16-1006. QUEUE_154_B Register Field Descriptions .....................................................................
16-1007. QUEUE_154_C Register Field Descriptions .....................................................................
130
List of Tables
2903
2904
2905
2906
2907
2908
2909
2910
2911
2912
2913
2914
2915
2916
2917
2918
2919
2920
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939
2940
2941
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951

www.ti.com
16-1008. QUEUE_154_D Register Field Descriptions ..................................................................... 2952

16-1009. QUEUE_155_A Register Field Descriptions ..................................................................... 2953
16-1010. QUEUE_155_B Register Field Descriptions ..................................................................... 2954
16-1011. QUEUE_155_C Register Field Descriptions ..................................................................... 2955
16-1012. QUEUE_155_D Register Field Descriptions ..................................................................... 2956
16-1013. QUEUE_0_STATUS_A Register Field Descriptions ............................................................ 2957
16-1014. QUEUE_0_STATUS_B Register Field Descriptions ............................................................ 2958
16-1015. QUEUE_0_STATUS_C Register Field Descriptions ............................................................ 2959









..........................................................
QUEUE_10_STATUS_B Register Field Descriptions ..........................................................
QUEUE_10_STATUS_C Register Field Descriptions ..........................................................
QUEUE_11_STATUS_A Register Field Descriptions ..........................................................
16-1043. QUEUE_10_STATUS_A Register Field Descriptions
2987
16-1044.
2988
16-1045.
16-1046.
16-1047.
16-1048.
16-1049.
16-1050.
16-1051.
16-1052.
16-1053.
16-1054.
16-1055.
16-1056.

List of Tables
2989
2990
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
131
www.ti.com
16-1057. QUEUE_14_STATUS_C Register Field Descriptions .......................................................... 3001

3002
16-1059. QUEUE_15_STATUS_B Register Field Descriptions
3003
16-1060.
3004
16-1061.
16-1062.
16-1063.
16-1064.
16-1065.
16-1066.
16-1067.
16-1068.
16-1069.
16-1070.
16-1071.
16-1072.
16-1073.
16-1074.
16-1075.
16-1076.
16-1077.
16-1078.
16-1079.
16-1080.
16-1081.
16-1082.
16-1083.
16-1084.
16-1085.
16-1086.
16-1087.
16-1088.
16-1089.
16-1090.
16-1091.
16-1092.
16-1093.
16-1094.
16-1095.
16-1096.
16-1097.
16-1098.
16-1099.
16-1100.
16-1101.
16-1102.
16-1103.
16-1104.
16-1105.
132
..........................................................
..........................................................
List of Tables
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049

www.ti.com
..........................................................
3050
16-1107.
3051
16-1108.
16-1109.
16-1110.
16-1111.
16-1112.
16-1113.
16-1114.
16-1115.
16-1116.
16-1117.
16-1118.
16-1119.
16-1120.
16-1121.
16-1122.
16-1123.
16-1124.
16-1125.
16-1126.
16-1127.
16-1128.
16-1129.
16-1130.
16-1131.
16-1132.
16-1133.
16-1134.
16-1135.
16-1136.
16-1137.
16-1138.
16-1139.
16-1140.
16-1141.
16-1142.
16-1143.
16-1144.
16-1145.
16-1146.
16-1147.
16-1148.
16-1149.
16-1150.
16-1151.
16-1152.
16-1153.
16-1154.

List of Tables
3052
3053
3054
3055
3056
3057
3058
3059
3060
3061
3062
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096
3097
3098
133
www.ti.com
3099
16-1156.
3100
16-1157.
16-1158.
16-1159.
16-1160.
16-1161.
16-1162.
16-1163.
16-1164.
16-1165.
16-1166.
16-1167.
16-1168.
16-1169.
16-1170.
16-1171.
16-1172.
16-1173.
16-1174.
16-1175.
16-1176.
16-1177.
16-1178.
16-1179.
16-1180.
16-1181.
16-1182.
16-1183.
16-1184.
16-1185.
16-1186.
16-1187.
16-1188.
16-1189.
16-1190.
16-1191.
16-1192.
16-1193.
16-1194.
16-1195.
16-1196.
16-1197.
16-1198.
16-1199.
16-1200.
16-1201.
16-1202.
16-1203.
134
..........................................................
List of Tables
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147

www.ti.com
16-1204. QUEUE_63_STATUS_C Register Field Descriptions .......................................................... 3148
..........................................................
..........................................................
3149
3150
16-1207.
3151
16-1208.
16-1209.
16-1210.
16-1211.
16-1212.
16-1213.
16-1214.
16-1215.
16-1216.
16-1217.
16-1218.
16-1219.
16-1220.
16-1221.
16-1222.
16-1223.
16-1224.
16-1225.
16-1226.
16-1227.
16-1228.
16-1229.
16-1230.
16-1231.
16-1232.
16-1233.
16-1234.
16-1235.
16-1236.
16-1237.
16-1238.
16-1239.
16-1240.
16-1241.
16-1242.
16-1243.
16-1244.
16-1245.
16-1246.
16-1247.
16-1248.
16-1249.
16-1250.
16-1251.
16-1252.

List of Tables
3152
3153
3154
3155
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165
3166
3167
3168
3169
3170
3171
3172
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196
135
www.ti.com
3197
16-1254.
3198
16-1255.
16-1256.
16-1257.
16-1258.
16-1259.
16-1260.
16-1261.
16-1262.
16-1263.
16-1264.
16-1265.
16-1266.
16-1267.
16-1268.
16-1269.
16-1270.
16-1271.
16-1272.
16-1273.
16-1274.
16-1275.
16-1276.
16-1277.
16-1278.
16-1279.
16-1280.
16-1281.
16-1282.
16-1283.
16-1284.
16-1285.
16-1286.
16-1287.
16-1288.
16-1289.
16-1290.
16-1291.
16-1292.
16-1293.
16-1294.
16-1295.
16-1296.
16-1297.
16-1298.
16-1299.
16-1300.
16-1301.
136
..........................................................
List of Tables
3199
3200
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229
3230
3231
3232
3233
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245

www.ti.com
..........................................................
QUEUE_100_STATUS_A Register Field Descriptions .........................................................
QUEUE_100_STATUS_B Register Field Descriptions .........................................................
QUEUE_100_STATUS_C Register Field Descriptions .........................................................
3246
16-1303.
3247
16-1304.
16-1305.
16-1306.
16-1307.
16-1308.
16-1309.
16-1310.
16-1311.
16-1312.
16-1313.
16-1314.
16-1315.
16-1316.
16-1317.
16-1318.
16-1319.
16-1320.
16-1321.
16-1322.
16-1323.
16-1324.
16-1325.
16-1326.
16-1327.
16-1328.
16-1329.
16-1330.
16-1331.
16-1332.
16-1333.
16-1334.
16-1335.
16-1336.
16-1337.
16-1338.
16-1339.
16-1340.
16-1341.
16-1342.
16-1343.
16-1344.
16-1345.
16-1346.
16-1347.
16-1348.
16-1349.
16-1350.

List of Tables
3248
3249
3250
3251
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282
3283
3284
3285
3286
3287
3288
3289
3290
3291
3292
3293
3294
137
www.ti.com
16-1351. QUEUE_112_STATUS_C Register Field Descriptions ......................................................... 3295
16-1352. QUEUE_113_STATUS_A Register Field Descriptions ......................................................... 3296
16-1353. QUEUE_113_STATUS_B Register Field Descriptions ......................................................... 3297
















138
List of Tables

www.ti.com

















List of Tables
139
www.ti.com











17-1.
Mailbox Connectivity Attributes ....................................................................................... 3427
17-2.
Mailbox Clock Signals
17-3.
17-4.
17-5.
17-6.
17-7.
17-8.
17-9.
17-10.
17-11.
17-12.
17-13.
17-14.
17-15.
17-16.
17-17.
140
.................................................................................................
Mailbox Implementation ...............................................................................................
Local Power Management Features .................................................................................
Interrupt Events .........................................................................................................
Global Initialization of Surrounding Modules for System Mailbox ................................................
Mailbox Global Initialization ...........................................................................................
Sending a Message (Polling Method) ...............................................................................
Sending a Message (Interrupt Method)..............................................................................
Receiving a Message (Polling Method)..............................................................................
Receiving a Message (Interrupt Method)............................................................................
Events Servicing in Sending Mode ...................................................................................
Events Servicing in Receiving Mode .................................................................................
MAILBOX REGISTERS................................................................................................
REVISION Register Field Descriptions ..............................................................................
MESSAGE_0 Register Field Descriptions ..........................................................................
List of Tables
3428
3428
3429
3430
3432
3433
3433
3433
3434
3434
3434
3434
3435
3438
3439
3440

www.ti.com
..........................................................................
FIFOSTATUS_0 Register Field Descriptions .......................................................................
MSGSTATUS_0 Register Field Descriptions .......................................................................
IRQSTATUS_RAW_0 Register Field Descriptions.................................................................
IRQSTATUS_CLR_0 Register Field Descriptions .................................................................
IRQENABLE_SET_0 Register Field Descriptions ..................................................................
IRQENABLE_CLR_0 Register Field Descriptions .................................................................
SPINLOCK REGISTERS ..............................................................................................
REV Register Field Descriptions .....................................................................................
SYSTATUS Register Field Descriptions.............................................................................
LOCK_REG_0 Register Field Descriptions .........................................................................
17-18. MESSAGE_1 Register Field Descriptions
3441
17-19.
3442
17-20.
17-21.
17-22.
17-23.
17-24.
17-25.
17-26.
17-27.
17-28.
17-29.
17-30.
17-31.
17-32.
17-33.
17-34.
17-35.
17-36.
17-37.
17-38.
17-39.
17-40.
17-41.
17-42.
17-43.
17-44.
17-45.
17-46.
17-47.
17-48.
17-49.
17-50.
17-51.
17-52.
17-53.
17-54.
17-55.
17-56.
17-57.
17-58.
17-59.
17-60.
17-61.
17-62.
17-63.
17-64.
17-65.
17-66.

List of Tables
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464
3466
3468
3470
3472
3474
3476
3478
3480
3482
3484
3486
3488
3490
3492
3494
3496
3499
3500
3501
3502
3503
3504
3505
3506
3507
141
www.ti.com
17-67. LOCK_REG_6 Register Field Descriptions ......................................................................... 3508

17-71. LOCK_REG_10 Register Field Descriptions ........................................................................ 3512
18-1.
18-2.
18-3.
18-4.
MMCHS Connectivity Attributes ...................................................................................... 3537

MMCHS Clock Signals................................................................................................. 3538
MMCHS Pin List ........................................................................................................ 3538
18-5.
DAT Line Direction for Data Transfer Modes ....................................................................... 3538
18-6.
ADPDATDIROQ and ADPDATDIRLS Signal States
..............................................................
3539
............................................................................................
Local Power Management Features .................................................................................
Clock Activity Settings .................................................................................................
Events ....................................................................................................................
Memory Size, BLEN, and Buffer Relationship ......................................................................
MMC, SD, SDIO Responses in the SD_RSPxx Registers ........................................................
CC and TC Values Upon Error Detected ............................................................................
MMC/SD/SDIO Controller Transfer Stop Command Summary ..................................................
MMC/SD/SDIO Hardware Status Features .........................................................................
Global Init for Surrounding Modules ................................................................................
MMC/SD/SDIO Controller Wake-Up Configuration ................................................................
MMC/SD/SDIO Registers .............................................................................................
System Configuration Register (SD_SYSCONFIG) Field Descriptions .........................................
System Status Register (SD_SYSSTATUS) Field Descriptions .................................................
Card Status Response Error (SD_CSRE) Field Descriptions ....................................................
System Test Register (SD_SYSTEST) Field Descriptions ........................................................
3545
18-7.
MMC/SD/SDIO Controller Pins and Descriptions .................................................................. 3542
18-8.
Response Type Summary
18-9.
18-10.
18-11.
18-12.
18-13.
18-14.
18-15.
18-16.
18-17.
18-18.
18-19.
18-20.
18-21.
18-22.
18-23.
142
Unsupported MMCHS Features ...................................................................................... 3535
List of Tables
3550
3550
3551
3558
3559
3560
3567
3572
3573
3574
3578
3579
3581
3581
3582

www.ti.com
18-24. Configuration Register (SD_CON) Field Descriptions ............................................................. 3585

18-25. Power Counter Register (SD_PWCNT) Field Descriptions ....................................................... 3588
18-26. Card Status Response Error (SD_SDMASA) Field Descriptions
................................................
3588
18-27. Transfer Length Configuration Register (SD_BLK) Field Descriptions .......................................... 3589
18-28. Command Argument Register (SD_ARG) Field Descriptions .................................................... 3590
18-29. Command and Transfer Mode Register (SD_CMD) Field Descriptions ......................................... 3591
18-30. Command Response[31:0] Register (SD_RSP10) Field Descriptions .......................................... 3594
18-31. Command Response[63:32] Register (SD_RSP32) Field Descriptions ......................................... 3594
18-32. Command Response[95:64] Register (SD_RSP54) Field Descriptions ......................................... 3595
18-33. Command Response[127:96] Register (SD_RSP76) Field Descriptions ....................................... 3595
18-34. Data Register (SD_DATA) Field Descriptions ...................................................................... 3596

18-35. Present State Register (SD_PSTATE) Field Descriptions ........................................................ 3597
18-36. Control Register (SD_HCTL) Field Descriptions ................................................................... 3600
.................................................
Interrupt Status Register (SD_STAT) Field Descriptions..........................................................
Interrupt SD Enable Register (SD_IE) Field Descriptions.........................................................
Interrupt Signal Enable Register (SD_ISE) Field Descriptions ...................................................
Auto CMD12 Error Status Register (SD_AC12) Field Descriptions .............................................
Capabilities Register (SD_CAPA) Field Descriptions ..............................................................
Maximum Current Capabilities Register (SD_CUR_CAPA) Field Descriptions ................................
Force Event Register (SD_FE) Field Descriptions .................................................................
ADMA Error Status Register (SD_ADMAES) Field Descriptions ................................................
ADMA System Address Low Bits (SD_ADMASAL) Field Descriptions..........................................
ADMA System Address High Bits Register (SD_ADMASAH) Field Descriptions ..............................
Versions Register (SD_REV) Field Descriptions ...................................................................
Unsupported UART Features .........................................................................................
UART0 Connectivity Attributes .......................................................................................
UART15 Connectivity Attributes ....................................................................................
UART0 Clock Signals ..................................................................................................
UART15 Clock Signals ...............................................................................................
UART Mode Baud and Error Rates ..................................................................................
IrDA Mode Baud and Error Rates ....................................................................................
UART Pin List ...........................................................................................................
UART Muxing Control ..................................................................................................
Local Power-Management Features .................................................................................
UART Mode Interrupts .................................................................................................
IrDA Mode Interrupts ...................................................................................................
CIR Mode Interrupts....................................................................................................
TX FIFO Trigger Level Setting Summary ...........................................................................
RX FIFO Trigger Level Setting Summary ...........................................................................
UART/IrDA/CIR Register Access Mode Programming (Using UART_LCR) ....................................
Subconfiguration Mode A Summary .................................................................................
Subconfiguration Mode B Summary .................................................................................
Suboperational Mode Summary ......................................................................................
UART/IrDA/CIR Register Access Mode Overview .................................................................
UART Mode Selection .................................................................................................
UART Mode Register Overview .....................................................................................
IrDA Mode Register Overview .......................................................................................
CIR Mode Register Overview ........................................................................................
18-37. SD System Control Register (SD_SYSCTL) Field Descriptions
3603
18-38.
3605
18-39.
18-40.
18-41.
18-42.
18-43.
18-44.
18-45.
18-46.
18-47.
18-48.
19-1.
19-2.
19-3.
19-4.
19-5.
19-6.
19-7.
19-8.
19-9.
19-10.
19-11.
19-12.
19-13.
19-14.
19-15.
19-16.
19-17.
19-18.
19-19.
19-20.
19-21.
19-22.
19-23.
19-24.

List of Tables
3610
3613
3616
3617
3619
3620
3622
3623
3623
3624
3627
3628
3629
3629
3629
3630
3630
3631
3631
3635
3635
3636
3637
3639
3639
3647
3647
3647
3647
3647
3649
3649
3650
3651
143
www.ti.com
19-25. UART Baud Rate Settings (48-MHz Clock) ......................................................................... 3654
19-26. UART Parity Bit Encoding ............................................................................................. 3654

19-27. UART_EFR[3:0] Software Flow Control Options ................................................................... 3656
..............................................................................................
UART Registers ........................................................................................................
Receiver Holding Register (RHR) Field Descriptions ..............................................................
Transmit Holding Register (THR) Field Descriptions ..............................................................
UART Interrupt Enable Register (IER) Field Descriptions ........................................................
IrDA Interrupt Enable Register (IER) Field Descriptions ..........................................................
CIR Interrupt Enable Register (IER) Field Descriptions ...........................................................
UART Interrupt Identification Register (IIR) Field Descriptions...................................................
IrDA Interrupt Identification Register (IIR) Field Descriptions.....................................................
CIR Interrupt Identification Register (IIR) Field Descriptions .....................................................
FIFO Control Register (FCR) Field Descriptions ...................................................................
Line Control Register (LCR) Field Descriptions ....................................................................
Modem Control Register (MCR) Field Descriptions................................................................
UART Line Status Register (LSR) Field Descriptions .............................................................
IrDA Line Status Register (LSR) Field Descriptions ...............................................................
CIR Line Status Register (LSR) Field Descriptions ................................................................
Modem Status Register (MSR) Field Descriptions .................................................................
Transmission Control Register (TCR) Field Descriptions .........................................................
Scratchpad Register (SPR) Field Descriptions .....................................................................
Trigger Level Register (TLR) Field Descriptions ...................................................................
RX FIFO Trigger Level Setting Summary ..........................................................................
TX FIFO Trigger Level Setting Summary ...........................................................................
Mode Definition Register 1 (MDR1) Field Descriptions ...........................................................
Mode Definition Register 2 (MDR2) Field Descriptions ...........................................................
Status FIFO Line Status Register (SFLSR) Field Descriptions...................................................
RESUME Register Field Descriptions ...............................................................................
Status FIFO Register Low (SFREGL) Field Descriptions .........................................................
Status FIFO Register High (SFREGH) Field Descriptions ........................................................
BOF Control Register (BLR) Field Descriptions ....................................................................
Auxiliary Control Register (ACREG) Field Descriptions ...........................................................
Supplementary Control Register (SCR) Field Descriptions .......................................................
Supplementary Status Register (SSR) Field Descriptions ........................................................
BOF Length Register (EBLR) Field Descriptions...................................................................
Module Version Register (MVR) Field Descriptions ...............................................................
System Configuration Register (SYSC) Field Descriptions .......................................................
System Status Register (SYSS) Field Descriptions................................................................
Wake-Up Enable Register (WER) Field Descriptions .............................................................
Carrier Frequency Prescaler Register (CFPS) Field Descriptions ...............................................
Divisor Latches Low Register (DLL) Field Descriptions ...........................................................
Divisor Latches High Register (DLH) Field Descriptions ..........................................................
Enhanced Feature Register (EFR) Field Descriptions.............................................................
EFR[3:0] Software Flow Control Options ...........................................................................
XON1/ADDR1 Register Field Descriptions..........................................................................
XON2/ADDR2 Register Field Descriptions..........................................................................
XOFF1 Register Field Descriptions ..................................................................................
XOFF2 Register Field Descriptions ..................................................................................
19-28. IrDA Baud Rate Settings

19-29.
19-30.
19-31.
19-32.
19-33.
19-34.
19-35.
19-36.
19-37.
19-38.
19-39.
19-40.
19-41.
19-42.
19-43.
19-44.
19-45.
19-46.
19-47.
19-48.
19-49.
19-50.
19-51.
19-52.
19-53.
19-54.
19-55.
19-56.
19-57.
19-58.
19-59.
19-60.
19-61.
19-62.
19-63.
19-64.
19-65.
19-66.
19-67.
19-68.
19-69.
19-70.
19-71.
19-72.
19-73.
144
List of Tables
3665
3684
3686
3686
3687
3688
3689
3690
3691
3692
3693
3694
3695
3696
3697
3698
3699
3700
3700
3701
3701
3701
3702
3703
3704
3704
3705
3705
3706
3707
3708
3709
3710
3711
3712
3712
3713
3714
3715
3715
3716
3717
3717
3717
3718
3718

www.ti.com
19-74. Transmit Frame Length Low Register (TXFLL) Field Descriptions .............................................. 3719
19-75. Transmit Frame Length High Register (TXFLH) Field Descriptions ............................................. 3719
19-76. Received Frame Length Low Register (RXFLL) Field Descriptions ............................................. 3720
19-77. Received Frame Length High Register (RXFLH) Field Descriptions ............................................ 3720
19-78. UART Autobauding Status Register (UASR) Field Descriptions ................................................. 3721
19-79. RXFIFO_LVL Register Field Descriptions ........................................................................... 3722

19-80. TXFIFO_LVL Register Field Descriptions ........................................................................... 3723
19-81. IER2 Register Field Descriptions ..................................................................................... 3724
19-82. ISR2 Register Field Descriptions ..................................................................................... 3725
19-83. FREQ_SEL Register Field Descriptions ............................................................................. 3726
19-84. Mode Definition Register 3 (MDR3) Register Field Descriptions................................................. 3727
20-1.
Timer Resolution and Maximum Range ............................................................................. 3729
20-2.
Timer[0] Connectivity Attributes
3731
20-3.
Timer[27] Connectivity Attributes
3731
20-4.
20-5.
20-6.
20-7.
20-8.
20-9.
20-10.
20-11.
20-12.
20-13.
20-14.
20-15.
20-16.
20-17.
20-18.
20-19.
20-20.
20-21.
20-22.
20-23.
20-24.
20-25.
20-26.
20-27.
20-28.
20-29.
20-30.
20-31.
20-32.
20-33.
20-34.
20-35.
20-36.
20-37.
20-38.
......................................................................................
...................................................................................
Timer Clock Signals ....................................................................................................
Timer Pin List ...........................................................................................................
Prescaler Functionality .................................................................................................
Prescaler Clock Ratios Value .........................................................................................
Value and Corresponding Interrupt Period ..........................................................................
OCP Error Reporting ...................................................................................................
TIMER REGISTERS ...................................................................................................
TIDR Register Field Descriptions.....................................................................................
TIOCP_CFG Register Field Descriptions ...........................................................................
IRQSTATUS_RAW Register Field Descriptions....................................................................
IRQSTATUS Register Field Descriptions ...........................................................................
IRQENABLE_SET Register Field Descriptions .....................................................................
IRQENABLE_CLR Register Field Descriptions ....................................................................
IRQWAKEEN Register Field Descriptions ..........................................................................
TCLR Register Field Descriptions ....................................................................................
TCRR Register Field Descriptions ...................................................................................
TLDR Register Field Descriptions ....................................................................................
TTGR Register Field Descriptions ...................................................................................
TWPS Register Field Descriptions ...................................................................................
TMAR Register Field Descriptions ...................................................................................
TCAR1 Register Field Descriptions ..................................................................................
TSICR Register Field Descriptions ...................................................................................
Timer1 Connectivity Attributes ........................................................................................
Timer Clock Signals ....................................................................................................
Value Loaded in TCRR to Generate 1ms Tick .....................................................................
Prescaler/Timer Reload Values Versus Contexts ..................................................................
SmartIdle - Clock Activity Field Configuration ......................................................................
Prescaler Clock Ratios Value .........................................................................................
Value and Corresponding Interrupt Period ..........................................................................
DMTIMER_1MS REGISTERS ........................................................................................
TIDR Register Field Descriptions.....................................................................................
TIOCP_CFG Register Field Descriptions ...........................................................................
TISTAT Register Field Descriptions..................................................................................
TISR Register Field Descriptions .....................................................................................

List of Tables
3732
3732
3735
3738
3738
3739
3742
3743
3744
3745
3746
3747
3748
3749
3750
3752
3753
3754
3755
3756
3757
3758
3759
3762
3763
3765
3768
3770
3771
3772
3772
3774
3775
3776
3777
145
www.ti.com
20-39. TIER Register Field Descriptions ..................................................................................... 3778
20-40. TWER Register Field Descriptions ................................................................................... 3779
20-41. TCLR Register Field Descriptions .................................................................................... 3780

20-42. TCRR Register Field Descriptions ................................................................................... 3782
20-43. TLDR Register Field Descriptions .................................................................................... 3783

3784
20-45.
3785
20-46.
20-47.
20-48.
20-49.
20-50.
20-51.
20-52.
20-53.
20-54.
20-55.
20-56.
20-57.
20-58.
20-59.
20-60.
20-61.
20-62.
20-63.
20-64.
20-65.
20-66.
20-67.
20-68.
20-69.
20-70.
20-71.
20-72.
20-73.
20-74.
20-75.
20-76.
20-77.
20-78.
20-79.
20-80.
20-81.
20-82.
20-83.
20-84.
20-85.
20-86.
20-87.
146
...................................................................................
TWPS Register Field Descriptions ...................................................................................
TMAR Register Field Descriptions ...................................................................................
TSICR Register Field Descriptions ...................................................................................
TPIR Register Field Descriptions .....................................................................................
TNIR Register Field Descriptions.....................................................................................
TCVR Register Field Descriptions ...................................................................................
TOCR Register Field Descriptions ...................................................................................
TOWR Register Field Descriptions...................................................................................
RTC Module Connectivity Attributes .................................................................................
RTC Clock Signals .....................................................................................................
RTC Pin List .............................................................................................................
RTC Signals .............................................................................................................
Interrupt Trigger Events ...............................................................................................
RTC Register Names and Values ....................................................................................
pmic_pwr_enable Description.........................................................................................
RTC REGISTERS ......................................................................................................
SECONDS_REG Register Field Descriptions ......................................................................
MINUTES_REG Register Field Descriptions .......................................................................
HOURS_REG Register Field Descriptions ..........................................................................
DAYS_REG Register Field Descriptions ............................................................................
MONTHS_REG Register Field Descriptions ........................................................................
YEARS_REG Register Field Descriptions ..........................................................................
WEEKS_REG Register Field Descriptions ..........................................................................
ALARM_SECONDS_REG Register Field Descriptions ...........................................................
ALARM_MINUTES_REG Register Field Descriptions.............................................................
ALARM_HOURS_REG Register Field Descriptions ...............................................................
ALARM_DAYS_REG Register Field Descriptions .................................................................
ALARM_MONTHS_REG Register Field Descriptions .............................................................
ALARM_YEARS_REG Register Field Descriptions................................................................
RTC_CTRL_REG Register Field Descriptions .....................................................................
RTC_STATUS_REG Register Field Descriptions ..................................................................
RTC_INTERRUPTS_REG Register Field Descriptions ...........................................................
RTC_COMP_LSB_REG Register Field Descriptions ..............................................................
RTC_COMP_MSB_REG Register Field Descriptions .............................................................
RTC_OSC_REG Register Field Descriptions.......................................................................
RTC_SCRATCH0_REG Register Field Descriptions ..............................................................
KICK0R Register Field Descriptions .................................................................................
KICK1R Register Field Descriptions .................................................................................
RTC_REVISION Register Field Descriptions .......................................................................
20-44. TTGR Register Field Descriptions
List of Tables
3787
3788
3789
3790
3791
3792
3793
3794
3795
3797
3797
3797
3799
3800
3802
3805
3806
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818
3819
3820
3821
3823
3824
3825
3826
3827
3828
3829
3830
3831
3832
3833

www.ti.com
20-88. RTC_SYSCONFIG Register Field Descriptions .................................................................... 3834
20-89. RTC_IRQWAKEEN Register Field Descriptions ................................................................... 3835

20-90. ALARM2_SECONDS_REG Register Field Descriptions .......................................................... 3836
20-91. ALARM2_MINUTES_REG Register Field Descriptions ........................................................... 3837

20-92. ALARM2_HOURS_REG Register Field Descriptions
.............................................................
3838
...........................................................
3840
20-93. ALARM2_DAYS_REG Register Field Descriptions ................................................................ 3839

20-94. ALARM2_MONTHS_REG Register Field Descriptions
20-95. ALARM2_YEARS_REG Register Field Descriptions .............................................................. 3841

20-96. RTC_PMIC Register Field Descriptions ............................................................................. 3842
....................................................................
3843
......................................................................................
3845
20-97. RTC_DEBOUNCE Register Field Descriptions
20-98. Public WD Timer Module Connectivity Attributes .................................................................. 3845

20-99. Public WD Timer Clock Signals
20-100. Watchdog Timer Events .............................................................................................. 3846
20-101. Count and Prescaler Default Reset Values ........................................................................ 3847

20-102. Prescaler Clock Ratio Values
.......................................................................................
3848
20-103. Reset Period Examples .............................................................................................. 3848
20-104. Default Watchdog Timer Reset Periods............................................................................ 3849

20-105. Global Initialization of Surrounding Modules ...................................................................... 3852
20-106. Watchdog Timer Module Global Initialization...................................................................... 3852
..............................................................................
........................................................................................
20-109. Enable the Watchdog Timer .........................................................................................
20-110. Watchdog Timer Registers...........................................................................................
20-111. WDT_WIDR Register Field Descriptions...........................................................................
20-112. WDT_WDSC Register Field Descriptions..........................................................................
20-113. WDT_WDST Register Field Descriptions ..........................................................................
20-114. WDT_WISR Register Field Descriptions ...........................................................................
20-115. WDT_WIER Register Field Descriptions ...........................................................................
20-116. WDT_WCLR Register Field Descriptions ..........................................................................
20-117. WDT_WCRR Register Field Descriptions .........................................................................
20-118. WDT_WLDR Register Field Descriptions ..........................................................................
20-119. WDT_WTGR Register Field Descriptions..........................................................................
20-120. WDT_WWPS Register Field Descriptions .........................................................................
20-121. WDT_WDLY Register Field Descriptions ..........................................................................
20-122. WDT_WSPR Register Field Descriptions ..........................................................................
20-123. WDT_WIRQSTATRAW Register Field Descriptions .............................................................
20-124. WDT_WIRQSTAT Register Field Descriptions....................................................................
20-125. WDT_WIRQENSET Register Field Descriptions .................................................................
20-126. WDT_WIRQENCLR Register Field Descriptions .................................................................
21-1. Unsupported I2C Features ............................................................................................
21-2. I2C0 Connectivity Attributes...........................................................................................
21-3. I2C(12) Connectivity Attributes ......................................................................................
21-4. I2C Clock Signals.......................................................................................................
21-5. I2C Pin List ..............................................................................................................
21-6. Signal Pads..............................................................................................................
21-7. Reset State of I2C Signals ............................................................................................
21-8. I2C Registers............................................................................................................
21-9. I2C_REVNB_LO Register (Module Revision) (LOW BYTES) Field Descriptions ..............................
21-10. I2C_REVNB_HI Register (HIGH BYTES) (Module Revision) Field Descriptions ..............................
20-107. Watchdog Timer Basic Configuration
3852
20-108. Disable the Watchdog Timer
3853

List of Tables
3853
3854
3855
3855
3856
3856
3857
3857
3858
3858
3859
3859
3860
3860
3861
3862
3863
3864
3866
3867
3868
3868
3868
3870
3870
3882
3883
3884
147
www.ti.com
21-11. I2C_SYSC Register (System Configuration) Field Descriptions ................................................. 3885

3886
21-13. I2C_IRQSTATUS Register (I2C Status) Field Descriptions
3890
21-14.
3892
21-15.
21-16.
21-17.
21-18.
21-19.
21-20.
21-21.
21-22.
21-23.
21-24.
21-25.
21-26.
21-27.
21-28.
21-29.
21-30.
21-31.
21-32.
21-33.
21-34.
21-35.
21-36.
21-37.
21-38.
21-39.
22-1.
22-2.
22-3.
22-4.
22-5.
22-6.
22-7.
22-8.
22-9.
22-10.
22-11.
22-12.
22-13.
22-14.
22-15.
22-16.
22-17.
22-18.
22-19.
22-20.
148
........................................
......................................................
I2C_IRQENABLE_SET Register (I2C Interrupt Enable Set) Field Descriptions ...............................
I2C_IRQENABLE_CLR Register (I2C Interrupt Enable Clear) Field Descriptions .............................
I2C_WE Register (I2C Wakeup Enable) Field Descriptions ......................................................
I2C_DMARXENABLE_SET Register (Receive DMA Enable Set) Field Descriptions .........................
I2C_DMATXENABLE_SET Register (Transmit DMA Enable Set) Field Descriptions ........................
I2C_DMARXENABLE_CLR Register (Receive DMA Enable Clear) Field Descriptions ......................
I2C_DMATXENABLE_CLR Register (Transmit DMA Enable Clear) Field Descriptions ......................
I2C_DMARXWAKE_EN Register (Receive DMA Wakeup) Field Descriptions ................................
I2C_DMATXWAKE_EN Register (Transmit DMA Wakeup) Field Descriptions ................................
I2C_SYSS Register (System Status) Field Descriptions ..........................................................
I2C_BUF Register (Buffer Configuration) Field Descriptions .....................................................
I2C_CNT Register (Data Counter) Field Descriptions .............................................................
I2C_DATA Register (Data Access) Field Descriptions ............................................................
I2C_CON Register (I2C Configuration) Field Descriptions .......................................................
I2C_OA Register (I2C Own Address) Field Descriptions .........................................................
I2C_SA Register (I2C Slave Address) Field Descriptions ........................................................
I2C_PSC Register (I2C Clock Prescaler) Field Descriptions .....................................................
I2C_SCLL Register (I2C SCL Low Time) Field Descriptions .....................................................
I2C_SCLH Register (I2C SCL High Time) Field Descriptions ....................................................
I2C_SYSTEST Register (System Test) Field Descriptions .......................................................
I2C_BUFSTAT Register (I2C Buffer Status) Field Descriptions..................................................
I2C_OA1 Register (OA1) (Own Address 1) Field Descriptions...................................................
I2C_OA2 Register (I2C Own Address 2) Field Descriptions......................................................
I2C_OA3 Register (I2C Own Address 3) Field Descriptions......................................................
I2C_ACTOA Register (Active Own Address) Field Descriptions .................................................
I2C_SBLOCK Register (I2C Clock Blocking Enable) Field Descriptions........................................
McASP Connectivity Attributes .......................................................................................
McASP Clock Signals ..................................................................................................
McASP Pin List .........................................................................................................
Biphase-Mark Encoder ................................................................................................
Preamble Codes ........................................................................................................
McASP Interface Signals ..............................................................................................
Channel Status and User Data for Each DIT Block ................................................................
Transmit Bitstream Data Alignment ..................................................................................
Receive Bitstream Data Alignment ...................................................................................
McASP Registers Accessed Through Configuration Bus .........................................................
McASP AFIFO Registers Accessed Through Peripheral Configuration Port ...................................
Revision Identification Register (REV) Field Descriptions ........................................................
Pin Function Register (PFUNC) Field Descriptions ................................................................
Pin Direction Register (PDIR) Field Descriptions ..................................................................
Pin Data Output Register (PDOUT) Field Descriptions ...........................................................
Pin Data Input Register (PDIN) Field Descriptions.................................................................
Pin Data Set Register (PDSET) Field Descriptions ................................................................
Pin Data Clear Register (PDCLR) Field Descriptions .............................................................
Global Control Register (GBLCTL) Field Descriptions ............................................................
Audio Mute Control Register (AMUTE) Field Descriptions........................................................
21-12. I2C_IRQSTATUS_RAW Register (I2C Status Raw) Field Descriptions
List of Tables
3894
3896
3899
3899
3900
3900
3901
3903
3905
3906
3908
3909
3910
3912
3913
3914
3915
3915
3916
3919
3920
3921
3922
3923
3924
3928
3929
3929
3936
3937
3944
3951
3962
3964
3983
3984
3985
3987
3989
3991
3993
3995
3997
3998
4000

www.ti.com
................................................
Digital Mode Control Register (DITCTL) Field Descriptions ......................................................
Receiver Global Control Register (RGBLCTL) Field Descriptions ...............................................
Receive Format Unit Bit Mask Register (RMASK) Field Descriptions ...........................................
Receive Bit Stream Format Register (RFMT) Field Descriptions ................................................
Receive Frame Sync Control Register (AFSRCTL) Field Descriptions .........................................
Receive Clock Control Register (ACLKRCTL) Field Descriptions ...............................................
Receive High-Frequency Clock Control Register (AHCLKRCTL) Field Descriptions .........................
Receive TDM Time Slot Register (RTDM) Field Descriptions ....................................................
Receiver Interrupt Control Register (RINTCTL) Field Descriptions ..............................................
Receiver Status Register (RSTAT) Field Descriptions ............................................................
Current Receive TDM Time Slot Registers (RSLOT) Field Descriptions .......................................
Receive Clock Check Control Register (RCLKCHK) Field Descriptions ........................................
Receiver DMA Event Control Register (REVTCTL) Field Descriptions .........................................
Transmitter Global Control Register (XGBLCTL) Field Descriptions ............................................
Transmit Format Unit Bit Mask Register (XMASK) Field Descriptions ..........................................
Transmit Bit Stream Format Register (XFMT) Field Descriptions................................................
Transmit Frame Sync Control Register (AFSXCTL) Field Descriptions .........................................
Transmit Clock Control Register (ACLKXCTL) Field Descriptions ...............................................
Transmit High-Frequency Clock Control Register (AHCLKXCTL) Field Descriptions .........................
Transmit TDM Time Slot Register (XTDM) Field Descriptions ...................................................
Transmitter Interrupt Control Register (XINTCTL) Field Descriptions ...........................................
Transmitter Status Register (XSTAT) Field Descriptions .........................................................
Current Transmit TDM Time Slot Register (XSLOT) Field Descriptions ........................................
Transmit Clock Check Control Register (XCLKCHK) Field Descriptions .......................................
Transmitter DMA Event Control Register (XEVTCTL) Field Descriptions ......................................
Serializer Control Registers (SRCTLn) Field Descriptions ........................................................
Write FIFO Control Register (WFIFOCTL) Field Descriptions ....................................................
Write FIFO Status Register (WFIFOSTS) Field Descriptions.....................................................
Read FIFO Control Register (RFIFOCTL) Field Descriptions ....................................................
Read FIFO Status Register (RFIFOSTS) Field Descriptions .....................................................
McASP Registers Accessed Through Data Port ...................................................................
DCAN Connectivity Attributes .........................................................................................
DCAN Clock Signals ...................................................................................................
DCAN Pin List ...........................................................................................................
Initialization of a Transmit Object.....................................................................................
Initialization of a single Receive Object for Data Frames .........................................................
Initialization of a Single Receive Object for Remote Frames .....................................................
Parameters of the CAN Bit Time .....................................................................................
Structure of a Message Object .......................................................................................
Field Descriptions ......................................................................................................
Message RAM addressing in Debug/Suspend and RDA Mode ..................................................
Message RAM Representation in Debug/Suspend Mode ........................................................
Message RAM Representation in RAM Direct Access Mode ....................................................
DCAN Control Register Summary Table ............................................................................
CAN Control Register (DCAN CTL) Field Descriptions ...........................................................
Error and Status Register (DCAN ES) Field Descriptions ........................................................
Error Counter Register (DCAN ERRC) Field Descriptions ........................................................
Bit Timing Register (DCAN BTR) Field Descriptions ..............................................................
22-21. Digital Loopback Control Register (DLBCTL) Field Descriptions

22-22.
22-23.
22-24.
22-25.
22-26.
22-27.
22-28.
22-29.
22-30.
22-31.
22-32.
22-33.
22-34.
22-35.
22-36.
22-37.
22-38.
22-39.
22-40.
22-41.
22-42.
22-43.
22-44.
22-45.
22-46.
22-47.
22-48.
22-49.
22-50.
22-51.
22-52.
23-1.
23-2.
23-3.
23-4.
23-5.
23-6.
23-7.
23-8.
23-9.
23-10.
23-11.
23-12.
23-13.
23-14.
23-15.
23-16.
23-17.

List of Tables
4002
4003
4004
4005
4006
4008
4009
4010
4011
4012
4013
4014
4015
4016
4017
4018
4019
4021
4022
4023
4024
4025
4026
4027
4028
4029
4030
4033
4034
4035
4036
4036
4039
4040
4040
4056
4056
4057
4064
4074
4074
4076
4077
4077
4079
4080
4082
4084
4085
149
www.ti.com
4086
23-19.
4087
23-20.
23-21.
23-22.
23-23.
23-24.
23-25.
23-26.
23-27.
23-28.
23-29.
23-30.
23-31.
23-32.
23-33.
23-34.
23-35.
23-36.
23-37.
23-38.
23-39.
23-40.
23-41.
23-42.
23-43.
24-1.
24-2.
24-3.
24-4.
24-5.
24-6.
24-7.
24-8.
24-9.
24-10.
24-11.
24-12.
24-13.
24-14.
24-15.
24-16.
24-17.
24-18.
24-19.
24-20.
24-21.
24-22.
24-23.
150
.................................................................
Test Register (DCAN TEST) Field Descriptions ....................................................................
Parity Error Code Register (DCAN PERR) Field Descriptions ...................................................
Auto-Bus-On Time Register (DCAN ABOTR) Field Descriptions ................................................
Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78) ........................................
Transmission Request Registers (DCAN TXRQ12 to DCAN TXRQ78) Field Descriptions ..................
New Data Registers (DCAN NWDAT12 to DCAN NWDAT78) ...................................................
New Data Registers (DCAN NWDAT12 to DCAN NWDAT78) Field Descriptions ............................
New Data Registers (DCAN NWDAT12 to DCAN NWDAT78) ...................................................
New Data Registers (DCAN NWDAT12 to DCAN NWDAT78) Field Descriptions ............................
Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78) ..........................................
Message Valid Registers (DCAN MSGVAL12 to DCAN MSGVAL78) Field Descriptions ....................
Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78) ......................................
Interrupt Multiplexer Registers (DCAN INTMUX12 to DCAN INTMUX78) Field Descriptions ...............
IF1/IF2 Command Registers (DCAN IF1CMD, DCAN IF2CMD) Field Descriptions ..........................
IF1/IF2 Mask Registers (DCAN IF1MSK, DCAN IF2MSK) Field Descriptions .................................
IF1/IF2 Arbitration Registers (DCAN IF1ARB, DCAN IF2ARB) Field Descriptions ............................
IF1/IF2 Message Control Registers (DCAN IF1MCTL, DCAN IF2MCTL) Field Descriptions ................
IF3 Observation Register (DCAN IF3OBS) Field Descriptions ...................................................
IF3 Mask Register (DCAN IF3MSK) Field Descriptions ...........................................................
IF3 Arbitration Register (DCAN IF3ARB) Field Descriptions .....................................................
IF3 Message Control Register (DCAN IF3MCTL) Field Descriptions ...........................................
Update Enable Registers (DCAN IF3UPD12 to IF3UPD78)) .....................................................
Update Enable Registers (DCAN IF3UPD12 to IF3UPD78) Field Descriptions ...............................
CAN TX I/O Control Register (DCAN TIOC) Field Descriptions .................................................
CAN RX IO Control Register (DCAN RIOC) Field Descriptions..................................................
Unsupported McSPI Features ........................................................................................
McSPI Connectivity Attributes ........................................................................................
McSPI Clock Signals ...................................................................................................
McSPI Pin List ..........................................................................................................
Phase and Polarity Combinations ...................................................................................
Chip Select Clock Edge Delay Depending on Configuration .................................................
CLKSPIO High/Low Time Computation ............................................................................
Clock Granularity Examples...........................................................................................
FIFO Writes, Word Length Relationship .............................................................................
SPI Registers ...........................................................................................................
McSPI Revision Register (MCSPI_REVISION) Field Descriptions ..............................................
McSPI System Configuration Register (MCSPI_SYSCONFIG) Field Descriptions ............................
McSPI System Status Register (MCSPI_SYSSTATUS) Field Descriptions ....................................
McSPI Interrupt Status Register (MCSPI_IRQSTATUS) Field Descriptions ...................................
McSPI Interrupt Enable Register (MCSPI_IRQENABLE) Field Descriptions ...................................
McSPI System Register (MCSPI_SYST) Field Descriptions .....................................................
McSPI Module Control Register(MCSPI_MODULCTRL) Field Descriptions ...................................
McSPI Channel (i) Configuration Register (MCSPI_CH(i)CONF) Field Descriptions .........................
Data Lines Configurations .............................................................................................
McSPI Channel (i) Status Register (MCSPI_CH(i)STAT) Field Descriptions ..................................
McSPI Channel (i) Control Register (MCSPI_CH(I)CTRL) Field Descriptions .................................
McSPI Channel (i) Transmit Register (MCSPI_TX(i)) Field Descriptions .......................................
McSPI Channel (i) Receive Register (MCSPI_RX(i)) Field Descriptions .......................................
23-18. Interrupt Register (DCAN INT) Field Descriptions
List of Tables
4088
4089
4091
4091
4093
4093
4095
4095
4097
4097
4098
4098
4100
4102
4103
4105
4108
4110
4111
4112
4115
4115
4116
4118
4121
4123
4123
4123
4128
4138
4140
4140
4141
4160
4161
4162
4163
4164
4167
4169
4171
4173
4176
4177
4178
4179
4179

www.ti.com
24-24. McSPI Transfer Levels Register (MCSPI_XFERLEVEL) Field Descriptions ................................... 4180
24-25. McSPI DMA Address Aligned FIFO Transmitter Register (MCSPI_DAFTX) Field Descriptions ............. 4181
24-26. McSPI DMA Address Aligned FIFO Receiver Register (MCSPI_DAFRX) Field Descriptions
25-1.
25-2.
...............
4182
GPIO0 Connectivity Attributes ........................................................................................ 4186
GPIO[1:3] Connectivity Attributes .................................................................................... 4186
25-3.
GPIO Clock Signals .................................................................................................... 4186
25-4.
GPIO Pin List
25-5.
25-6.
...........................................................................................................
4187
GPIO REGISTERS ..................................................................................................... 4195

GPIO_REVISION Register Field Descriptions ...................................................................... 4196
25-7.
GPIO_SYSCONFIG Register Field Descriptions ................................................................... 4197
25-8.
GPIO_IRQSTATUS_RAW_0 Register Field Descriptions
25-9.
25-10.
25-11.
25-12.
25-13.
25-14.
25-15.
25-16.
25-17.
25-18.
25-19.
25-20.
25-21.
25-22.
25-23.
25-24.
25-25.
25-26.
25-27.
25-28.
26-1.
26-2.
26-3.
26-4.
26-5.
26-6.
26-7.
26-8.
26-9.
26-10.
26-11.
26-12.
26-13.
26-14.
26-15.
26-16.
26-17.
26-18.
........................................................
GPIO_IRQSTATUS_RAW_1 Register Field Descriptions ........................................................
GPIO_IRQSTATUS_0 Register Field Descriptions ................................................................
GPIO_IRQSTATUS_1 Register Field Descriptions ................................................................
GPIO_IRQSTATUS_SET_0 Register Field Descriptions .........................................................
GPIO_IRQSTATUS_SET_1 Register Field Descriptions .........................................................
GPIO_IRQSTATUS_CLR_0 Register Field Descriptions .........................................................
GPIO_IRQSTATUS_CLR_1 Register Field Descriptions .........................................................
GPIO_SYSSTATUS Register Field Descriptions...................................................................
GPIO_CTRL Register Field Descriptions............................................................................
GPIO_OE Register Field Descriptions ...............................................................................
GPIO_DATAIN Register Field Descriptions .........................................................................
GPIO_DATAOUT Register Field Descriptions ......................................................................
GPIO_LEVELDETECT0 Register Field Descriptions ..............................................................
GPIO_LEVELDETECT1 Register Field Descriptions ..............................................................
GPIO_RISINGDETECT Register Field Descriptions ..............................................................
GPIO_FALLINGDETECT Register Field Descriptions.............................................................
GPIO_DEBOUNCENABLE Register Field Descriptions ..........................................................
GPIO_DEBOUNCINGTIME Register Field Descriptions ..........................................................
GPIO_CLEARDATAOUT Register Field Descriptions .............................................................
GPIO_SETDATAOUT Register Field Descriptions ................................................................
ROM Exception Vectors ...............................................................................................
Dead Loops .............................................................................................................
RAM Exception Vectors ...............................................................................................
Tracing Data ............................................................................................................
Crystal Frequencies Supported .......................................................................................
ROM Code Default Clock Settings ...................................................................................
SYSBOOT Configuration Pins[5] .....................................................................................
XIP Timings Parameters ...............................................................................................
Pins Used for NOR Boot ..............................................................................................
Special SYSBOOT Pins for NOR Boot ..............................................................................
NAND Timings Parameters ...........................................................................................
ONFI Parameters Page Description .................................................................................
Supported NAND Devices .............................................................................................
4th NAND ID Data Byte................................................................................................
Pins Used for NANDI2C Boot for I2C EEPROM Access ..........................................................
NAND Geometry Information on I2C EEPROM ....................................................................
ECC Configuration for NAND Boot ...................................................................................
Pins Used for NAND Boot .............................................................................................

List of Tables
4198
4199
4200
4201
4202
4203
4204
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4223
4223
4224
4225
4226
4227
4230
4240
4241
4241
4243
4244
4244
4245
4246
4246
4246
4251
151
www.ti.com
4252
26-20.
4256
26-21.
26-22.
26-23.
26-24.
26-25.
26-26.
26-27.
26-28.
26-29.
26-30.
26-31.
26-32.
26-33.
26-34.
26-35.
26-36.
26-37.
26-38.
26-39.
A-1.
152
............................................................................
Master Boot Record Structure ........................................................................................
Partition Entry ...........................................................................................................
Partition Types ..........................................................................................................
FAT Boot Sector ........................................................................................................
FAT Directory Entry ....................................................................................................
FAT Entry Description .................................................................................................
Pins Used for MMC0 Boot.............................................................................................
Pins Used for MMC1 Boot.............................................................................................
Pins Used for SPI Boot ................................................................................................
Blocks and Sectors Searched on Non-XIP Memories .............................................................
Pins Used for EMAC Boot in MII Mode ..............................................................................
Pins Used for EMAC Boot in RGMII Mode ..........................................................................
Pins Used for EMAC Boot in RMII Mode ............................................................................
Ethernet PHY Mode Selection ........................................................................................
Pins Used for UART Boot .............................................................................................
Customized Descriptor Parameters ..................................................................................
Pins Used for USB Boot ...............................................................................................
GP Device Image Format .............................................................................................
Booting Parameters Structure ........................................................................................
Tracing Vectors .........................................................................................................
Document Revision History ...........................................................................................
26-19. Special SYSBOOT Pins for NAND Boot
List of Tables
4257
4257
4258
4262
4263
4263
4263
4264
4264
4267
4267
4267
4267
4268
4269
4270
4271
4272
4274
4277


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AM335x ARM Cortex-A8 Microprocessors

Technical Reference Manual

Literature Number: SPRUH73E

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

Interrupt Controller Registers ........................................................................................... 211

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

control_status Register (offset = 40h) [reset = 0h] .........................................................

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

tpcc_evt_mux_12_15 Register (offset = F9Ch) [reset = 0h] .............................................

Enhanced Direct Memory Access (EDMA)

Introduction ............................................................................................................... 996

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

11.3.7 EDMA3 Channel Controller Regions .......................................................................

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

13.3.4 LIDD Controller ...............................................................................................

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

Pulse-Width Modulation Subsystem (PWMSS)

Pulse-Width Modulation Subsystem (PWMSS) ....................................................................

Universal Serial Bus (USB)

Functional Description .................................................................................................

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

16.2.3 USB Pin List ...................................................................................................

Multimedia Card (MMC)

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

Universal Asynchronous Receiver/Transmitter (UART)

18.3.13 Card Boot Mode Management ............................................................................

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

20.4.3 Functional Description ....................................................................................... 3846

I2C ................................................................................................................................ 3865

Multichannel Audio Serial Port (McASP)

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

Controller Area Network (CAN)

Multichannel Serial Port Interface (McSPI)

22.3.14 EDMA Event Support .......................................................................................

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

24.3.9 Reset ...........................................................................................................

Functional Description .................................................................................................

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

Microprocessor Unit (MPU) Subsystem Signal Interface ........................................................... 172

MPU Subsystem Clocking Scheme

Reset Scheme of the MPU Subsystem ............................................................................... 174

MPU Subsystem Power Domain Overview ........................................................................... 177

SGX530 Integration ...................................................................................................... 187

SGX Block Diagram

Microprocessor Unit (MPU) Subsystem ............................................................................... 170

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

INTC_MIR_CLEAR3 Register .......................................................................................... 252

INTC_MIR_SET3 Register .............................................................................................. 253

INTC_ISR_SET3 Register .............................................................................................. 254

SPRUH73E October 2011 Revised May 2012

Copyright 20112012, Texas Instruments Incorporated

00 Cover & Contents

00 Cover & Contents