This document details the implementation of two microcontroller models: the 8051 from Intel and the 16f54 from PIC. The 8051 core includes an arithmetic and logic unit to support a huge set of instructions. Most of the data format is in 8 bit format. Some instructions do not appear in this list, such as the multiplication and division.
This document details the implementation of two microcontroller models: the 8051 from Intel and the 16f54 from PIC. The 8051 core includes an arithmetic and logic unit to support a huge set of instructions. Most of the data format is in 8 bit format. Some instructions do not appear in this list, such as the multiplication and division.
This document details the implementation of two microcontroller models: the 8051 from Intel and the 16f54 from PIC. The 8051 core includes an arithmetic and logic unit to support a huge set of instructions. Most of the data format is in 8 bit format. Some instructions do not appear in this list, such as the multiplication and division.
Etienne SICARD Professor INSA-Dgei, 135 Av de Rangueil 31077 Toulouse France email: Etienne.sicard@insa-toulouse.fr
This document details the implementation of two microcontroller models: the 8051 from Intel and the 16f54 from PIC.
1 Logic Model of the 8051 In DSCH3, a simplified model of the Intel 8051 micro-controller is included. 1.1 Arithmetic and Logic Unit The 8051 core includes an arithmetic and logic unit to support a huge set of instructions. Most of the data format is in 8 bit format. We consider here the following instructions, listed in table 1. Some instructions do not appear in this list, such as the multiplication and division.
Mnemonic Type Description CLR Clear Clear the accumulator CPL Complement Complements the accumulator, a bit or a memory contents. All the bits will be reversed. ADD Addition Add the operand to the value of the accumulator, leaving the resulting value in the accumulator. SUBB Substractor Subtracts the operand to the value of the accumulator, leaving the resulting value in the accumulator. INC Increment Increment the content of the accumulator, the register or the memory. DEC Decrement Decrement the content of the accumulator, the register or the memory. XRL XOR operator Exclusive OR operation between the accumulator and the operand, leaving the resulting value in the accumulator. ANL AND operator AND operation between the accumulator and the operand, leaving the resulting value in accumulator. ORL OR operator OR operation between the accumulator and the operand, leaving the resulting value in accumulator. RR Rotate right Shifts the bits of the accumulator to the right. The bit 0 is loaded into bit 7. RL Rotate left Shifts the bits of the accumulator to the left. The bit 7 is loaded into bit 0. Table 1. Some important instructions implemented in the ALU of the 8051 micro-controller
Page 1/12 DSCH APPLICATION NOTE Microcontrollers
Accumulator A Arithmetic and Logic Unit 8 bits 8 bits Result S 8 bits OpCode input Registers R0..R7 Immediate value Memory contents CarryIn CarryOut
Figure 2. The arithmetic and logic unit of the 8051
For example: ADD A,R0 (Opcode 0x28) overwrites the accumulator with the result of the addition of A and the content of R0. SUBB A,#2 (Opcode 0x94 0x02) overwrites the accumulator with the result of the subtraction of A and the sum of the Carry and the byte 0x02. INC A (0x04) increments the content of the accumulator. DEC A (0x14) Decrements the content of the accumulator. ANL A,#10 (0x54) overwrites the accumulator with by the AND-gating of A and the constant 0x10. ORL A,R7 (0x4F) overwrites the accumulator with by the OR-gating of A and the content of R7. XRL A, R1 (0x69) overwrites the accumulator with the result of the XOR-gating of A and the content of the internal register R1. 1.2 Inside the 8051 A simplified model of the 8-bit micro-controller 8051 exists through the symbol 8051.SYM accessible using the command Insert User Symbol. The symbol is also directly accessible through the symbol palette starting version 3.5. Page 2/12 DSCH APPLICATION NOTE Microcontrollers
Figure 3. The IEEE symbol library contains the 8051 symbol (8051.SYM)
Figure 4. Access to the 8051 symbol from the palette, in the Advanced list
The symbol consists mainly of general purpose input/output ports (P0,P1,P2 and P3), a clock and a reset control signals. The basic connection consists of a clock on the Clock input and a button on the Reset input (Figure 5).
Page 3/12 DSCH APPLICATION NOTE Microcontrollers
Figure 5. The 8051 symbol and its embedded software (8051.SCH) After a double-click in the symbol, the embedded code appears. That code may be edited and modified (Figure 6). When the button Assembly is pressed, the assembly text is translated into executable binary format. Once the logic simulation is running, the code is executed as soon as the reset input is deactivated. The value of the program counter, the accumulator A, the current op_code and the registers is displayed.
1.3 Minimum features for running the 8051 The user should 1. Add a clock on input Clock 2. Add a button on input RST 3. Double click on the symbol and click Assembly so that the editable text of the code is converted into assembly code 4. Run the logic simulator 5. Click the RST button (RST=1, button red) so that Reset is INACTIVE
In the chronograms, the accumulator variations versus the time are displayed. It can be noticed that this core operates with one single clock cycle per instruction, except for some instructions such as MOV (Move data) and AJ MP (J ump to a specific address).
Page 4/12 DSCH APPLICATION NOTE Microcontrollers Click Assembly to compute
Figure 6. The default code proposed in the 8051 component compiled using DSCH3 (8051.SYM)
Figure 7. The simulation of the arithmetic and logic operation using the 8051 micro-controller (8051.SCH) 1.4 Traffic light Example An example of code and schematic diagram for traffic light control is proposed below. Notice the subroutine call through the instruction AJ UMP.
Figure 8. A simple code for 8051 micro-controller for traffic light control (8051_traffic_lights.sch) Page 5/12 DSCH APPLICATION NOTE Microcontrollers
Figure 9. Interface for compiling the code for the traffic light controller (8051_traffic_lights.sch) Ports are activated using control commands such as MOV P3,#0, while port input pins are tested through the instruction such as J B P2.2,URG. See table 2 for the complete code embedded in the 8051 processor.
/ / Tr af f i c Li ght s E. Si car d / / 11. nov. 01 L1 MOV P3, #84H ACALL TEMPO { Feu1=r , F2=ver t } J B P2. 2, URG J B P2. 1, FJ AJ MP L1 FJ ACALL TEMPO MOV P3, #88H { Feu1=r , F2=j aune} ACALL TEMPO MOV P3, #90H ACALL TEMPO { r , r } L2 MOV P3, #30H { v , r } J B P2. 2, URG J B P2. 0, FJ 1 AJ MP L2
FJ 1 ACALL TEMPO MOV P3, #50H ACALL TEMPO { j , r } MOV P3, #90H ACALL TEMPO { r , r } MOV P3, #84H AJ MP L1
{ Tempor i sat i on} TEMPO NOP NOP NOP NOP NOP NOP NOP RET { Ur gence } URG MOV P3, #48H NOP MOV P3, #0 J NB P2. 2, L1 AJ MP URG
Table 2. Code embedded in the traffic light controller (8051_traffic_lights.sch) Page 6/12 DSCH APPLICATION NOTE Microcontrollers
2 Model of the PIC 16f84 DSCH3 includes the model of the PIC16f84 micro-controller. 2.1 Activating Ports of the 16f84 The following program is used to activate the Port B as output. The schematic diagram which implements this code is 16f84.SCH (Fig. 10). The corresponding simulation is reported in Fig. 11.
; PI C16f 84 by Et i enne Si car d f or Dsch ; Si mpl e pr ogr amt o put 10101010 on por t B ; 01010101 on por t B ; Por t B equ 0x06 ; decl ar es t he addr ess of out put por t B
or g 0 l oop movl w 0x55 ; l oad Wwi t h a pat t er n ( hexa f or mat ) movwf Por t B ; Moves t he pat t er n t o por t B movl w 0xaa ; l oad Wwi t h an ot her pat t er n movwf Por t B ; Moves t he pat t er n t o por t B got o l oop ; and agai n
Figure 10. Simulation of the PIC 16f84 (16f84.SCH) Page 7/12 DSCH APPLICATION NOTE Microcontrollers
Figure 11. Activating output ports of the PIC 16f84 (16f84.SCH) 2.2 Adder using 16f84 An example file can be found in 16f84adder.SCH. Double click the 16f84 symbol, and click Assembly to convert the text lines into binary executable code.
; Si mpl e pr ogr amt o add t wo number s ; oper 1 EQU 0x0c oper 2 EQU 0x0d r esul t EQU 0x0e
or g 0
movl w 5 movwf oper 1 movl w 2 movwf oper 2 movf oper 1, 0 addwf oper 2, 0 movwf r esul t sl eep
Then click OK, run the simulation. Click the Reset button to activate the processor. The default code realizes the addition of two numbers (Instruction addwf ) and stores the result in the internal registers. Modify the code to perform the AND (Instruction andwf ), OR (Instruction i or wf ) , XOR (Instruction xor wf ) and SUB (Instruction subwf ) operations. Page 8/12 DSCH APPLICATION NOTE Microcontrollers
Figure 12. Adder using PIC 16f84 (16f84_adder.SCH)
3 References E. Sicard, S. Ben Dhia Basic CMOS cell Design Mc Graw Hill professional series, 2006, http://books.mcgraw- hill.com E. Sicard. Microwind & Dsch user's manual version 3.5 on-line at http://www.microwind.org Page 9/12 DSCH APPLICATION NOTE Microcontrollers
4 Appendix 4.1 8051 Labels Name Descr i pt i on Addr ess SP St ack $81 P0 Por t 0 $80 P1 Por t 1 $90 P2 Por t 2 $A0 P3 Por t 3 $B0 P0. 0 Por t 0 bi t 0 $80 P0. 1 Por t 0 bi t 1 $81 P0. 2 Por t 0 bi t 2 $82 P0. 3 Por t 0 bi t 3 $83 P0. 4 Por t 0 bi t 4 $84 P0. 5 Por t 0 bi t 5 $85 P0. 6 Por t 0 bi t 6 $86 P0. 7 Por t 0 bi t 7 $87
4.2 8051 Instruction Model
CASE muCode OF $0 : ; $1 : muAddr ess: = Next Byt e( 1) ; $3 : i f ( mur egA AND $01) <> 0 t hen mur egA: =( mur egA shr 1) +$80 el se mur egA: =( mur egA shr 1) ; $4 : I F muRegA<$FF THEN / / I nc I nc( muRegA) ELSE muRegA : = 0; $08, $09, $0A, $0B, $0C, $0D, $0E, $0F: i nc( mur eg[ mucode- $8] ) ; $11 : begi n must ak[ muSp] : = muAddr ess+2; muAddr ess: =Next Byt e( 1) ; i nc( muSp) ; end; $14 : I F muRegA=0 THEN muRegA : = $FF ELSE Dec( muRegA) ; / / DEC $18, $19, $1A, $1B, $1C, $1D, $1E, $1F: dec( mur eg[ mucode- $18] ) ; $20 : I F Pi n( Bi t Pi n( 1) ) =l ogi c1 THEN J umpRel at i ve( 2) el se muAddr ess: = muAddr ess+3; $22 : begi n dec( muSp) ; muAddr ess: =must ak[ muSp] ; end; $23 : BEGI N i f ( mur egA AND $80) <>0 t hen myVal : =( mur egA shl 1) +1 el se myVal : =( mur egA shl 1) ; muRegA : = myVal AND $00FF; END; $24 : BEGI N myVal : =muRegA+Next Byt e( 1) ; muRegA : = myVal AND $00FF; END; $28, $29, $2A, $2B, $2C, $2D, $2E, $2F: BEGI N myVal : =mur egA+mur eg[ mucode- $28] ; muRegA : = myVal AND $00FF; END; $30 : I F Pi n( Bi t Pi n( 1) ) =l ogi c0 THEN J umpRel at i ve( 2) el se muAddr ess: = muAddr ess+3; $44 : mur egA: =mur egA or Next Byt e( 1) ; / / ORL Page 10/12 DSCH APPLICATION NOTE Microcontrollers $48, $49, $4A, $4B, $4C, $4D, $4E, $4F: mur egA: =mur egA or mur eg[ mucode- $48] ; $54 : mur egA: =mur egA and Next Byt e( 1) ;
$58, $59, $5A, $5B, $5C, $5D, $5E, $5F: mur egA: =mur egA and mur eg[ mucode- $58] ; $60 : i f mur egA=$0 t hen j umpr el at i ve( 1) el se muAddr ess: =muAddr ess+2; $64 : mur egA: =mur egA xor Next Byt e( 1) ; / / XRL $68, $69, $6A, $6B, $6C, $6D, $6E, $6F: mur egA: =mur egA xor mur eg[ mucode- $68] ; $70 : i f mur egA<>$0 t hen j umpr el at i ve( 1) el se muAddr ess: =muAddr ess+2; $73 : j umpr el at i ve( 1) ; $74 : muRegA : = Next Byt e( 1) ; $75 : DumpDat a( 1, Next Byt e( 2) ) ; $78, $79, $7A, $7B, $7C, $7D, $7E, $7F: mur eg[ mucode- $78] : =mumem[ muAddr ess+1] ; $B2 : i f Pi n( Bi t Pi n( 1) ) =l ogi c1 t hen St or e( Bi t Pi n( 1) , l ogi c0) el se St or e( Bi t Pi n( 1) , l ogi c1) ; $B4 : i f muRegA<>Next Byt e( 1) t hen J umpRel at i ve( 2) el se muAddr ess: =muAddr ess+3; $B8, $B9, $BA, $BB, $BC, $BD, $BE, $BF: i f mur eg[ mucode- $B8] <>Next Byt e( 1) t hen j umpr el at i ve( 2) el se muAddr ess: =muAddr ess+3; $C2 : St or e( Bi t Pi n( 1) , l ogi c0) ; $D2 : St or e( Bi t Pi n( 1) , l ogi c1) ; $E4 : mur egA: =0; / / CLR A $E5 : muRegA : = Dat aOf Byt e( 1) ; $E8, $E9, $EA, $EB, $EC, $ED, $EE, $EF: mur egA : = mur eg[ mucode- $E8] ; $F4 : mur egA: =mur egA xor $FF; / / CPL $F5 : DumpDat a( 1, muRegA) ; $F8, $F9, $FA, $FB, $FC, $FD, $FE, $FF: mur eg[ mucode- $F8] : =mur egA; END; 4.3 16f84 Instruction Model
I F wor ds[ 2] =' ADDLW' t hen dat aWor d : = addl w OR ( HexAdr ( wor ds[ 3] ) AND $FF) el se I F wor ds[ 2] =' ANDLW' t hen dat aWor d : = andl w OR ( HexAdr ( wor ds[ 3] ) AND $FF) el se I F wor ds[ 2] =' ADDWF' t hen dat aWor d : = addwf OR ( HexAdr ( wor ds[ 3] ) AND $7F) OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 8) el se I F wor ds[ 2] =' ANDWF' t hen dat aWor d : = andwf OR ( HexAdr ( wor ds[ 3] ) AND $7F) OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 8)
I F wor ds[ 2] =' BCF' t hen dat aWor d : = bcf OR ( HexAdr ( wor ds[ 4] ) SHL 7) OR ( HexAdr ( wor ds[ 3] ) AND $7F) el se I F wor ds[ 2] =' BTFSC' t hen dat aWor d : = bt f sc OR ( HexAdr ( wor ds[ 4] ) SHL 7) OR ( HexAdr ( wor ds[ 3] ) AND $7F) el se I F wor ds[ 2] =' BSF' t hen dat aWor d : = bsf OR ( HexAdr ( wor ds[ 4] ) SHL 7) OR ( HexAdr ( wor ds[ 3] ) AND $7F) el se I F wor ds[ 2] =' BTFSS' t hen dat aWor d : = bt f ss OR ( HexAdr ( wor ds[ 4] ) SHL 7) OR ( HexAdr ( wor ds[ 3] ) AND $7F)
I F wor ds[ 2] =' CALL' t hen dat aWor d : = cal l OR ( HexAdr ( wor ds[ 3] ) AND $7FF) el se I F wor ds[ 2] =' CLRF' t hen dat aWor d : = cl r f OR ( HexAdr ( wor ds[ 3] ) AND $7F) el se I F wor ds[ 2] =' CLRW' t hen dat aWor d : = cl r w OR ( HexAdr ( wor ds[ 3] ) AND $7F) el se I F wor ds[ 2] =' CLRWDT' t hen dat aWor d : = cl r wdt el se I F wor ds[ 2] =' COMF' t hen dat aWor d : = comf OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7) OR ( HexAdr ( wor ds[ 3] ) AND $7F)
I F wor ds[ 2] =' DECFSZ' t hen dat aWor d : = decf sz OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7) OR ( HexAdr ( wor ds[ 3] ) AND $7F) el se Page 11/12 DSCH APPLICATION NOTE Microcontrollers I F wor ds[ 2] =' DECF' t hen dat aWor d : = decf OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7) OR ( HexAdr ( wor ds[ 3] ) AND $7F)
I F wor ds[ 2] =' EQU' t hen DoNot hi ng ELSE I F wor ds[ 2] =' END' t hen DoNot hi ng
I F wor ds[ 2] =' GOTO' t hen BEGI N dat aWor d : = got o1 OR ( HexAdr ( wor ds[ 3] ) AND $7FF) ; END
I F wor ds[ 2] =' I NCF' t hen dat aWor d : = i ncf OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7) OR ( HexAdr ( wor ds[ 3] ) AND $7F) el se I F wor ds[ 2] =' I NCFSZ' t hen dat aWor d : = i ncf sz OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7) OR ( HexAdr ( wor ds[ 3] ) AND $7F) el se I F wor ds[ 2] =' I ORLW' t hen dat aWor d : = i or l w OR ( HexAdr ( wor ds[ 3] ) AND $FF) el se I F wor ds[ 2] =' I ORWF' t hen dat aWor d : = i or wf OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7) OR ( HexAdr ( wor ds[ 3] ) AND $7F)
I F wor ds[ 2] =' MOVLW' t hen dat aWor d : = movl w OR ( HexAdr ( wor ds[ 3] ) AND $FF) el se I F wor ds[ 2] =' MOVF' t hen dat aWor d : = movf OR ( HexAdr ( wor ds[ 3] ) AND $7F) OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7) el se I F wor ds[ 2] =' MOVWF' t hen dat aWor d : = movwf OR ( HexAdr ( wor ds[ 3] ) AND $7F)
I F wor ds[ 2] =' NOP' t hen dat aWor d : = nop;
I F wor ds[ 2] =' ORG' t hen BEGI N act ual Addr ess: =HexAdr ( wor ds[ 3] ) ; byt eNumber : =0; i gnor eLi ne : = TRUE; END
I F wor ds[ 2] =' RETFI E' t hen dat aWor d : =r et f i e el se I F wor ds[ 2] =' RETLW' t hen dat aWor d : =r et l w OR ( HexAdr ( wor ds[ 3] ) AND $FF) el se I F wor ds[ 2] =' RETURN' t hen dat aWor d : =r et ur n el se I F wor ds[ 2] =' RLF' t hen dat aWor d : = r l f OR ( HexAdr ( wor ds[ 3] ) AND $7F) OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7) el se I F wor ds[ 2] =' RRF' t hen dat aWor d : = r r f OR ( HexAdr ( wor ds[ 3] ) AND $7F) OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7)
I F wor ds[ 2] =' SLEEP' t hen dat aWor d : = sl eep1 el se I F wor ds[ 2] =' SUBLW' t hen dat aWor d : =subl w OR ( HexAdr ( wor ds[ 3] ) AND $FF) el se I F wor ds[ 2] =' SUBWF' t hen dat aWor d : = subwf OR ( HexAdr ( wor ds[ 3] ) AND $7F) OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7) el se I F wor ds[ 2] =' SWAPF' t hen dat aWor d : = swapf OR ( HexAdr ( wor ds[ 3] ) AND $7F) OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7)
I F wor ds[ 2] =' XORLW' t hen dat aWor d : = xor l w OR ( HexAdr ( wor ds[ 3] ) AND $FF) el se I F wor ds[ 2] =' XORWF' t hen dat aWor d : = xor wf OR ( HexAdr ( wor ds[ 3] ) AND $7F) OR ( ( HexAdr ( wor ds[ 4] ) AND $01) SHL 7) Page 12/12