VERY LARGE SCALE INTEGRATION

From KARSHAK ENGINEERING COLLEGE,

ECE 3RD YEAR.

Members,
CH.NEERAJA- neeru_chimata@yahoo.co.in
CH.SUPRIYA

]
 VERY LARGE SCALE INTEGRATION

ABSTRACT:

Electronics as we know it today is characterized by reliability, low power

dissipation ,extremely low weight and volume, and low cost, coupled with an ability to
cope easily with a high degree of sophistication and complexity .
Electronics , and in particular the integrated circuit ,has made possible the design of
powerful and flexible processors which provide highly intelligent and adaptable devices
for the user . Integrated circuit memories have provided the essential elements to
complete this processors and together with a wide range of logic and analog integrated
circuitry.
The invention of transistor by William B Shockley ,Walter H. Brattian and John
Bardeen of bell telephone laboratories was followed by the development of the integrated
circuits.
Over the past several years ,silicon CMOS technology has become the dominate
fabrication process for relatively high performance and cost effective VLSI circuits.
VLSI technology providing the user with a new and more complex range of ’off
the shelf ’circuits, but VLSI design processes are such that system designer can readily
design their own special circuits of considerable complexity . This provides a new degree
of freedom for designer and it is probable that some very significant advances will result .

Functions of IC

• Less area/volume and therefore, compactness

• Less power consumption
• Less testing requirements at system level
• Higher reliability, mainly due to improved on-chip interconnects
• Higher speed, due to significantly reduced interconnection length
• Significant cost savings
HISTORY OF IC’S

Integrated circuit (IC), electronic circuit built on a semiconductor substrate,

usually one of single-crystal silicon. The circuit, often called a chip, is packaged in a
hermetically sealed case or a non-hermetic plastic capsule, with leads extending from it
for input, output, and power-supply connections, and for other connections that may be
necessary when the device is put to use. Integrated circuits can be classified into two
groups based on the type of transistor they contain. Bipolar integrated circuits contain
bipolar junction transistors as their principle elements. Metal-oxide-semiconductor
(MOS) integrated contain MOS transistors as their principle elements. Some integrated
circuits contain both types of transistors. An integrated circuit (IC) is a thin chip
consisting of at least two interconnected semiconductor devices mainly transistors, as
well as passive components like resistors .The following are the IC depends on number of
transistor
Integrated Circuit Evolution
Approx.
Size Description
Date
A few transistors and other components combined to form an
1950s gate level
AND, OR or NOR gates
4 or more gates; NAND, NOR, OR, AND, EXOR, NOT or
mid 1960s SSI
INVERT
Early
MSI up to 200 gates; registers, decoders, multiplexers, etc.
1970s
several hundred gates; ALU with scratch-pad registers, interrupt
late 1970s LSI
controllers, microprogram sequencers, ROMs, PROM
1980s VLSI 700 gates and up; CPUs, complex functions
1980s ASIC up to 30,000 gates; multiple functions
Early up to 100,000 gates and increasing with speeds at 1.4GHz and
ASIC
1990s higher
1980-1990s EPAC The development of analog circuit arrays
Deep SubMicron (< 0.18µ) designs; 1 Million gate arrays;
DSM
1990s System on a Chip
SoC IP
Intellectual Property - soft and hard IP building blocks
Deep SubMicron (0.13µ) designs; 4-10 Million gate arrays;
Design
2000 and more gates, faster designs; improved test methodology; faster
Reuse (IP);
up synthesis
High-speed
the 1 GHz and faster CPUs
VLSI

The final step in the development process, starting in the 1980s and continuing
on, was "Very Large-Scale Integration" (VLSI), with hundreds of thousands of
transistors. For the first time it became possible to fabricate a CPU or even an entire
microprocessor on a single integrated circuit. In 1986 the first one mega bit RAM chips
were introduced, which contained more than one million transistors. Microprocessor
chips produced in 1994 contained more than three million transistors.

VLSI Design Flow

The design process, at various levels, is usually evolutionary in nature. It starts

with a given set of requirements. Initial design is developed and tested against the
requirements. When requirements are not met, the design has to be improved. If such
improvement is either not possible or too costly, then the revision of requirements and its
impact analysis must be considered. The Y-chart shown illustrates a design flow for
most logic chips, using design activities on three different axes (domains) which
resemble the letter Y.

Typical VLSI design flow in three domains (Y-chart representation).

The Y-chart consists of three major domains, namely:

 Behavioral domain,
 Structural domain,
 Geometrical layout domain.

The design flow starts from the algorithm that describes the behavior of the target
chip. The corresponding architecture of the processor is first defined. It is mapped onto
the chip surface by floor planning. The next design evolution in the behavioral domain
defines finite state machines (FSM’S) which are structurally implemented with
functional modules such as registers and arithmetic logic units (ALU’S). These modules
are then geometrically placed onto the chip surface using CAD tools for automatic
module placement followed by routing, with a goal of minimizing the interconnects area
and signal delays. The third evolution starts with a behavioral module description.
Individual modules are then implemented with leaf cells. At this stage the chip is
described in terms of logic gates(leaf cell) , which can be placed and interconnected by
using a cell placement & routing program. The last evolution involves a detailed Boolean
description of leaf cells followed by a transistor level implementation of leaf cells and
mask generation. In standard-cell based design, leaf cells are already pre-designed and
stored in a library for logic design use.

Above Figure provides a more simplified view of the VLSI design flow, taking into
account failure to properly verify a design in its early phases typically causes significant
and expensive re-design at a later stage, which ultimately increases the time-to-market.
Although the design process has been described in linear fashion for simplicity, in reality
there are many iterations back and forth, especially between any two neighboring steps,
and occasionally even remotely separated pairs. Although top-down design flow provides
an excellent design process control, in reality, there is no truly unidirectional top-down
design flow. Both top-down and bottom-up approaches have to be combined. For
instance, if a chip designer defined an architecture without close estimation of the
corresponding chip area, then it is very likely that the resulting chip layout exceeds the
area limit of the available technology. In such a case, in order to fit the architecture into
the allowable chip area, some functions may have to be removed and the design process
must be repeated. Such changes may require significant modification of the original
requirements. Thus, it is very important to feed forward low-level information to higher
levels (bottom up) as early as possible.
In the following, we will examine design methodologies and structured
approaches which have been developed over the years to deal with both complex
hardware and software projects. Regardless of the actual size of the project, the basic
principles of structured design will improve the prospects of success. Some of the
classical techniques for reducing the complexity of IC design are: Hierarchy, regularity,
modularity and locality.

Design Hierarchy

The use of hierarchy, or “divide and conquer” technique involves dividing a module into
sub- modules and then repeating this operation on the sub-modules until the
complexity of the smaller parts becomes manageable. The design of a VLSI chip
can be represented in three domains. Correspondingly, a hierarchy structure can
be described in each domain separately. In the physical domain, partitioning a
complex system into its various functional blocks will provide a valuable
guidance for the actual realization of these blocks on chip. Obviously, the
approximate shape and size (area) of each sub-module should be estimated in
order to provide a useful floorplan. signals (in this case the carry signals) to be
transferred from one sub-block to the other

Concepts of Regularity, Modularity and Locality

The hierarchical design approach reduces the design complexity by dividing

the large system into several sub-modules. Usually, other design concepts and design
approaches are also needed to simplify the process. Regularity means that the hierarchical
decomposition of a large system should result in not only simple, but also similar blocks,
as much as possible. A good example of regularity is the design of array structures
consisting of identical cells - such as a parallel multiplication array.
Modularity in design means that the various functional blocks which make
up the larger system must have well-defined functions and interfaces. Modularity allows
that each block or module can be designed relatively independently from each other,
since there is no ambiguity about the function and the signal interface of these blocks. All
of the blocks can be combined with ease at the end of the design process, to form the
large system.
we effectively ensure that the internals of each module become unimportant
to the exterior modules. Internal details remain at the local level. The concept of locality
also ensures that connections are mostly between neighboring modules, avoiding long-
distance connections as much as possible. This last point is extremely important for
avoiding excessive interconnect delays. Time-critical operations should be performed
locally, without the need to access distant modules or signals.
VLSI Design Styles

Several design styles can be considered for chip implementation of specified algorithms
or logic functions. Each design style has its own merits and shortcomings, and
thus a proper choice has to be made by designers in order to provide the
functionality at low cost.

Field Programmable Gate Array (FPGA)

Fully fabricated FPGA chips containing thousands of logic gates or even more, with
programmable interconnects, are available to users for their custom hardware
programming to realize desired functionality. This design style provides a means
for fast prototyping and also for cost-effective chip design, especially for low-
volume applications. A typical field programmable gate array (FPGA) chip
consists of I/O buffers, an array of configurable logic blocks (CLB’S), and
programmable interconnect structures. The programming of the interconnects is
implemented by programming of RAM cells whose output terminals are
connected to the gates of MOS pass transistors. The largest advantage of FPGA-
based design is the very short turn-around time, i.e., the time required from the
start of the design process until a functional chip is available.

Gate Array Design

In view of the fast prototyping capability, the gate array (GA) comes after the
FPGA. While the design implementation of the FPGA chip is done with user
programming, that of the gate array is done with metal mask design and processing. Gate
array implementation requires a two-step manufacturing process: The first phase, which
is based on generic (standard) masks, results in an array of uncommitted transistors on
each GA chip .

Standard-Cells Based Design

The standard-cells based design is one of the most prevalent full custom design
styles which require development of a full custom mask set. The standard cell is also
called the poly cell. In this design style, all of the commonly used logic cells are
developed, characterized, and stored in a standard cell library. A typical library may
contain a few hundred cells including inverters, NAND gates, NOR gates, complex AOI,
OAI gates, D-latches, and flip-flops. Each gate type can have multiple implementations
to provide adequate driving capability for different fan outs. For instance, the inverter
gate can have standard size transistors, double size transistors, and quadruple size
transistors so that the chip designer can choose the proper size to achieve high circuit
speed and layout density.

Full Custom Design

 Although the standard-cells based design is often called full custom design, in a
strict sense, it is somewhat less than fully custom since the cells are pre-designed for
general use and the same cells are utilized in many different chip designs. In a fuller
custom design, the entire mask design is done anew without use of any library. However,
the development cost of such a design style is becoming prohibitively high. Thus, the
concept of design reuse is becoming popular in order to reduce design cycle time and
development cost. The most rigorous full custom design can be the design of a memory
cell, be it static or dynamic. Since the same layout design is replicated, there would not
be any alternative to high density memory chip design.

APPLICATIONS:

VLSI FOR TELE COMMUNICATIONS

Telecommunication fundamentals

Figure shows a switching network. Lines are the media links. Ovals are called
network nodes. Media links simply carry data from one point to other. Nodes take the
incoming data and route them to an output port.

Figure: Switching network

If two different communication paths intersect through this network they have to
share some resources. Two paths can share a media link or a network node.

Time Division Multiple Access (TDMA)

This simple method consists on multiplexing data in time. Each user transmits a
period of time equal to 1/(number of possible channels) in full bandwidth W. This
sharing mode can be synchronous or asynchronous. These two techniques are used to
connect users. Providing broadcast channels in TDMA can not be done easily. Frequency
Division Multiple Access technique avoids this problem.

Frequency Division Multiple Access (FDMA)

This sharing method consists on giving to each channel a piece of available

bandwidth. Each user transmits over a constant bandwidth equal to W/(number of
possible channels). Filtering with a bandwidth equal to W’ = W/(number of possible
channels) the whole W bandwidth spectrum selects one channel. TV and radio
broadcasters use this media sharing technique

Code Division Multiple Access (CDMA)

Each user transmits using the full bandwidth. Demodulating the whole W band
using a given identification code selects one channel out of the others. Next mobile
phones standard (IS-95 or W-CDMA) uses this media sharing technique. These
techniques can be merged together. For example, the Global System Mobile (GSM =
Natel D) phone standard uses an FDMA-TDMA technique.

Node sharing technique

Node sharing occurs when two communication channels use the same network
node.Before answering this question, we have to define the specification of the switching
function. Next section presents this concept.

Switching function

A switch has N input ports and N output ports. Data come in the lines attached to
the input ports. After identifying their destination, data are routed through the switch to
the appropriate output port. After this stage, data can be sent to the communication line
attach to the output port hardware this canonical switch.

General telecommunication network taxonomy

Telecommunication Networks can be mainly classified into two groups based on

the criteria of who has made the decision of which nodes are not going to receive the
transmitted information. When the network takes the responsibility of this decision, we
have a switching network. When this decision is left to the end-nodes, we have a
broadcast network that can be divided in packet radio networks, satellite networks and
local area networks.

SCOPE:
Our next goal is to size up the present chip designs and integrate them in larger
systems. Since the VLSI designs are fully scalable and parallel, sizing is limited mostly
by budget considerations and fabrication process yield. The projected computational
bandwidth available from such scaled versions is enormous (10 GOPS and larger), while
the energetic efficiency (operations per Joule) remains a factor 100-10,000 better than
general-purpose computer platforms.

CONCLUSION
Our progress on hardware implementations has demonstrated the advantages
of neuromorphic VLSI hardware in efficient computation of highly complex functions in
biological models of vision processing. Our developed systems emulate models of
boundary contour extraction in visual cortex and beyond, encompassing layers of simple
cells, complex cells, hypercomplex cells, and bipole cells, including wide-range
interactions among the several layers. Both multi-chip modules and single-chip solutions
have been demonstrated, interfacing with a digital computer to extend the computational
platform.