FUNCTIONAL VERIFICATION QUESTIONS

(Q i1)Explaino ehowi tooinject qare crc ierroroq jinre a ipacket owhichqhas

justzdatau yande ocrczx fields.
Ans:


Crc ierroro einjecttioni canobe qdonere by imodifyingoq jthere crc ivalue oonly.q
If idatao eisi modifiedoto qinjectre crc ierror,oq jthenre it imay oendqup
inz auysituatione othatzx the new modified packet may have the same crc.

For iexampleo e,i aopacket qofre length i5oq jbitsre with i3 obitsqof dataz andu y2eobitszx of
crc value.
Then ithereo ewilli beo8 qpacketsre of idifferentoq jdata.re There iare oonlyq4
possiblez crcu yvalues.e o
So, iforo eonei crcovalue, qtherere could ibeoq jmorere than ione odataqvalues
whichz areu ycorrect. www.testbench.in

If iyouo emodifyi theodata, qthenre the inewoq jdatare may ihave otheqsame
crczvalue,u ywhiche owillzx not be resulted as crc error.

For ioneo edatai field,othere qwillre one ionlyoq jonere crc ivalue, obyqchanging
thezcrcu yvalue,e ocrczx error will be injected for sure.


(Q i2)o eHowi dooyou qknowre when iverificationoq jcompleted?
Ans: i


Verification iiso eneveri completedoas qperre me. i
I icano eonlyi sayothat qmyre verification itaskoq jisre completed iwhen oIqverified
allz theu ypointse omentionszx in test plan.


(Q i3)o eHowi toodetect qdeadlockre conditions iinoq jFSMsre ?
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i4)o eHowi tooavoid qracere condition ibetweenoq jTestbenchre and iDUT o?www.testbench.in

Ans:


In iverilogo eori VHDL,o
i
1)The iclocko ewhichi isogiven qtore DUT iandoq jTestbenchre should ihave oaqphase
difference.z
2)DUT ishouldo eworki oroposedge qofre clock iandoq jtestbenchre should iworkoonqnegedge
ofz clock.
3)Testbench ioutputo eandi DUTooutput qpinsre should ialwaysoq jbere driven iusingononqbloc
king statements.

In iSV,o e
1)The iaboveo edefinei 3otechniques.
2)Clocking iblocks. www.testbench.in

3)Program iblock.



(Q i5)o eWhati isomutex?
Ans:


A imutualo eexclusioni oroMUTEX qre essential ifunctionoq jisre to imake oitqpossible
forz au ymultiplee oprocesseszx to make use of a single resource.
When iao esinglei resourceois qrequiredre by imultipleoq jprocesses,re MUTEX iwillomakeqsure
thatz onlyu yonee oprocesszx will be granted the access at a time.
For iexample,
A iDUTo ehasi aomemory qtore store itheoq jconfigurationre registers. iTooaccessqthe
memory,z letsu ysay,e oazx protocol is defined to read the memory of one location at a
time. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

Testbench imayo erequirei tooaccess qthere configuration/status/interruptiregistersoq jatre ti
mes ifrom odifferentqplaces. Forz example,u yae omonitorzx is reading register location of
status bit, while the testcase is reading a configuration register.
To iaccesso ethei memory,oTestcase qandre monitor iwilloq jsendre the iaddressoofqthe
locationsz andu yreade ocommand.zx But the DUT can accept only one read request at a
time. www.testbench.in

By iusingo eMUTEX,i accessoto qmemoryre interface icanoq jbere granted ionce oatqa
time,z sou ythee oreadzx operations by monitor and testcases will not collide.

In iSV,o etoi createoa qMUTEX,re construct iaoq jsemaphorere with ione okey.
A ikeyo eisi giveno qtore either imonitoroq jorre testcase ito oreadqoperation
basedzonu ywhoe ocomeszx first. Once the key is returned, other waiting component can take
the key and start its operation.

Some itimes,o ethei keyowhich qisre consumed imayoq jnotre be iretunedowhichqleads
toz deadu ylocke ocondition.zx So if a key is not returned, then a timeout should happen and a
error message should be triggered.


(Q i6)o eWhati isosemaphore?
Ans:


Conceptually, iao esemaphorei isoa qbucket.re When iaoq jsemaphorere is iallocated,oaqbucke
t thatz containsu yae ofixedzx number of keys is created. Processes using semaphores must
first procure a key from the bucket before they can continue to execute. If a specific process
requires a key, only a fixed number of occurrences of that process can be in progress
simultaneously. All others must wait until a sufficient number of keys is returned to the
bucket. Semaphores are typically used for mutual exclusion, access control to shared
resources, and basic synchronization.
www.testbench.in



(Q i7)o eWhati isothe qneedre of iregression?
Ans:


1) iChangeso eini theoRTL q(re development, ienhancementoq jorre bug ifix)omayqcause
existingz functionalityu ytoe obreak.zx
2) iToo ecreatei newoscenarios qbyre giving idifferentoq jseedsre to irandomizationoengine.q


(Q i8)o eWhati isorandomization?
Ans:


It iiso enoti possibleoto qlistre out ieveryoq jpossiblere real itime oscenarioqwhile
verifyingz DUT. .....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

If iweo etryi toolist qoutre the iscenarios,oq jthenre we imay omissqsome
ofz them.uySo,e ousingzx randomization, based on the specification, scenarios are generated
in a randomfashion.
For iexample,o etoi generateoa qpacketre of ilengthoq jwhichre ranges ifrom oq0
toz9,u yine overilogzx {$random()} % 10 should be used.
With ithis,o epacketsi ofolength qarere generated irandomly.oq j www.testbench.in



(Q i9)o eWhati isothe qsignificancere of iseedoq jinre randomization?
Ans:


Seed iiso eusedi toochange qthere sequence iofoq jrandomre numbers igenerated.
The iseedo einitializesi othe qrandomre number igenerator.oq j
All itheo erandomi numbersowhich qarere generated ifromoq jre a iparticularoseedqvalue
canz beu yrecreatede ozx by giving the same seed.

In iouro eregressions,i stimulusogeneration qisre done irandomly.oq jRunningre theicomplete o
regressionqwill generatez sameu yrandome onumberszx if we use same seed.
So iouro eregressioni usesothe qtimere of itestoq jcasere simulation istarted oasqthe
seedz tou yrandome onumberzx generator, with this we are able to generate different stimulus
for each regressions.


(Q i10)o eWhati isothe qdifferencere between icodeoq jcoveragere and ifunctionalocoverage?
Ans: www.testbench.in



Coverage iiso eusedi toocheck qwhetherre the iTestbenchoq jhasre satisfactoryiexercised othe
qdesign orz not?u y
Code icoverageo ewilli giveoinformation qaboutre how imanyoq jlinesre areiexecuted, ohowqm
any timesz expressions,u ybranchese oexecuted.zx This coverage is collected by the simulation
tools. Users use this coverage to reach those corner cases which are not hit by the random
testcases. Users have to write the directed testcases to reach the missing code coverage
areas.

Functional icoverageo e,i byothe qnamere itself i,oq jisre related itootheqfunctionality
ofz theu ydesigne oandzx it is defined by the user. User will define the coverage points for the
functions to be covered in DUT. This is completely under user control.

Both iofo ethemi haveoequal qimportancere in itheoq jverification.re 100 io0.000000unctional
qcoverage doesz notu ymeane othatzx the DUT is completely exercised and vice-versa.
Verification engineers will consider both coverages to measure the verification
progress......w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n




(Q i11)o eIfi CodeoCoverage qisre 100% iandoq jfunctionalre coverage iis onot,qwhat
doesz itu ymeane o?
Ans:


The ireasono ecouldi beoany qonere of itheoq jfollowing. www.testbench.in

1)User ididnoto eexercisei allothe qscenarios.re User ineedoq jtore write itestcasesotoqfill
thez functionalu ycoveragee oholes.
2)There icouldo ebei aobug qinre the ifunctionaloq jcoveragere block iwhich oisqnot
recordingz theu yexecutede oscenario.zx User need to debug to find and fix the issue.


(Q i12)o eIfi Functionalocoverage qisre 100% iandoq jcodere coverage iis onot,qthen
whatz doesu yite omean?
Ans:


1) iIfo etherei isoa qbugre in itestoq jenvironment,re due ito othisqtest
mayz falseuyPass.e oThezx functional coverage will hit due to this false pass but some of the
dut code may not get exercised.
2) iIfo ethei dutois qare legacy icodeoq jre or iIP, oitqmay havez someu yusee olesszxblocks to
support extra functionality. Due to this code coverage will not be 100% achieved.
3) iIno emyi firstocompany, qre there iwasoq jsomere use iless ologicqwhich
didz notuygete oexercised.zx When I approached the RTL designer, he said that fixing this use
less code will break the whole design. So he did not fix it. In this situation , functional
coverage is 100%, but not the code coverage.
4)My ifriendso eexperience,i onceoRTL qdesignerre added iaoq jcodere for iaonewqfeature. z B
ecauseu yofe omisszx communication, my friend didnt know that RTL designer added this new
functionality.
When imyo efriendi didothe qcodere coverage, iheoq jfoundre some iunexercisedologicqwhich
hez didntu yunderstoode oandzx approached RTL designer. Then they figured out that because
of miscommunication, they found a feature in the spec which was implemented, but not
verified.
www.testbench.in

I idonto ethinki ,opoint q2)re can ibeoq javoided.re Point i1), o3)qand
4)z canu ybeeosolved.zx


(Q i13)o eWhati isothe qdifferencere between ipassiveoq jmonitorre and iactiveomonitor.
Ans:


Monitor ireportso ethei protocoloviolation qandre identifies ialloq jtheretransactions. iMonitors
oareqtwo types,z Passiveu yande oactive.zx Passive monitors do not drive any signals, all the
signals are inputs. Active monitors can drive the DUT signals. Sometimes this is also refered as
receiver. Monitor converts the state of the design and its outputs to a transaction abstraction
level so it can be stored in a 'score-boards' database to be checked later on. Monitor converts
the pin level activities in to high level.
.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n



(Q i14)o eIni simulationoenvironment, qunderre what iconditionoq jthere simulationishould oen
d?
Ans:


1) iPacketo ecounti match.
2) iError
3) iErroro ecount www.testbench.in

4) iInterfaceo eidlei count
5) iGlobalo etimeout


(Q i15)o eWhati isoscoreboard?
Ans:


The itermo eSCOREBOARDi isonot qwell-
definedre in itheoq jindustry.re It isometimesorefersqto
thez storageu ydatae ostructurezx only, sometimes it includes the transfer function as well,
and sometimes it includes the comparison function. In vmm methodology, the term scoreboard
is used to refer to the entire dynamic response-checking structure.


(Q i16)o eHowi theotest qcasesre are iincludedoq jinre to isimulation oenvironment?
Ans:


There iareo emultiplei waysoto qdore this. i
Two iveryo esimplei stylesoare qdiscussedre in ibelowoq jlink. Click on the below link
http://www.testbench.in/TB_29_HANDLING_TESTCASE_FILES.html www.testbench.in
HANDLING TESTCASE FILES




A test case is a file that describes an input, action, or event and an expected response, to
determine if a feature of an application is working correctly. A test case should contain
particulars such as test case identifier, test case name, objective, test conditions/setup, input
data requirements, steps, and expected results.

Note that the process of developing test cases can help find problems in the requirements or
design of an application, since it requires completely thinking through the operation of the
application. For this reason, it's useful to prepare test cases early in the development cycle if
possible.


The following example contains testbench environment and has 2 test cases.



EXAMPLE: top.v

module top();
// DUT instance, clock generator and TB components

// some tasks

task write()
begin
// some logic
end
endtask

task read()
begin
// some logic
end
endtask


end

EXAMPLE: testcase_1.v

// Do 10 write operations

EXAMPLE: testcase_2.v

// Do 10 read operations




To test first test cases, We have to simulate the contents of top.v file and testcase_1.v file.

1) Take an instance of module TEST in top.v file. Define the module definition in test cases.

During compilation just use the following commands

for testcase_1.v file
comile_command top.v testcase_1.v

for testcase_2.v file
comile_command top.v testcase_2.v





EXAMPLE: top.v

module top();
// DUT instance, clock generator and TB components

// some tasks

task write()
begin
// some logic
end
endtask

task read()
begin
// some logic
end
endtask

// TEST case instance

TEST tst();

end

EXAMPLE: testcase_1.v

// Do 10 write operations

module TEST();

initial
repeat(10)
top.write();

endmodule
EXAMPLE: testcase_2.v

// Do 10 read operations

module TEST();

initial
repeat(10)
top.read();

endmodule



2) use `include test.v file. This needs a small script to copy the testcase file to test file. The
compilation command is same. But copy command which copies the testcase to test.v file is
different.

During compilation just use the following commands

for testcase_1.v file
cp testcase_1 test.v
comile_command top.v test.v

for testcase_2.v file
cp testcase_2 test.v
comile_command top.v test.v



EXAMPLE: top.v

module top();
// DUT instance, clock generator and TB components

// some tasks

task write()
begin
// some logic
end
endtask

task read()
begin
// some logic
end
endtask

// incule test.v file

`include test.v

end

EXAMPLE: testcase_1.v

// Do 10 write operations

initial
repeat(10)
top.write();


EXAMPLE: testcase_2.v

// Do 10 read operations

initial
repeat(10)
top.read();



2) With the above two approaches, for each test case, we have to do individual compilation. In
this method, compile once and use simulation command to test with individual test case.

This needs a small script to convert all the test cases to single intermediate file. compilation
command is same. During simulation by giving the test case file name, we can include
particular testcase.

During compilation just give following command

cat testcase_1.v > test.v
cat testcase_2.v > test.v
compile_command top.v test.v

During simulation ,
for each test case, use

run_command +testcase_1
run_coomand +testcase_2


EXAMPLE: top.v

module top();
// DUT instance, clock generator and TB components

// some tasks

task write()
begin
// some logic
end
endtask

task read()
begin
// some logic
end
endtask

// incule test.v file

`include test.v

end

EXAMPLE: testcase_1.v

// Do 10 write operations

repeat(10)
top.write();


EXAMPLE: testcase_2.v

// Do 10 read operations

repeat(10)
top.read();



Intermediate file generated contains all the testcase contents with some extra logic as shown.



EXAMPLE: INTERMEDIATE FILE test.v

initial
begin
if($test$plusargs("testcase_1")
begin // testcase_1 contents
// Do 10 write operations
repeat(10)
top.write();
end
if($test$plusargs("testcase_2")
begin // testcase_2 contents
// Do 10 read operations
repeat(10)
top.read();
end
end



(Q i17)o eWhati areothe qdifferentre ways itestcaseoq jarere included iforosimulationsq?
Ans:


1)Compile ionce,o esimulatei multipleotimes qwithre different itestcases:oq j.....w.....w......w......t.
....e.....s.....t......b.....e.....n.....c.....h......i.....n

Compile iTestbencho e+i Allotestcases qatre once iandoq jduringre the isimulation,ousingqthe
$plusargs,z selectu ythee ologiczx of a particular testcase and execute it.
This istyleo eisi suedoin qOVMre and iUVM.oq j
This istyleo eshouldi makeosure qthat,re when itheoq jtestre is iexecutedofromqcommand
line,z u yonlye oTestbenchzx + required testcase should be compiled. Other wise, compiling all
the testcases will consume huge time.
In iregression,o eCompilingi allothe qtestcasesre + itestbenchsoq jatre once iwillosaveqtime.

2)Separate icompilation: www.testbench.in

iCompileo ethei testbenchoonce. qre To irunoq jare testcase, icompile otheqtestcase
,z linku ythee otestcasezx to testbench compiled code and simulate.

3)Compile ionce,o esimulatei once:o
iAllo etestcasesi withosimilar qconfigurationre setting iandoq jtestbenchre areicompiled oonce
qand simulatedz inu yonee osinglezx run. After executing each testcase logic, HARD reset
should be applied to DUT and BFMs, so that the simulation looks as if it started fresh for the
next testcase code.
This istyleo eisi usedoin qVMMre 1.2. ioq jThisre style isaves olotqof timez inuyregressions.

4)Compile ionce,o esimulatei multipleotimes qwithre different idata:oq j
In isomeo everificationi environments,otestcase qcodere doesnt ineedoq jtore beicompiles. oT
estcaseqfile containsz someu ydatae owhichzx is read by testbench to create different
scenarios. Testcase file can be read using $fopen or $plusargs in Verilog.

There icouldo ebei manyomore qwaysre to idooq jthis.re www.testbench.in

If iyouo eknowi somethingowhich qisre not imentionedoq jabovere , iplease otakeqa
minutez tou ymaile oitzx to gopi@testbench.in



.....w.....w......w......t.....e.....s.....t......b.....e.....n.....c.....h......i.....n

(Q i18)o eExplaini howomessages qarere implemented iinoq jyourre testbench?
Ans:


In iVMM/RVM/AVM/OVM/UVM/ERM/Truss&Tealo emethodologies,i omessageqhandlingre logic ii
soq jpredefined.re Use ican ouseqthese predefinedz messageuyservicese oandzx print
messages as required by testbench. If above methodology base classes are not used, then user
can define his own message handling logic.

I ihaveo edefinedi aosimple qverilogre logic, ilookoq jforre Message iControloSystemqtopic
inz theu ybelowe olink Click on the below link
http://www.testbench.in/TB_23_DEBUGGING.html
www.testbench.in



(Q i19)o eWritei codeofor qclockre generator?
Ans:


reg iclk;
initial iclko e=i 0;o
always i#10o eclki =o~clk; q


(Q i20)o eHowi toopass qare value itooq jtestbenchre from icommand oline?
Ans: Click on the below link


http://www.testbench.in/TB_22_COMPILATION_N_SIMULATION_SWITCHS.html
COMPILATION N SIMULATION SWITCHS


Compilation And Simulation Directives:




Conditional Compilation directive switches vs Simulation directive switches

Verilog has following conditional compiler directives.


`ifdef
`else
`elsif
`endif
`ifndef


The `ifdef compiler directive checks for the definition of a text_macro_name. If the
text_macro_name is defined, then the lines following the `ifdef directive are included. If the
text_macro_name is not defined and an `else directive exists, then this source is
compiled. The `ifndef compiler directive checks for the definition of a text_macro_name. If
the text_macro_name is not defined, then the lines following the `ifndef directive are
included. If the text_macro_name is defined and an `else directive exists, then this source is
compiled. If the `elsif directive exists (instead of the `else) the compiler checks for the
definition of the text_macro_name. If the name exists the lines following the `elsif directive
are included. The `elsif directive is equivalent to the compiler directive sequence `else `ifdef
... `endif. This directive does not need a corresponding `endif directive. This directive must
be preceded by an `ifdef or `ifndef directive.



EXAMPLE:
module switches();

initial
begin
`ifdef TYPE_1
$display(" TYPE_1 message ");
`else
`ifdef TYPE_2
$display(" TYPE_2 message ");
`endif
`endif
end
endmodule



Compile with +define+TYPE_1
Then simulate,result is


RESULT:

TYPE_1 message



Compile with +define+TYPE_2
Then simulate,result is



RESULT:

TYPE_2 message



TYPE_1 and TYPE_2 are called switches.

In the above example, When TYPE_1 switch is given, statement " $display(" TYPE_1 message ");
" is only compile and statement " $display(" TYPE_2 message "); " is not compiled.
Similarly for TYPE_2 switch. It wont take much time to compile this small example.
Compilation time is not small for real time verification environment. Compiler takes time for
each change of conditional compilation switches.

Simulation directives are simple. This is archived by `define macros. The following example
demonstrated the same functionality as the above example.



EXAMPLE:

module switches();

initial
begin
if($test$plusargs("TYPE_1"))
$display(" TYPE_1 message ");
else
if($test$plusargs("TYPE_2"))
$display(" TYPE_2 message ");
end
endmodule



No need to give +define+TYPE_1 or +define+TYPE_2 during compilation

Simulate with +TYPE_1


RESULT:

TYPE_1 message




Simulate with +TYPE_2
Then simulate,result is


RESULT:

TYPE_2 message



With the above style of programing,we can save recompilation times.


This system function searches the list of plusargs (like the $test$plusargs system function) for a
user specified plusarg string. The string is specified in the first argument to the system
function as either a string or a register which is interpreted as a string. If the string is found,
the remainder of the string is converted to the type specified in the user_string and the
resulting value stored in the variable provided. If a string is found, the function returns a non-
zero integer. If no string is found matching, the function returns the integer value zero and the
variable provided is not modified.

%d decimal conversion
%o octal conversion
%h hexadecimal conversion
%b binary conversion
%e real exponential conversion
%f real decimal conversion
%g real decimal or exponential conversion
%s string (no conversion)

The first string, from the list of plusargs provided to the simuator, which matches the
plusarg_string portion of the user_string specified shall be the plusarg string available for
conversion. The remainder string of the matching plusarg (the remainder is the part of the
plusarg string after the portion which matches the users plusarg_string) shall be converted
from a string into the format indicated by the format string and stored in the variable
provided. If there is no remaining string, the value stored into the variable shall either be a
zero (0) or an empty string value.




Example


module valuetest();

integer i;
real r;
reg [11:0] v;
reg [128:0] s;

initial
begin
if($value$plusargs("STRING=%s",s))
$display(" GOT STRING ");
if($value$plusargs("INTG=%d",i))
$display(" GOT INTEGER ");
if($value$plusargs("REAL=%f",r))
$display(" GOT REAL ");
if($value$plusargs("VECTOR=%b",v))
$display(" GOT VECTOR ");

$display( " String is %s ",s);
$display(" Integer is %d ",i);
$display(" Realnum is %f ",r);
$display(" Vector is %b ",v);
end

endmodule

Compilation :
command filename.v
Simulation :
command +STRING=rrf +INTG=123 +REAL=1.32 +VECTOR=10101

RESULTS:

GOT STRING
GOT INTEGER
GOT REAL
GOT VECTOR
String is rrf
Integer is 123
Realnum is 1.320000e+00
Vector is 000000010101


(Q i21)o eWhati isotest qplanre ? iWhatoq jitre contains i?
Ans: www.testbench.in
Click on the below link


http://www.testbench.in/TS_24_VERIFICATION_PLAN.html
VERIFICATION PLAN





The Verification Plan is the focal point for defining exactly what needs to be tested, and drives
the coverage criteria. Success of a verification project relies heavily on the completeness and
accurate implementation of a verification plan. A good plan contains detailed goals using
measurable metrics, along with optimal resource usage and realistic schedule estimates.
Verification plan gives an opportunity to present and review the strategy for functional
verification before the verification engineer have gone into detail to implement it. It also
establishes proper communication. Just imagine how it would be working with a multisite
project and you have a query for which you have to wait till the next day to see the answer in
email and they just call you while you are in sleep. It also gives an idea about the areas that
are going to be difficult to verify for taking necessary steps. It is used to determine the
progress and completion of the verification phase of verification. Verification Planning should
start early with system/architecture evaluation phase. Once the functional spec is given to the
verification team, they will start its development.

A verification plan could come in many forms, such as a spreadsheet, a document or a simple
text file. Templates are good if continually used in your company as it makes common
interface for information, reviewer know where to look for certain information even in a huge
document that he wants to know at this moment, because different reviewers want different
infomation in different moments.

Generally Verification plan development is divided in two steps: What to verify and How to
verify?
Step one: What to Verify?
list of clearly defined features-to-verify. This is called feature extraction phase.
Step two: How to Verify?
After defining what exactly need to be verified, define how to verify them.



Verification Plan Contains The Following:



Overview
Resources, Budget and Schedule
Verification Environment
System Verilog Verification Flow
Feature Extraction
Stimulus Generation Plan
Checker Plan
Coverage Plan
Details of reusable components






Overview




This section contains description of the project, what specification is followed, what languages
and methodology are used. Information related to the HW blocks, SW blocks and HW/SW
interaction is outlined.



Feature Extraction




This section contains list of all the features to be verified. Generally each feature is associated
with



1. Unique Name Id
2. Description
3. Expected result
4. Pointer to the specification
5. priority.




The "Unique name ID" should be descriptive in nature to understand the nature of the feature
and should be unique. For example, <module name>_<sub module>_<feature
number>_<feature name>

Some points on how extraction the features:
Read the MRD, System Specification, Macro and Micro Hardware Specification.
Go through the designer notes/presentations.
Annotate each line/paragraph specifying a functional item e.g., read/write a register
Annotate each line/paragraph specifying a multiple-functional items e.g., steps required to
set and cause an interrupt .
Identify all RTL configurations
Identify interfaces and related protocols across interface.
Identify standards compliance requirements, list corner cases.
Create a list of illegal scenarios to verify.
Create a list of exceptions to verify.
Create a list of operation sequences to verify e.g., interrupt followed by breakpoint etc.
Create a list of things to try and break the machine.
Take advantage of existing plans.
Use points from compliance checklist for standard protocols.
Get information about the Common tests for all chips.
Get review by a number of people, usually very experienced engineers. Better if you get
reviewed by Architects, micro Architects, Leads, verification engineers, RTL Designers,
software designers, marketing team and other team members.



Resources, Budget And Schedule




This section contains details of man power required and schedule for each phase of the
verification. Information about the tools which are used for simulation, debugger and bug
tracking are listed.



Verification Environment




A detailed TestBench architecture is essential for a robust verification environment. In this
section describe the topology, about each component of the TestBench, special techniques
that are used, IPs, Reused blocks, new blocks, and guidelines on how to reuse the TestBench
components. For example if you think upfront about error injection, configuration, component
communication, callbacks etc, you can provide hooks to do those.



System Verilog Verification Flow




Details about each level (block, sub-system, system) and phases (RTL, gate) of verification are
mentioned.



Stimulus Generation Plan




The stimulus generation section contains information about different types of transactions,
sequences of transactions and various scenarios generated as per the specification.

Each point is associated with




1. Unique name ID
2. Stimulus to be generated for driving into the DUT
3. Configuration/constraints Information



Checker Plan




This section will explain the expected result checking's in the TestBench. This can be done in
monitor/checker.

Various fields associated with each of the point are:



1. Checker Unique name
2. Unique Feature ID(Defined in Feature plan)
3. Checker Description


Coverage Plan




The coverage section explains the functional coverage of the features. A functional coverage
plan should be built to help implement coverage points in the verification environment.
Genarally it would be better if the coverage block is brocken based on the design logical
blocks. It will list the various Coverage groups and assertion.

Various fields of the coverage plan section are:



1. Coverage Group
2. Coverage Description
3. Coverage name
4. Unique name ID (Defined in feature plan)
5. Cover point (Items/cross/transition/assertion)
6. Coverage goal


Details Of Reusable Components




This section contains the details of reusable components and the description about their
usage.


(Q i22)o eExplaini someocoding qguidelinesre which iyouoq jfollowedre in iyouroenvironment? .
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(Q i23)o eExplaini aboutowhite qbox/blockre box iandoq jgrayre box itesting.
Ans: Click on the below link


http://www.testbench.in/TB_34_WHITE_GRAY_BLACK_BOX.html
WHITE GRAY BLACK BOX


Black Box Verification




Black Box verification refers to the technique of verification if system with no knowledge of
the internals of the DUT. Black Box testbench do not have access to the source code of DUT,
and are oblivious of the DUT architecture. A Black Box testbench, typically, interacts with a
system through a user interface by providing inputs and examining outputs, without knowing
where and how the inputs were operated upon. In Black Box verification, the target DUT is
exercised over a range of inputs, and the outputs are observed for correctness. How those
outputs are generated or what is inside the box doesn't matter.



White Box Verification



In White box verification, testbench has access to internal structure of DUT. This makes the
testbench environment reuse less. This is not much preferred in the industry.



Gray Box Verification



Gray box verification, the name itself Conway that testbench has access to some part of the
DUT.