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4
1
2
1
C
2
C
3
C
Vdc/3
2Vdc/3
(2)
(1)
SCEECS 2014
DC link voltage Vdc : 300 Volts
C1-C2-C3 : 3300F
Switching frequency : 10 kHz
Filter inductor : 5mH
Filter capacitor : 2F
Filter damping resistor : 2
For modulation index greater than 0.66, the phase angle
displacement is determined by
1
1
1
2
3 2
4 1
sin
sin
2
c
m
c
m
A
A
A
A
=
=
=
=
(2)
The switching pattern adopted in the proposed inverter, and
the output voltage levels according to the switch on off
conditions is as shown in Fig. 6. It also shows the five regions
that makes up one half cycle of the inverter output. Fig. 7
shows the decision signals produced by the comparators .C1
represents the comparison output between
ref1
V and
carrier
V .
C2 represents comparison output between
ref2
V and
carrier
V and C3 represents comparison output between
ref3
V
and
carrier
V . The gating signals are constructed by adding
portions of the PWM decision signals produced by the
comparators together through appropriate logic gates. From
Table I, the gating signals for high frequency switches can be
derived to match the output voltage level shown in Fig. 6.
Having the three comparator outputs and the output regions
defined it is possible to define the switching signal for each
high frequency switch. The PWM signals for all the six
switches are as shown in Fig. 8. The gating signal for output
polarity generator stage, which changes the polarity of inverter
output voltage, is simple. Low-frequency output polarity
generator works in two modes: forward and reverse modes. In
forward mode, switches
7
S and
8
S are ON generating positive
polarity output. In reverse mode switches
9
S and
10
S will be
ON generating negative polarity output. The switching function
of Fig. 8 are given by
1
S =
3 3
R C (3)
2
S =
1
S
3
S =
3 3 4 2 2
) ( R C R R C + +
4
S = ) (
5 4 2 1 2
R R R R C + + +
5
S = ) ( ) (
4 2 2 5 1 1
R R C R R C + + +
6
S = ) (
5 1 1
R R C +
Where + is a logical OR, is a logical AND and -
is logical inverse (NOT). The overall efficiency of converter is
dependent on the number of switches involved in producing
each voltage levels. In a seven-level cascaded topology six
switches conduct the inverter current at every instance.
However, in the proposed topology the number of switches
which conduct current ranges from three switches (for
generating level 3) to five switches conducting for other level,
while two of the switches are from polarity generator of the
inverter. Therefore, the number of switches that conduct
current in the proposed topology is lower than that of the
cascade inverter that reduces the switching losses and hence it
has a better efficiency.
IV. SIMULATION RESULTS
In order to verify the proposed inverter topology and the
PWM switching pattern, simulations are performed by using
MATLAB/SIMULINK. An output LC filter is used to remove
the remove high frequency switching ripples and the design of
filter components is done in the same way of tuning filter
values as given in [9]. The resonance frequency is considered
to be 30 times the line frequency (50 Hz). The PWM switching
signals are generated by comparing three reference signals
against a triangular carrier signal. The multilevel inverter
specification and its associated parameters are as shown in
Table III.
TABLE III
MULTILEVEL INVERTER SPECIFICATIONS
The waveform of the proposed multilevel inverter with an
output filter and a series R-L load of 150 and 30mH
respectively are shown in Fig. 9.
Fig. 9. From top: Output voltage of level generator (100 V/div), output
voltage (200 V/div) and output current (1 A/div) for Ma=0.8.
Fig. 10. Current waveform THD for seven levels of output voltage of Fig. 9.
(4)
(5)
(6)
(7)
(8)
SCEECS 2014
Fig. 11 corresponds to modulation index (
a
M ) between
0.33 and 0.66. In this range, only
ref1
V and
ref2
V gets
compared with the triangular carrier wave which results in the
generation of output voltage having only five levels.
Fig. 11. From top: Output voltage of polarity generator (100 V/div), and
output current (0.5 A/div) for Ma=0.6.
Fig. 12. Current waveform THD for five levels of output voltage of Fig. 11.
For modulation index (
a
M ) less than 0.33, only
ref1
V will
be compared with the triangular carrier wave which results in
the generation of output voltage having only three levels as
shown in Fig. 13.
Fig. 13. From top: Output voltage of polarity generator (50 V/div), and output
current (0.25 A/div) for Ma=0.2.
Fig. 14. Current waveform THD for three levels of output voltage of Fig. 13.
Comparing the THD values of the current for three different
modulation index shows that the THD reduces with the
increase in number of output voltage levels.
V. CONCLUSION
In this paper a new inverter topology which has superior
performance, offering improved output waveforms and lower
THD over conventional topology in terms of number of
switches required, cost, control system and reliability. The
number of power semiconductor switches required for the
proposed inverter is same as RV topology. However the
number of current conducting switches for generation of level
2 and level 3 is lesser than the RV topology results in improved
performance of the inverter proposed, in terms of its efficiency.
The operating principles and the switching functions are
analyzed. The complexity of PWM for this topology is low
since it only needs to generate gating pulses for generation of
positive level only. The inverter generates a 7-level output
waveform for modulation index above 0.66, a 5-level output
waveform for modulation index between 0.33-0.66, and a 3-
level output waveform for modulation index less than 0.33.
The results obtained clearly shows the effectiveness of the
proposed topology as a multilevel inverter with reduced
number of switches and carriers for PWM.
ACKNOWLEDGMENT
The authors would like to thank the authorities of VNIT,
Nagpur for providing facilities to carry out the research work.
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