Relatório Do Projeto de MT - Bruno Mariana Federica

Microelectronics Telecommunications
Project Front-End Receiver"

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Masters in Electronics Engineering, N66004, N66020 and N77855 School Year 2013/20114
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I IN NS ST TI IT TU UT TO O S SU UP PE ER RI IO OR R T T C CN NI IC CO O T TA AG GU US SP PA AR RK K
S SC CH HO OO OL L Y YE EA AR R 2 20 01 13 3/ /2 20 01 14 4, , 1 1 S SE EM ME ES ST TE ER R

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MI IC CR RO OE EL LE EC CT TR RO ON NI IC CS S
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TE EL LE EC CO OM MM MU UN NI IC CA AT TI IO ON NS S

F FR RO ON NT T- -E EN ND D R RE EC CE EI IV VE ER R

T Te ea ac ch he er r: : J Jo o o o V Va az z ( (R Re es sp po on ns si ib bl le e) )

Masters in Electronics Engineering:
Bruno Guilherme, N66004
Mariana Daniel, N 66020
Federica Pelli, N77855

January 17, 2014
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INDEX
1. INTRODUCTION ..............................................................................ERRO! MARCADOR NO DEFINIDO.
2. LOW NOISE AMPLIFIER (LNA) .......................................................................................................... 3
2.1 SPECIFICATIONS LNA ...................................................................................................................... 3
2.2 SCHEMATIC LNA ............................................................................................................................. 3
2.3 LAYOUT LNA .................................................................................................................................. 5
2.4 SIMULATION RESULTS OF LNA ........................................................................................................ 6
2.4.1 INPUT AND OUTPUT MATCHING, NOISE FIGURE, TRANSDUCER AND AVAILABLE GAINS .................... 6
2.4.2 1-DB COMPRESSION POINT AND THIRD ORDER INTERMODULATION DISTORTION .............................. 8
2.4.3 (2.4.1) WITH CORNERS AND MONTE-CARLO SIMULATION ............................................................... 9
2.4.4 (24.1) WITH POST-LAYOUT SIMULATIONS ...................................................................................... 10
3. VOLTAGE-CONTROLLED OSCILLATOR (VCO) ............................................................................... 11
3.1 SPECIFICATIONS VCO .................................................................................................................... 11
3.2 SCHEMATIC VCO ........................................................................................................................... 11
3.3 LAYOUT VCO ................................................................................................................................ 12
3.4 SIMULATION RESULTS OF VCO ..................................................................................................... 13
3.4.1 VCO ONSET AND STEADY-STAGE OUTPUT VOLTAGE IN THE TIME DOMAIN .................................... 13
3.4.2 VCO STEADY-STAGE OUTPUT VOLTAGE, POWER AND PHASE-NOISE ............................................. 14
3.4.3 VCO OUTPUT FREQUENCY AND POWER INSIDE THE TUNING RANGE .............................................. 15
4. MIXER ............................................................................................................................................... 17
4.1 SPECIFICATIONS MIXER ................................................................................................................. 17
4.2 SCHEMATIC MIXER ...................................................................................................................... 117
4.3 LAYOUT MIXER ............................................................................................................................. 18
4.4 SIMULATION RESULTS OF MIXER ................................................................................................... 19
4.4.1 LO-RF AND LO-IF ISOLATIONS, AND LO INPUT IMPEDANCE (PSS ANALYSIS) ............................... 20
4.4.2 POWER, AVAILABLE AND TRANSDUCER CONVERSION GAINS, RF AND IF PORTS INPUT IMPEDANCES
(PSS+PSP ANALYSIS) .................................................................................................................................... 20
5. FINAL RECEIVER ............................................................................................................................... 23
5.1 SIMULATION RESULTS OF FINAL RECEIVER .................................................................................... 23
5.1.1 OVERALL POWER, AVAILABLE, TRANSDUCER AND VOLTAGE CONVERSION GAINS ........................ 24
5.1.2 INPUT IMPEDANCE AND REFLECTION COEFFICIENT ........................................................................ 25
5.1.3 ADJACENT CHANNEL AND IMAGE FREQUENCY REJECTION ............................................................ 25
5.1.4 COMPLETE NOISE FIGURE .............................................................................................................. 26
5.1.5 OVERALL AND INDIVIDUAL BLOCKS POWER CONSUMPTION ........................................................... 26
6. LIST OF FIGURES ............................................................................................................................. 227
7. CONCLUSION ..................................................................................................................................... 29

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1. INTRODUCTION
In order of discipline Microelectronics Telecommunications, proposed the creation
of a project aiming to develop a Receiver Front-End. The proposed receiver consists of
a low noise amplifier (LNA) a voltage controlled oscillator (VCO), and a mixer. An RF
input signal will be down converted to an intermediate frequency output signal.
The technology used in this project is the CMOS C35B4C3 Austria Microsystems
(AMS). This is a manufacturing process suitable for the realization of circuits with few
GHz frequencies. For this project, one has a series of specifications that must be
followed to perform the Receiver. Among the various specifications, the input
frequency FRF is one of them, which to our working group was proposed value of 3.5
GHZ.
This project is divided into four main parts, LNA development, VCO development,
Mixer development and finally the complete development of the Receiver. Each major
step is divided in making the schematic layout of the realization and implementation of
appropriate simulation tests.
Along the report we will present the explanations necessary for the understanding of
the various stages of the project with the final objective of understanding the
development of Receiver Front-End.

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2. LOW NOISE AMPLIFIER (LNA)

The LNA is one of the first stages of the receiver system and its role and position in
the receive chain specifically define their design criteria. In general, knowing that the
entire circuit generates some form of noise, the primary function of the LNA amplifying
the received signal is adding little noise as possible so that it can be properly processed
in the following stages, and meets the requirements of the signal to noise ratio for
decoding the modulation scheme used.

2.1 SPECIFICATIONS - LNA

In the first phase of the project, the objective is to develop a low-noise amplifier to
operate at a frequency of 3.5 GHz.
For the realization of the LNA, beyond the proposed working frequency (3.5 GHz) to
the group, some specifications were required for their implementation. Figure 1, shows
the specifications imposed for work. In relation to the size of input transistor, through
the table provided by the teacher with assignments for each respective group, was
proposed a value of 5 micrometers.
This architecture has two floors, on the first floor consists of an assembly of the
transistor in common source inductive degeneration and is recognized in the literature as
the most suitable for low noise amplifiers tuned. It is well recognized by allowing the
best performance with respect to noise added.

Figure 1 - Specifications of LNA.

2.2 SCHEMATIC - LNA

One of the first block is found in a Receiver is a low noise amplifier - LNA.
Its function is to amplify the input signal to the mixer. This part of the project,
completion of the LNA, is critical because it must provide enough gain to low levels of
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power arriving at the receiving antenna, inserting the minimum possible noise power to
the signal such that the signal-to-noise ratio (SNR) is not degraded, and should also be
able to sustain large signals with low distortion and low power consumption. As a step
before the LNA is typically an antenna, there is a need to combine the input impedance
of a specific value in this case was 50 to ensure maximum power transfer.

So the schematic of the LNA requires several appointments:
- Designed to the output stage so as to obtain input impedance set at the maximum
value;
- Care was taken with the power gain and maximized up as was possible;
- Obtained the size of the input transistor and the bias point to coincide with the input
of LNA and minimized noise;
- Maximized power to the LNA, the gain and the gain available transducer.

This way, in sum, the design of low noise amplifier requires an agreement between
the sufficient gain, low noise, "marriage" in the input and output, high linearity and low
power consumption.
Then in Figure 2 shows the schematic design to the appropriate LNA and Figure 3
shows the respective symbol.

Figure 2 - Schematic of LNA.
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Figure 3 - Symbol of LNA.

2.3 LAYOUT - LNA

Layout is one of the most important steps in the design of an integrated circuit. In
fact, it is the layout of the circuit that leads to a set of masks that will be manufactured.
Thus, a poorly designed layout can prevent the use of LNA in the receiving chain, due
to a number of factors: errors present in the representation of certain electrical
components, significant deviations in the operation of the device due to the existence of
parasitic. But fortunately there are simulators whose purpose is to ensure that the layout
is designed appropriately the desired circuit. Along the layout low noise amplifier,
design certain precautions were taken, and some key goals were outlined, such as:

To minimize the parasitic effects of internal connections;
All electrical connections between the LNA and the outside world must be
made using frame pads.

Then in Figure 4 is shown the respective LNA design the layout.

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Figure 4 - Layout of LNA.

2.4 SIMULATION RESULTS OF LNA

The amplifier features for simulation, adapting the input and output, a gain of
21dB, good insulation and noise factor of about 4.6 dB at the desired frequency. It
should be noted that good insulation is achieved through the use of a cascode transistor
and the noise factor is mainly determined by the noise generated by the main transistor
and the resistance of the coil connected to the door.
The simulations also show the suitability of CMOS technology for the
implementation of low-noise amplifiers. Results obtained through simulations validate
the LNA design and show that the project objectives were partly achieved because the
LNA presents satisfactory compared to the list of specifications submitted.
When compared to other projects LNA's, it is observed that the strengths of
LNA designed are: low power consumption, the use of a few inductors, the possibility
of using other loads and high linearity.

2.4.1 INPUT AND OUTPUT MATCHING, NOISE FIGURE, TRANSDUCER
AND AVAILABLE GAINS
One of the main specifications of an LNA is the Noise Figure. Figure Noise
measures the amount of noise added to the signal circuit. Noise is an unwanted signal
that appears added to the desired signal and is random in nature, causing changes in
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signal going through a circuit or transmission medium. The main sources of noise in
integrated circuits are transistors and resistors.
In these projects we use the Noise Figure as a parameter to characterize the
performance of the circuit. This parameter corresponds to the noise factor expressed in
dB, which is a measure of the degradation of the signal to noise ratio (SNR), when an
electrical signal passes through a given circuit. It is this parameter that can determine
the sensitivity of the system.
In an RF receiver, all components (LNA, filters, mixers, etc.) contribute to the
increase of noise in the system, so you must calculate the Noise Figure of cascaded 'n'
blocks. Is the LNA, for being the first block, which must make a compromise between
minimizing the Noise Figure and increased gain in the block, since the latter also
contributes to noise reduction the following stages.
This simulation serves to test whether the LNA promotes a sufficient gain, without
much harm signal to noise ratio (explained above) and low distortion. Moreover, it also
requires impedance matching at the input and output (usually 50 ) to ensure maximum
power transfer. So in this simulation the goal is to require a compromise between
sufficient LNA gain, low noise figure, impedance matching input and output, high
linearity and good reverse isolation.

Figure 5- Simulation of impedance matching input and output.

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2.4.2 1 DB COMPRESSION POINT AND THIRD ORDER
INTERMODULATION DISTORTION

The point of 1 dB compression is a parameter that is defined as the level of the input
signal causing a reduction of 1 dB in the output signal relative to the ideal response
curve, which represents a fundamental view on the previous item. To find this point, it
is sufficient to extrapolate the fundamental and verify the extent that the difference
between the actual and extrapolated curve corresponds to 1dB, as in the Figure 8:

Figure 8 - Simulation of 1 dB compression point.
Figure 6 - Simulation of noise figure. Figure 7 - Simulation of transducer and available gains.

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On systems with limited band width normally you cannot measure the harmonic
distortion, because the harmonics can be out of the frequency range , thus the distortion
in the output appears very small , even if the input stage introduces a big "no linearity " .
One way to solve this problem is by testing and measuring intermodulation distortion.
For this reason it is a test which applies two close frequencies at the input of LNA
allowing frequency components in the vicinity of the pass band of the system. The
frequency of these components is called an intermodulation product (IM).
In the case of the LNA, the LNA used for example in cellular networks where there
is present adjacent to the desired channel antenna channels appear a product of third
order intermodulation (IM3) in the band of interest channel.
A parameter that characterizes this influence is called the point of third order
intercept (IP3). In this case , the test was done by analyzing the input and output signals
that vary with the amplitude of the input signal, one comes to a logarithmic graph (Input
dBm x Output dBm) where you can check different inclinations to the fundamental and
the intermodulation product of third order, as shown in Figure 9:

Figure 9 - Simulation of third order intermodulation distortion.

2.4.3 (2.4.1) WITH CORNERS AND MONTE-CARLO SIMULATION

Then simulations of Corners and Monte Carlo are presented respectively. The data
obtained were analyzed and concluded that were expected.
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Figure 10 - Simulation of Corners.

Figure 11 - Simulation of Monte Carlo.

2.4.4 (2.4.1) WITH POST-LAYOUT SIMULATIONS

With the Layout completed, the simulation was carried out due to evidence that the
LNA is manufactured correctly. Next, the post-layout simulation which shows a very
satisfactory analysis is presented. Although this simulation has shown some differences
in the results due to parasitic effects, the truth is that the simulation showed many
similarities to the simulation performed in 2.4.1.

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3. VOLTAGE-CONTROLLED OSCILLATOR (VCO)

3.1 SPECIFICATIONS - VCO

In a second phase of the project, the goal is to develop a voltage controlled Oscillator
- VCO. A voltage controlled oscillator is an oscillator whose frequency generated can
be controlled by varying the voltage. Among various topologies presented, the VCO
ring will focus in this work because of its simplicity and its wide tuning range. The
VCO ring consists of an odd number of inverters connected in series, forming a ring.
First a set of specifications for the design of the VCO were defined:
Frequency of output signal: + / - 50MHz;
Voltage signal output: 0V to 3.3V.
Dimension of transistors: 10 micrometers.

3.2 SCHEMATIC - VCO

This VCO design, basically consisted of connected inverters and control structures
inserted between each inverter. Each control structure consisted of a NMOS transistor in
series with a capacitor. The control voltage of the VCO enters the gate of each NMOS
transistor control structures. Thus, by varying the control voltage can be varied between
each drive the load, thereby varying the delay of each inverter, finally varying the
oscillation frequency of the VCO.
To meet a requirement of the mixer were added to each of the outputs of the two
VCO library components but in order to serve as a buffer, allowing the voltage of the
output signal would meet the specifications of the VCO and varied from 0V to 3.3 V.
Another reason for the addition of these buffers is the need to isolate the VCO and to
prevent its operation was dependent circuit connected to it.
During the preparation of the VCO design, it was found that the parasitic
capacitances considerably degraded circuit performance. A strategy to try to reduce
these parasitic capacitances was the design of the VCO has only 5 steps closer inverters
and components as much as possible, reducing the length and width of paths and
consequently , reducing parasitic capacitances .
The schematic of the VCO is shown below in the Figure 12, in which it is possible to
observe the VCO together with two connected components at each of its two outputs to
act as buffers.
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To achieve the schematic was taken into attention some important steps:
Choose the local oscillator frequency with a lower value than the RF
frequency;
Include buffer stages at both outputs and DC decoupling capacitors;
Assume the mixer LO input port differential impedance is 10k // 135fF;
Use the technology varactors to give the oscillator a tuning capability of at
least 50MHz.

Figure 12 - Schematic of VCO.

Figure 13 - Symbol of VCO.

3.3 LAYOUT - VCO

Through all the proper schematic and basic simulations, we moved on to the Layout
implementation referring to the block oscillator (VCO). It is shown below in Figure 14
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the Layout respective to the VCO, and later in the following chapter the simulation
proves that the proper construction of the layout is shown.

Figure 14 - Layout of LNA.

3.4 SIMULATION RESULTS OF VCO

Then the elaborate simulations are presented to demonstrate the functioning of VCO
projected.

3.4.1 VCO ONSET AND STEADY-STAGE OUTPUT VOLTAGE IN THE
TIME DOMAIN

The following simulation demonstrates the good start of the oscillator.

Figure 15 - Simulation of onset and steady-stage output voltage in the time domain.
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3.4.2 VCO STEADY-STAGE OUTPUT VOLTAGE, POWER AND PHASE-
NOISE

The first phase of this simulation shows the output spectrum for the central frequency
of the project which is 3.5 GHz.

Figure 16 - Simulation of steady-stage output voltage for central frequency.

The following simulation shows the power for the center frequency.

Figure 17 - Simulation of Power for central frequency.

Finally, for this stage presents the phase noise corresponding to the center frequency
graph.
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Figure 18 - Simulation of Phase-Noise for central frequency.

3.4.3 VCO OUTPUT FREQUENCY AND POWER INSIDE THE TUNING
RANGE

The first simulation applied at this stage is related to the variation of the signal
obtained with the Vtune and then with frequency.

Figure 19 - Simulation of variation with Vtune and then with frequency.

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The following simulation shows the variation for power with VTune.

Figure 20 - Simulation of variation Power vs Vtune.

VCO phase noise is a key parameter in the voltage controlled oscillator used for
applications including use in frequency synthesizers for radio receivers, transmitters and
RF signal generators. VCO phase noise is a key specification parameter for any VCO
design as the phase noise performance of a VCO will affect the overall performance of
the system in which the oscillator is located.
Then the last stage of this simulation, with regard to the phase noise is found by the
spacing of the lines to for example the frequency of 1 MHz (mark placed on the chart).
The phase noise displayed has a value of 2dBc / Hz.

Figure 21 - Simulation of phase noise for Vtune.
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4. MIXER

4.1 SPECIFICATIONS - MIXER

In a third step of this project, the goal is the electrical design of the mixer in terms of
both schematic and layout as the level of simulations required. To elaborate the Mixer
had as starting the choice of circuit topology. The topology chosen by the teacher was a
cell Gilbert classic, with capacitive degeneration so as to increase the conversion gain.
This circuit is a double-balanced (as seen in Figure 5), or has a higher common mode
rejection and intermodulation products from the LNA. This type of circuit consumes
twice the power of a single-balanced mixer. Furthermore, the double-balanced mixer
output load of the LNA and the VCO (which is responsible for main control transistors
of the mixer) with twice the parasitic capacitance of a single-balanced mixer of the same
dimensions.

Figure 22 - Circuit Double-balanced mixer.

Then, the circuit parameters were calculated and optimized through simulation.
C35B4C3 the AMS parameters were used for this, as mentioned in the specification.

4.2 SCHEMATIC - MIXER
Unlike what is done for the LNA, an optimization technique developed for that good
results are achieved when designing the mixer is generally not required. This is due to
the fact that there is concern minimize noise, since the presence of a high gain LNA and
optimized gives us great scope for degradation. The major goals in designing the mixer
were maximize linearity, minimize power consumption and minimize capacitive loads
presented to the LNA and VCO.
For successful delivery schematic is shown in Figure 23 took into account the
previously mentioned, but also followed some important steps, which are:
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Assure that all transistors bias points are in the saturation region;
Maximize the conversion gain for the available LO power;
Each mixer output port will have one pad and one bondwire that should be
considered in the design.

Figure 23 - Schematic of Mixer.

Figure 24 - Symbol of Mixer.

4.3 LAYOUT - MIXER

In this part shall quote the techniques used to perform the layout of the mixer. The
goal is to have a good connection between the device instances. Since this is a
differential circuit, the two branches of the circuit are identical.
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Then in Figure 25 is shown the layout of the mixer. In Layout various techniques
were employed.

Figure 25 - Layout of Mixer.

4.4 SIMULATION RESULTS OF MIXER

This section will present the results of the extracted circuit. The differences between
the results obtained in the electrical design and obtained the extracted circuit are due to
parasitic agents of the circuit. For example the parasitic capacitances are responsible for
reducing the gain at high frequencies. Other changes occur due to ohmic differences
may even create offset voltages in differential outputs.
The design of the mixer presented a power consumption of 1.34 mW. Analyzing the
expected values and comparing them with the results obtained, it is correct to say that
the behavior of mixer designed portrays what was physically expected. Mixers with
higher earnings have a lower performance in linearity. To increase the conversion gain
and improve the performance of linearity, the power consumption of the circuit must be
increased. Below are presented in sections, the simulations are necessary to prove the
performance of the mixer.
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4.4.1 LO-RF AND LO-IF ISOLATIONS, AND LO INPUT IMPEDANCE
(PSS ANALYSIS)

The first simulation is done through a pss analysis and as can be seen from the
simulations were then performed well yielding the expected results.

Figure 26 - Simulations of isolation with pss analysis.

4.4.2 POWER, AVAILABLE AND TRANSDUCER CONVERSION GAINS, RF
AND IF PORTS INPUT IMPEDANCES (PSS+PSP ANALYSIS)

The following quote is referring to the power, profits and even to ports input
impedance by pss analysis and analysis psp.

Figure 27 - Simulation of Power.
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Figure 28 - Simulation of Available Gain.

Figure 29 - Simulation of Transducer Gain.

Figure 31 - Simulation of ZM2 (IF port input impedance).

Figure 30 - Simulation of ZM1 (RF port input impedance).

22

Figure 32 - Simulation of S11 and S22 parameters.

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5. FINAL RECEIVER

This final phase of the project is to bring together the previously designed blocks
(LNA, VCO and Mixer) in a single block. That is, the following schematic shows the
three blocks that constitute our final receiver. For this schematic some adjustments were
necessary, but nothing complicated.
It was taken in creating a small concern due to the respective Layout of receiver
should be placed inside a rectangular frame of pads. Padscenters should be 120um
apart from each other.

Figure 33 - Schematic of Final Receiver: Symbol LNA, Symbol VCO and Symbol Mixer.

5.1 SIMULATION RESULTS OF FINAL RECEIVER

Given for completion of the drafting of the three blocks that constitute the ront-End
Receiver has gone up due to the simulations prove that the performance of the Receiver.
The simulations performed for the final Receiver of the genre simulations were made to
the Mixer block.

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5.1.1 OVERALL POWER, AVAILABLE AND TRANSDUCER GAINS
(PSS+PSP ANALYSIS)

Figure 36 - Simulation of Transducer Gain.

Figure 34 - Simulation of Power Gain.

Figure 35 - Simulation of Available Gain.

25
5.1.2 INPUT IMPEDANCE AND REFLECTION COEFFICIENT (PSS+PSP
ANALYSIS)

5.1.3 ADJACENT CHANNEL AND IMAGE FREQUENCY REJECTION
(PSS+PSP ANALYSIS)

Figure 39 - Simulation of adjacent channel and image frequency rejection concerning the available gain.
Figure 37 - Simulation of input impedance.

Figure 38 - Simulation of reflection coefficient (S11 and S22).

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5.1.4 COMPLETE NOISE FIGURE (PSS+PSP ANALYSIS)

Figure 40 - Simulation of Noise Figure.

5.1.5 OVERALL AND INDIVIDUAL BLOCKS POWER CONSUMPTION
(TRAN ANALYSIS)

This last simulation was performed with the support of the transient analysis.
Through this analysis, we calculated the values of the power consumption of each block
individually. Then, with the individual calculation of the three blocks calculate the value
of the total power circuit. Then the calculated values are presented.

Power consumption of LNA: 147.84 mW
Power consumption of VCO: 33 mW
Power consumption of Mixer: 154.11 mW
Power consumption of Receiver Front-End: 334.95 mW

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6. LIST OF FIGURES

Figure 1 - Specifications of LNA. (Page 3)
Figure 2 - Schematic of LNA. (Page 4)
Figure 3 - Symbol of LNA. (Page 5)
Figure 4 - Layout of LNA. (Page 6)
Figure 5- Simulation of impedance matching input and output. (Page 7)
Figure 6 - Simulation of noise figure. (Page 8)
Figure 7 - Simulation of transducer and available gains. (Page 8)
Figure 8 - Simulation of 1 dB compression point. (Page 8)
Figure 9 - Simulation of third order intermodulation distortion. (Page 9)
Figure 10 - Simulation of Corners. (Page 10)
Figure 11 - Simulation of Monte Carlo. (Page 10)
Figure 12 - Schematic of VCO. (Page 12)
Figure 13 - Symbol of VCO. (Page 12)
Figure 14 - Layout of LNA. (Page 13)
Figure 15 - Simulation of onset and steady-stage output voltage in the time domain.
(Page 13)
Figure 16 - Simulation of steady-stage output voltage for central frequency.
(Page 14)
Figure 17 - Simulation of Power for central frequency. (Page 14)
Figure 18 - Simulation of Phase-Noise for central frequency. (Page 15)
Figure 19 - Simulation of variation with Vtune and then with frequency. (Page 15)
Figure 20 - Simulation of variation Power vs Vtune. (Page 16)
Figure 21 - Simulation of phase noise for Vtune. (Page 16)
Figure 22 - Circuit Double-balanced mixer. (Page 17)
Figure 23 - Schematic of Mixer. (Page 18)
Figure 24 - Symbol of Mixer. (Page 18)
Figure 25 - Layout of Mixer. (Page 19)
Figure 26 - Simulations of isolation with pss analysis. (Page 20)
Figure 27 - Simulation of Power. (Page 20)
Figure 28 - Simulation of Available Gain. (Page 21)
Figure 29 - Simulation of Transducer Gain. (Page 21)
Figure 30 - Simulation of ZM1 (RF port input impedance). (Page 21)
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Figure 31 - Simulation of ZM2 (IF port input impedance). (Page 21)
Figure 32 - Simulation of S11 and S22 parameters. (Page 22)
Figure 33 - Schematic of Final Receiver: Symbol LNA, Symbol VCO and Symbol
Mixer. (Page 23)
Figure 34 - Simulation of Power Gain. (Page 24)
Figure 35 - Simulation of Available Gain. (Page 24)
Figure 36 - Simulation of Transducer Gain. (Page 24)
Figure 37 - Simulation of input impedance. (Page 25)
Figure 38 - Simulation of reflection coefficient (S11 and S22). (Page 25)
Figure 39 - Simulation of adjacent channel and image frequency rejection concerning
the available gain. (Page 25)
Figure 40 - Simulation of Noise Figure. (Page 26)

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7. CONCLUSION

In summary, this project has four distinct phases and each with equal importance.
The first phase consisted in the implementation of LNA (Schematic, Layout, and due
simulations), a second stage went up the implementation of the VCO (Schematic,
Layout, and due simulations), a third phase was elaborated the last block, the Mixer
(Schematic, Layout and due simulations) and finally, a fourth phase has joined the
previously mentioned 3 blocks with the purpose of preparing the Receiver Front End.
In relation to design of LNA for 3.5GHz application, it is concluded that the results
obtained by simulation it is possible to design a LNA with specification of consumption
and noise pre-determined with satisfactory results. One of the challenges of this stage of
the LNA is the insertion of the inductor can limit the performance of the circuit and the
predetermined specifications. The insertion of the inductor imposes the need for an
adjustment to the amplifier due to its capacitance and resistance of the substrate, causing
a decrease of the transistor to reset the wedding and achieve better performance against
noise. However, this reduction results in a loss of gain while decreasing power
consumption. The designed circuit has achieved satisfactory results in terms of power
consumption, noise and marriage in the input and output. The noise factor was 4.6dB.
The spreading factor at the input (S11) is 1.3dBm while referring to S22 simulation
shows that never attains the value zero confirming the good stability of the circuit, being
a good input and output impedance matching. Finally, the LNA has a rather good gain
with the value of 21dB.
A voltage-controlled oscillator or VCO is an electronic oscillator whose oscillation
frequency is controlled by a voltage input. The applied input voltage determines the
instantaneous oscillation frequency. Due to the good phase noise basic performances
and ease of implementation in the CMOS process, LC oscillators with differential and
cross-coupled topology are among the more frequently used circuital primitives. The
results of the simulations were created to meet expectations. In relation to the output
voltage in the time domain, the VCO has a good response as evidenced by reading the
graph shown. With regard to the phase noise performance, it is notable for the frequency
of 1MHz for example, the spacing of the lines has a value of 2dBc / Hz.
The mixer was the last block to be realized. It was shown good performance due to
the same number of simulations performed. The mixer has developed a power
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consumption of 1.34 mW and the analyzed values of the gains were within the desired
range. The simulations were made to Mixer by pss analysis, and analysis of the psp.
As the end stage of the project joined the three blocks made elaborating the
respective schematic and appropriate simulations. It was concluded that the values are
not in accordance with reality is impossible to design the receiver professionally.
The last simulation shown power consumption of the three individual blocks and
final receiver.
This project was quite useful because it allowed acquiring varied skills level
microelectronics. Although the project is designed not worthy of designing in real life,
was very rewarding for the group carry out the entire project, with some difficulty, but
with a huge learning about the tools.

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Microelectronics Telecommunications

Project Front-End Receiver"

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